1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsDirectObjLower.h"
17 #include "MCTargetDesc/MipsFixupKinds.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/Support/raw_ostream.h"
32 class MipsMCCodeEmitter : public MCCodeEmitter {
33 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
34 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 const MCInstrInfo &MCII;
39 MipsMCCodeEmitter(const MCInstrInfo &mcii, bool IsLittle) :
40 MCII(mcii), IsLittleEndian(IsLittle) {}
42 ~MipsMCCodeEmitter() {}
44 void EmitByte(unsigned char C, raw_ostream &OS) const {
48 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
49 // Output the instruction encoding in little endian byte order.
50 for (unsigned i = 0; i < Size; ++i) {
51 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
52 EmitByte((Val >> Shift) & 0xff, OS);
56 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
57 SmallVectorImpl<MCFixup> &Fixups) const;
59 // getBinaryCodeForInstr - TableGen'erated function for getting the
60 // binary encoding for an instruction.
61 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 SmallVectorImpl<MCFixup> &Fixups) const;
64 // getBranchJumpOpValue - Return binary encoding of the jump
65 // target operand. If the machine operand requires relocation,
66 // record the relocation and return zero.
67 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
68 SmallVectorImpl<MCFixup> &Fixups) const;
70 // getBranchTargetOpValue - Return binary encoding of the branch
71 // target operand. If the machine operand requires relocation,
72 // record the relocation and return zero.
73 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
74 SmallVectorImpl<MCFixup> &Fixups) const;
76 // getMachineOpValue - Return binary encoding of operand. If the machin
77 // operand requires relocation, record the relocation and return zero.
78 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
79 SmallVectorImpl<MCFixup> &Fixups) const;
81 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
82 SmallVectorImpl<MCFixup> &Fixups) const;
83 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl<MCFixup> &Fixups) const;
85 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 }; // class MipsMCCodeEmitter
91 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
92 const MCRegisterInfo &MRI,
93 const MCSubtargetInfo &STI,
96 return new MipsMCCodeEmitter(MCII, false);
99 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
100 const MCRegisterInfo &MRI,
101 const MCSubtargetInfo &STI,
104 return new MipsMCCodeEmitter(MCII, true);
107 /// EncodeInstruction - Emit the instruction.
108 /// Size the instruction (currently only 4 bytes
109 void MipsMCCodeEmitter::
110 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const
114 // Non-pseudo instructions that get changed for direct object
115 // only based on operand values.
116 // If this list of instructions get much longer we will move
117 // the check to a function call. Until then, this is more efficient.
119 switch (MI.getOpcode()) {
120 // If shift amount is >= 32 it the inst needs to be lowered further
124 Mips::LowerLargeShift(TmpInst);
126 // Double extract instruction is chosen by pos and size operands
129 Mips::LowerDextDins(TmpInst);
132 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
134 // Check for unimplemented opcodes.
135 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
136 // so we have to special check for them.
137 unsigned Opcode = TmpInst.getOpcode();
138 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
139 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
141 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
142 uint64_t TSFlags = Desc.TSFlags;
144 // Pseudo instructions don't get encoded and shouldn't be here
145 // in the first place!
146 if ((TSFlags & MipsII::FormMask) == MipsII::Pseudo)
147 llvm_unreachable("Pseudo opcode found in EncodeInstruction()");
149 // For now all instructions are 4 bytes
150 int Size = 4; // FIXME: Have Desc.getSize() return the correct value!
152 EmitInstruction(Binary, Size, OS);
155 /// getBranchTargetOpValue - Return binary encoding of the branch
156 /// target operand. If the machine operand requires relocation,
157 /// record the relocation and return zero.
158 unsigned MipsMCCodeEmitter::
159 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
160 SmallVectorImpl<MCFixup> &Fixups) const {
162 const MCOperand &MO = MI.getOperand(OpNo);
164 // If the destination is an immediate, we have nothing to do.
165 if (MO.isImm()) return MO.getImm();
166 assert(MO.isExpr() &&
167 "getBranchTargetOpValue expects only expressions or immediates");
169 const MCExpr *Expr = MO.getExpr();
170 Fixups.push_back(MCFixup::Create(0, Expr,
171 MCFixupKind(Mips::fixup_Mips_PC16)));
175 /// getJumpTargetOpValue - Return binary encoding of the jump
176 /// target operand. If the machine operand requires relocation,
177 /// record the relocation and return zero.
178 unsigned MipsMCCodeEmitter::
179 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
180 SmallVectorImpl<MCFixup> &Fixups) const {
182 const MCOperand &MO = MI.getOperand(OpNo);
183 // If the destination is an immediate, we have nothing to do.
184 if (MO.isImm()) return MO.getImm();
185 assert(MO.isExpr() &&
186 "getJumpTargetOpValue expects only expressions or an immediate");
188 const MCExpr *Expr = MO.getExpr();
189 Fixups.push_back(MCFixup::Create(0, Expr,
190 MCFixupKind(Mips::fixup_Mips_26)));
194 /// getMachineOpValue - Return binary encoding of operand. If the machine
195 /// operand requires relocation, record the relocation and return zero.
196 unsigned MipsMCCodeEmitter::
197 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
198 SmallVectorImpl<MCFixup> &Fixups) const {
200 unsigned Reg = MO.getReg();
201 unsigned RegNo = getMipsRegisterNumbering(Reg);
203 } else if (MO.isImm()) {
204 return static_cast<unsigned>(MO.getImm());
205 } else if (MO.isFPImm()) {
206 return static_cast<unsigned>(APFloat(MO.getFPImm())
207 .bitcastToAPInt().getHiBits(32).getLimitedValue());
210 // MO must be an Expr.
213 const MCExpr *Expr = MO.getExpr();
214 MCExpr::ExprKind Kind = Expr->getKind();
216 if (Kind == MCExpr::Binary) {
217 Expr = static_cast<const MCBinaryExpr*>(Expr)->getLHS();
218 Kind = Expr->getKind();
221 assert (Kind == MCExpr::SymbolRef);
223 Mips::Fixups FixupKind = Mips::Fixups(0);
225 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
226 default: llvm_unreachable("Unknown fixup kind!");
228 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
229 FixupKind = Mips::fixup_Mips_GPOFF_HI;
231 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
232 FixupKind = Mips::fixup_Mips_GPOFF_LO;
234 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
235 FixupKind = Mips::fixup_Mips_GOT_PAGE;
237 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
238 FixupKind = Mips::fixup_Mips_GOT_OFST;
240 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
241 FixupKind = Mips::fixup_Mips_GOT_DISP;
243 case MCSymbolRefExpr::VK_Mips_GPREL:
244 FixupKind = Mips::fixup_Mips_GPREL16;
246 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
247 FixupKind = Mips::fixup_Mips_CALL16;
249 case MCSymbolRefExpr::VK_Mips_GOT16:
250 FixupKind = Mips::fixup_Mips_GOT_Global;
252 case MCSymbolRefExpr::VK_Mips_GOT:
253 FixupKind = Mips::fixup_Mips_GOT_Local;
255 case MCSymbolRefExpr::VK_Mips_ABS_HI:
256 FixupKind = Mips::fixup_Mips_HI16;
258 case MCSymbolRefExpr::VK_Mips_ABS_LO:
259 FixupKind = Mips::fixup_Mips_LO16;
261 case MCSymbolRefExpr::VK_Mips_TLSGD:
262 FixupKind = Mips::fixup_Mips_TLSGD;
264 case MCSymbolRefExpr::VK_Mips_TLSLDM:
265 FixupKind = Mips::fixup_Mips_TLSLDM;
267 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
268 FixupKind = Mips::fixup_Mips_DTPREL_HI;
270 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
271 FixupKind = Mips::fixup_Mips_DTPREL_LO;
273 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
274 FixupKind = Mips::fixup_Mips_GOTTPREL;
276 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
277 FixupKind = Mips::fixup_Mips_TPREL_HI;
279 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
280 FixupKind = Mips::fixup_Mips_TPREL_LO;
282 case MCSymbolRefExpr::VK_Mips_HIGHER:
283 FixupKind = Mips::fixup_Mips_HIGHER;
285 case MCSymbolRefExpr::VK_Mips_HIGHEST:
286 FixupKind = Mips::fixup_Mips_HIGHEST;
290 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), MCFixupKind(FixupKind)));
292 // All of the information is in the fixup.
296 /// getMemEncoding - Return binary encoding of memory related operand.
297 /// If the offset operand requires relocation, record the relocation.
299 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
300 SmallVectorImpl<MCFixup> &Fixups) const {
301 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
302 assert(MI.getOperand(OpNo).isReg());
303 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
304 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
306 return (OffBits & 0xFFFF) | RegBits;
310 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
311 SmallVectorImpl<MCFixup> &Fixups) const {
312 assert(MI.getOperand(OpNo).isImm());
313 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
314 return SizeEncoding - 1;
317 // FIXME: should be called getMSBEncoding
320 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
321 SmallVectorImpl<MCFixup> &Fixups) const {
322 assert(MI.getOperand(OpNo-1).isImm());
323 assert(MI.getOperand(OpNo).isImm());
324 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
325 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
327 return Position + Size - 1;
330 #include "MipsGenMCCodeEmitter.inc"