1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsDirectObjLower.h"
17 #include "MCTargetDesc/MipsFixupKinds.h"
18 #include "MCTargetDesc/MipsMCTargetDesc.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstrInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/Support/raw_ostream.h"
33 class MipsMCCodeEmitter : public MCCodeEmitter {
34 MipsMCCodeEmitter(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
35 void operator=(const MipsMCCodeEmitter &) LLVM_DELETED_FUNCTION;
36 const MCInstrInfo &MCII;
41 MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_,
42 const MCSubtargetInfo &sti, bool IsLittle) :
43 MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {}
45 ~MipsMCCodeEmitter() {}
47 void EmitByte(unsigned char C, raw_ostream &OS) const {
51 void EmitInstruction(uint64_t Val, unsigned Size, raw_ostream &OS) const {
52 // Output the instruction encoding in little endian byte order.
53 for (unsigned i = 0; i < Size; ++i) {
54 unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
55 EmitByte((Val >> Shift) & 0xff, OS);
59 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
60 SmallVectorImpl<MCFixup> &Fixups) const;
62 // getBinaryCodeForInstr - TableGen'erated function for getting the
63 // binary encoding for an instruction.
64 uint64_t getBinaryCodeForInstr(const MCInst &MI,
65 SmallVectorImpl<MCFixup> &Fixups) const;
67 // getBranchJumpOpValue - Return binary encoding of the jump
68 // target operand. If the machine operand requires relocation,
69 // record the relocation and return zero.
70 unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
71 SmallVectorImpl<MCFixup> &Fixups) const;
73 // getBranchTargetOpValue - Return binary encoding of the branch
74 // target operand. If the machine operand requires relocation,
75 // record the relocation and return zero.
76 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
77 SmallVectorImpl<MCFixup> &Fixups) const;
79 // getMachineOpValue - Return binary encoding of operand. If the machin
80 // operand requires relocation, record the relocation and return zero.
81 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
82 SmallVectorImpl<MCFixup> &Fixups) const;
84 unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
85 SmallVectorImpl<MCFixup> &Fixups) const;
86 unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
87 SmallVectorImpl<MCFixup> &Fixups) const;
88 unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
89 SmallVectorImpl<MCFixup> &Fixups) const;
92 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const;
94 }; // class MipsMCCodeEmitter
97 MCCodeEmitter *llvm::createMipsMCCodeEmitterEB(const MCInstrInfo &MCII,
98 const MCRegisterInfo &MRI,
99 const MCSubtargetInfo &STI,
102 return new MipsMCCodeEmitter(MCII, Ctx, STI, false);
105 MCCodeEmitter *llvm::createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
106 const MCRegisterInfo &MRI,
107 const MCSubtargetInfo &STI,
110 return new MipsMCCodeEmitter(MCII, Ctx, STI, true);
113 /// EncodeInstruction - Emit the instruction.
114 /// Size the instruction (currently only 4 bytes
115 void MipsMCCodeEmitter::
116 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
117 SmallVectorImpl<MCFixup> &Fixups) const
120 // Non-pseudo instructions that get changed for direct object
121 // only based on operand values.
122 // If this list of instructions get much longer we will move
123 // the check to a function call. Until then, this is more efficient.
125 switch (MI.getOpcode()) {
126 // If shift amount is >= 32 it the inst needs to be lowered further
130 Mips::LowerLargeShift(TmpInst);
132 // Double extract instruction is chosen by pos and size operands
135 Mips::LowerDextDins(TmpInst);
138 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups);
140 // Check for unimplemented opcodes.
141 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
142 // so we have to special check for them.
143 unsigned Opcode = TmpInst.getOpcode();
144 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary)
145 llvm_unreachable("unimplemented opcode in EncodeInstruction()");
147 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
149 // Get byte count of instruction
150 unsigned Size = Desc.getSize();
152 llvm_unreachable("Desc.getSize() returns 0");
154 EmitInstruction(Binary, Size, OS);
157 /// getBranchTargetOpValue - Return binary encoding of the branch
158 /// target operand. If the machine operand requires relocation,
159 /// record the relocation and return zero.
160 unsigned MipsMCCodeEmitter::
161 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
162 SmallVectorImpl<MCFixup> &Fixups) const {
164 const MCOperand &MO = MI.getOperand(OpNo);
166 // If the destination is an immediate, divide by 4.
167 if (MO.isImm()) return MO.getImm() >> 2;
169 assert(MO.isExpr() &&
170 "getBranchTargetOpValue expects only expressions or immediates");
172 const MCExpr *Expr = MO.getExpr();
173 Fixups.push_back(MCFixup::Create(0, Expr,
174 MCFixupKind(Mips::fixup_Mips_PC16)));
178 /// getJumpTargetOpValue - Return binary encoding of the jump
179 /// target operand. If the machine operand requires relocation,
180 /// record the relocation and return zero.
181 unsigned MipsMCCodeEmitter::
182 getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
183 SmallVectorImpl<MCFixup> &Fixups) const {
185 const MCOperand &MO = MI.getOperand(OpNo);
186 // If the destination is an immediate, divide by 4.
187 if (MO.isImm()) return MO.getImm()>>2;
189 assert(MO.isExpr() &&
190 "getJumpTargetOpValue expects only expressions or an immediate");
192 const MCExpr *Expr = MO.getExpr();
193 Fixups.push_back(MCFixup::Create(0, Expr,
194 MCFixupKind(Mips::fixup_Mips_26)));
198 unsigned MipsMCCodeEmitter::
199 getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups) const {
202 if (Expr->EvaluateAsAbsolute(Res))
205 MCExpr::ExprKind Kind = Expr->getKind();
206 if (Kind == MCExpr::Constant) {
207 return cast<MCConstantExpr>(Expr)->getValue();
210 if (Kind == MCExpr::Binary) {
211 unsigned Res = getExprOpValue(cast<MCBinaryExpr>(Expr)->getLHS(), Fixups);
212 Res += getExprOpValue(cast<MCBinaryExpr>(Expr)->getRHS(), Fixups);
215 if (Kind == MCExpr::SymbolRef) {
216 Mips::Fixups FixupKind = Mips::Fixups(0);
218 switch(cast<MCSymbolRefExpr>(Expr)->getKind()) {
219 default: llvm_unreachable("Unknown fixup kind!");
221 case MCSymbolRefExpr::VK_Mips_GPOFF_HI :
222 FixupKind = Mips::fixup_Mips_GPOFF_HI;
224 case MCSymbolRefExpr::VK_Mips_GPOFF_LO :
225 FixupKind = Mips::fixup_Mips_GPOFF_LO;
227 case MCSymbolRefExpr::VK_Mips_GOT_PAGE :
228 FixupKind = Mips::fixup_Mips_GOT_PAGE;
230 case MCSymbolRefExpr::VK_Mips_GOT_OFST :
231 FixupKind = Mips::fixup_Mips_GOT_OFST;
233 case MCSymbolRefExpr::VK_Mips_GOT_DISP :
234 FixupKind = Mips::fixup_Mips_GOT_DISP;
236 case MCSymbolRefExpr::VK_Mips_GPREL:
237 FixupKind = Mips::fixup_Mips_GPREL16;
239 case MCSymbolRefExpr::VK_Mips_GOT_CALL:
240 FixupKind = Mips::fixup_Mips_CALL16;
242 case MCSymbolRefExpr::VK_Mips_GOT16:
243 FixupKind = Mips::fixup_Mips_GOT_Global;
245 case MCSymbolRefExpr::VK_Mips_GOT:
246 FixupKind = Mips::fixup_Mips_GOT_Local;
248 case MCSymbolRefExpr::VK_Mips_ABS_HI:
249 FixupKind = Mips::fixup_Mips_HI16;
251 case MCSymbolRefExpr::VK_Mips_ABS_LO:
252 FixupKind = Mips::fixup_Mips_LO16;
254 case MCSymbolRefExpr::VK_Mips_TLSGD:
255 FixupKind = Mips::fixup_Mips_TLSGD;
257 case MCSymbolRefExpr::VK_Mips_TLSLDM:
258 FixupKind = Mips::fixup_Mips_TLSLDM;
260 case MCSymbolRefExpr::VK_Mips_DTPREL_HI:
261 FixupKind = Mips::fixup_Mips_DTPREL_HI;
263 case MCSymbolRefExpr::VK_Mips_DTPREL_LO:
264 FixupKind = Mips::fixup_Mips_DTPREL_LO;
266 case MCSymbolRefExpr::VK_Mips_GOTTPREL:
267 FixupKind = Mips::fixup_Mips_GOTTPREL;
269 case MCSymbolRefExpr::VK_Mips_TPREL_HI:
270 FixupKind = Mips::fixup_Mips_TPREL_HI;
272 case MCSymbolRefExpr::VK_Mips_TPREL_LO:
273 FixupKind = Mips::fixup_Mips_TPREL_LO;
275 case MCSymbolRefExpr::VK_Mips_HIGHER:
276 FixupKind = Mips::fixup_Mips_HIGHER;
278 case MCSymbolRefExpr::VK_Mips_HIGHEST:
279 FixupKind = Mips::fixup_Mips_HIGHEST;
281 case MCSymbolRefExpr::VK_Mips_GOT_HI16:
282 FixupKind = Mips::fixup_Mips_GOT_HI16;
284 case MCSymbolRefExpr::VK_Mips_GOT_LO16:
285 FixupKind = Mips::fixup_Mips_GOT_LO16;
287 case MCSymbolRefExpr::VK_Mips_CALL_HI16:
288 FixupKind = Mips::fixup_Mips_CALL_HI16;
290 case MCSymbolRefExpr::VK_Mips_CALL_LO16:
291 FixupKind = Mips::fixup_Mips_CALL_LO16;
295 Fixups.push_back(MCFixup::Create(0, Expr, MCFixupKind(FixupKind)));
301 /// getMachineOpValue - Return binary encoding of operand. If the machine
302 /// operand requires relocation, record the relocation and return zero.
303 unsigned MipsMCCodeEmitter::
304 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
305 SmallVectorImpl<MCFixup> &Fixups) const {
307 unsigned Reg = MO.getReg();
308 unsigned RegNo = Ctx.getRegisterInfo().getEncodingValue(Reg);
310 } else if (MO.isImm()) {
311 return static_cast<unsigned>(MO.getImm());
312 } else if (MO.isFPImm()) {
313 return static_cast<unsigned>(APFloat(MO.getFPImm())
314 .bitcastToAPInt().getHiBits(32).getLimitedValue());
316 // MO must be an Expr.
318 return getExprOpValue(MO.getExpr(),Fixups);
321 /// getMemEncoding - Return binary encoding of memory related operand.
322 /// If the offset operand requires relocation, record the relocation.
324 MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo,
325 SmallVectorImpl<MCFixup> &Fixups) const {
326 // Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
327 assert(MI.getOperand(OpNo).isReg());
328 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
329 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
331 return (OffBits & 0xFFFF) | RegBits;
335 MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo,
336 SmallVectorImpl<MCFixup> &Fixups) const {
337 assert(MI.getOperand(OpNo).isImm());
338 unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
339 return SizeEncoding - 1;
342 // FIXME: should be called getMSBEncoding
345 MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo,
346 SmallVectorImpl<MCFixup> &Fixups) const {
347 assert(MI.getOperand(OpNo-1).isImm());
348 assert(MI.getOperand(OpNo).isImm());
349 unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups);
350 unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups);
352 return Position + Size - 1;
355 #include "MipsGenMCCodeEmitter.inc"