1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MipsAsmBackend class.
12 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/MipsFixupKinds.h"
16 #include "MCTargetDesc/MipsAsmBackend.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "llvm/MC/MCAsmBackend.h"
19 #include "llvm/MC/MCAssembler.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCDirectives.h"
22 #include "llvm/MC/MCELFObjectWriter.h"
23 #include "llvm/MC/MCFixupKindInfo.h"
24 #include "llvm/MC/MCObjectWriter.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/raw_ostream.h"
32 // Prepare value for the target space for it
33 static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
34 MCContext *Ctx = nullptr) {
36 unsigned Kind = Fixup.getKind();
38 // Add/subtract and shift
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16:
55 case Mips::fixup_MICROMIPS_LO16:
56 case Mips::fixup_MICROMIPS_GOT_PAGE:
57 case Mips::fixup_MICROMIPS_GOT_OFST:
58 case Mips::fixup_MICROMIPS_GOT_DISP:
59 case Mips::fixup_MIPS_PCLO16:
61 case Mips::fixup_Mips_PC16:
62 // The displacement is then divided by 4 to give us an 18 bit
63 // address range. Forcing a signed division because Value can be negative.
64 Value = (int64_t)Value / 4;
65 // We now check if Value can be encoded as a 16-bit signed immediate.
66 if (!isIntN(16, Value) && Ctx)
67 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
69 case Mips::fixup_MIPS_PC19_S2:
70 // Forcing a signed division because Value can be negative.
71 Value = (int64_t)Value / 4;
72 // We now check if Value can be encoded as a 19-bit signed immediate.
73 if (!isIntN(19, Value) && Ctx)
74 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC19 fixup");
76 case Mips::fixup_Mips_26:
77 // So far we are only using this type for jumps.
78 // The displacement is then divided by 4 to give us an 28 bit
82 case Mips::fixup_Mips_HI16:
83 case Mips::fixup_Mips_GOT_Local:
84 case Mips::fixup_Mips_GOT_HI16:
85 case Mips::fixup_Mips_CALL_HI16:
86 case Mips::fixup_MICROMIPS_HI16:
87 case Mips::fixup_MIPS_PCHI16:
88 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1.
89 Value = ((Value + 0x8000) >> 16) & 0xffff;
91 case Mips::fixup_Mips_HIGHER:
92 // Get the 3rd 16-bits.
93 Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
95 case Mips::fixup_Mips_HIGHEST:
96 // Get the 4th 16-bits.
97 Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
99 case Mips::fixup_MICROMIPS_26_S1:
102 case Mips::fixup_MICROMIPS_PC7_S1:
104 // Forcing a signed division because Value can be negative.
105 Value = (int64_t) Value / 2;
106 // We now check if Value can be encoded as a 7-bit signed immediate.
107 if (!isIntN(7, Value) && Ctx)
108 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC7 fixup");
110 case Mips::fixup_MICROMIPS_PC10_S1:
112 // Forcing a signed division because Value can be negative.
113 Value = (int64_t) Value / 2;
114 // We now check if Value can be encoded as a 10-bit signed immediate.
115 if (!isIntN(10, Value) && Ctx)
116 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC10 fixup");
118 case Mips::fixup_MICROMIPS_PC16_S1:
120 // Forcing a signed division because Value can be negative.
121 Value = (int64_t)Value / 2;
122 // We now check if Value can be encoded as a 16-bit signed immediate.
123 if (!isIntN(16, Value) && Ctx)
124 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC16 fixup");
126 case Mips::fixup_MIPS_PC18_S3:
127 // Forcing a signed division because Value can be negative.
128 Value = (int64_t)Value / 8;
129 // We now check if Value can be encoded as a 18-bit signed immediate.
130 if (!isIntN(18, Value) && Ctx)
131 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC18 fixup");
133 case Mips::fixup_MIPS_PC21_S2:
134 // Forcing a signed division because Value can be negative.
135 Value = (int64_t) Value / 4;
136 // We now check if Value can be encoded as a 21-bit signed immediate.
137 if (!isIntN(21, Value) && Ctx)
138 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC21 fixup");
140 case Mips::fixup_MIPS_PC26_S2:
141 // Forcing a signed division because Value can be negative.
142 Value = (int64_t) Value / 4;
143 // We now check if Value can be encoded as a 26-bit signed immediate.
144 if (!isIntN(26, Value) && Ctx)
145 Ctx->reportFatalError(Fixup.getLoc(), "out of range PC26 fixup");
153 MipsAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
154 return createMipsELFObjectWriter(OS,
155 MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
158 // Little-endian fixup data byte ordering:
159 // mips32r2: a | b | x | x
160 // microMIPS: x | x | a | b
162 static bool needsMMLEByteOrder(unsigned Kind) {
163 return Kind != Mips::fixup_MICROMIPS_PC10_S1 &&
164 Kind >= Mips::fixup_MICROMIPS_26_S1 &&
165 Kind < Mips::LastTargetFixupKind;
168 // Calculate index for microMIPS specific little endian byte order
169 static unsigned calculateMMLEIndex(unsigned i) {
170 assert(i <= 3 && "Index out of range!");
172 return (1 - i / 2) * 2 + i % 2;
175 /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
176 /// data fragment, at the offset specified by the fixup and following the
177 /// fixup kind as appropriate.
178 void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
179 unsigned DataSize, uint64_t Value,
180 bool IsPCRel) const {
181 MCFixupKind Kind = Fixup.getKind();
182 Value = adjustFixupValue(Fixup, Value);
185 return; // Doesn't change encoding.
187 // Where do we start in the object
188 unsigned Offset = Fixup.getOffset();
189 // Number of bytes we need to fixup
190 unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
191 // Used to point to big endian bytes
194 switch ((unsigned)Kind) {
196 case Mips::fixup_Mips_16:
197 case Mips::fixup_MICROMIPS_PC10_S1:
201 case Mips::fixup_Mips_64:
210 // Grab current value, if any, from bits.
213 bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind);
215 for (unsigned i = 0; i != NumBytes; ++i) {
216 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
218 : (FullSize - 1 - i);
219 CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
222 uint64_t Mask = ((uint64_t)(-1) >>
223 (64 - getFixupKindInfo(Kind).TargetSize));
224 CurVal |= Value & Mask;
226 // Write out the fixed up bytes back to the code/data bits.
227 for (unsigned i = 0; i != NumBytes; ++i) {
228 unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i)
230 : (FullSize - 1 - i);
231 Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
235 const MCFixupKindInfo &MipsAsmBackend::
236 getFixupKindInfo(MCFixupKind Kind) const {
237 const static MCFixupKindInfo LittleEndianInfos[Mips::NumTargetFixupKinds] = {
238 // This table *must* be in same the order of fixup_* kinds in
241 // name offset bits flags
242 { "fixup_Mips_16", 0, 16, 0 },
243 { "fixup_Mips_32", 0, 32, 0 },
244 { "fixup_Mips_REL32", 0, 32, 0 },
245 { "fixup_Mips_26", 0, 26, 0 },
246 { "fixup_Mips_HI16", 0, 16, 0 },
247 { "fixup_Mips_LO16", 0, 16, 0 },
248 { "fixup_Mips_GPREL16", 0, 16, 0 },
249 { "fixup_Mips_LITERAL", 0, 16, 0 },
250 { "fixup_Mips_GOT_Global", 0, 16, 0 },
251 { "fixup_Mips_GOT_Local", 0, 16, 0 },
252 { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
253 { "fixup_Mips_CALL16", 0, 16, 0 },
254 { "fixup_Mips_GPREL32", 0, 32, 0 },
255 { "fixup_Mips_SHIFT5", 6, 5, 0 },
256 { "fixup_Mips_SHIFT6", 6, 5, 0 },
257 { "fixup_Mips_64", 0, 64, 0 },
258 { "fixup_Mips_TLSGD", 0, 16, 0 },
259 { "fixup_Mips_GOTTPREL", 0, 16, 0 },
260 { "fixup_Mips_TPREL_HI", 0, 16, 0 },
261 { "fixup_Mips_TPREL_LO", 0, 16, 0 },
262 { "fixup_Mips_TLSLDM", 0, 16, 0 },
263 { "fixup_Mips_DTPREL_HI", 0, 16, 0 },
264 { "fixup_Mips_DTPREL_LO", 0, 16, 0 },
265 { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
266 { "fixup_Mips_GPOFF_HI", 0, 16, 0 },
267 { "fixup_Mips_GPOFF_LO", 0, 16, 0 },
268 { "fixup_Mips_GOT_PAGE", 0, 16, 0 },
269 { "fixup_Mips_GOT_OFST", 0, 16, 0 },
270 { "fixup_Mips_GOT_DISP", 0, 16, 0 },
271 { "fixup_Mips_HIGHER", 0, 16, 0 },
272 { "fixup_Mips_HIGHEST", 0, 16, 0 },
273 { "fixup_Mips_GOT_HI16", 0, 16, 0 },
274 { "fixup_Mips_GOT_LO16", 0, 16, 0 },
275 { "fixup_Mips_CALL_HI16", 0, 16, 0 },
276 { "fixup_Mips_CALL_LO16", 0, 16, 0 },
277 { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
278 { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
279 { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
280 { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
281 { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
282 { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
283 { "fixup_MICROMIPS_26_S1", 0, 26, 0 },
284 { "fixup_MICROMIPS_HI16", 0, 16, 0 },
285 { "fixup_MICROMIPS_LO16", 0, 16, 0 },
286 { "fixup_MICROMIPS_GOT16", 0, 16, 0 },
287 { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
288 { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
289 { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
290 { "fixup_MICROMIPS_CALL16", 0, 16, 0 },
291 { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
292 { "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
293 { "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
294 { "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
295 { "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
296 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
297 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
298 { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
299 { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
302 const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = {
303 // This table *must* be in same the order of fixup_* kinds in
306 // name offset bits flags
307 { "fixup_Mips_16", 16, 16, 0 },
308 { "fixup_Mips_32", 0, 32, 0 },
309 { "fixup_Mips_REL32", 0, 32, 0 },
310 { "fixup_Mips_26", 6, 26, 0 },
311 { "fixup_Mips_HI16", 16, 16, 0 },
312 { "fixup_Mips_LO16", 16, 16, 0 },
313 { "fixup_Mips_GPREL16", 16, 16, 0 },
314 { "fixup_Mips_LITERAL", 16, 16, 0 },
315 { "fixup_Mips_GOT_Global", 16, 16, 0 },
316 { "fixup_Mips_GOT_Local", 16, 16, 0 },
317 { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
318 { "fixup_Mips_CALL16", 16, 16, 0 },
319 { "fixup_Mips_GPREL32", 0, 32, 0 },
320 { "fixup_Mips_SHIFT5", 21, 5, 0 },
321 { "fixup_Mips_SHIFT6", 21, 5, 0 },
322 { "fixup_Mips_64", 0, 64, 0 },
323 { "fixup_Mips_TLSGD", 16, 16, 0 },
324 { "fixup_Mips_GOTTPREL", 16, 16, 0 },
325 { "fixup_Mips_TPREL_HI", 16, 16, 0 },
326 { "fixup_Mips_TPREL_LO", 16, 16, 0 },
327 { "fixup_Mips_TLSLDM", 16, 16, 0 },
328 { "fixup_Mips_DTPREL_HI", 16, 16, 0 },
329 { "fixup_Mips_DTPREL_LO", 16, 16, 0 },
330 { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
331 { "fixup_Mips_GPOFF_HI", 16, 16, 0 },
332 { "fixup_Mips_GPOFF_LO", 16, 16, 0 },
333 { "fixup_Mips_GOT_PAGE", 16, 16, 0 },
334 { "fixup_Mips_GOT_OFST", 16, 16, 0 },
335 { "fixup_Mips_GOT_DISP", 16, 16, 0 },
336 { "fixup_Mips_HIGHER", 16, 16, 0 },
337 { "fixup_Mips_HIGHEST", 16, 16, 0 },
338 { "fixup_Mips_GOT_HI16", 16, 16, 0 },
339 { "fixup_Mips_GOT_LO16", 16, 16, 0 },
340 { "fixup_Mips_CALL_HI16", 16, 16, 0 },
341 { "fixup_Mips_CALL_LO16", 16, 16, 0 },
342 { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
343 { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
344 { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
345 { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
346 { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
347 { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
348 { "fixup_MICROMIPS_26_S1", 6, 26, 0 },
349 { "fixup_MICROMIPS_HI16", 16, 16, 0 },
350 { "fixup_MICROMIPS_LO16", 16, 16, 0 },
351 { "fixup_MICROMIPS_GOT16", 16, 16, 0 },
352 { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
353 { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
354 { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
355 { "fixup_MICROMIPS_CALL16", 16, 16, 0 },
356 { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
357 { "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
358 { "fixup_MICROMIPS_GOT_OFST", 16, 16, 0 },
359 { "fixup_MICROMIPS_TLS_GD", 16, 16, 0 },
360 { "fixup_MICROMIPS_TLS_LDM", 16, 16, 0 },
361 { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 },
362 { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 },
363 { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 },
364 { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }
367 if (Kind < FirstTargetFixupKind)
368 return MCAsmBackend::getFixupKindInfo(Kind);
370 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
374 return LittleEndianInfos[Kind - FirstTargetFixupKind];
375 return BigEndianInfos[Kind - FirstTargetFixupKind];
378 /// WriteNopData - Write an (optimal) nop sequence of Count bytes
379 /// to the given output. If the target cannot generate such a sequence,
380 /// it should return an error.
382 /// \return - True on success.
383 bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
384 // Check for a less than instruction size number of bytes
385 // FIXME: 16 bit instructions are not handled yet here.
386 // We shouldn't be using a hard coded number for instruction size.
388 // If the count is not 4-byte aligned, we must be writing data into the text
389 // section (otherwise we have unaligned instructions, and thus have far
390 // bigger problems), so just write zeros instead.
391 OW->WriteZeros(Count);
395 /// processFixupValue - Target hook to process the literal value of a fixup
397 void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
398 const MCAsmLayout &Layout,
399 const MCFixup &Fixup,
400 const MCFragment *DF,
401 const MCValue &Target,
404 // At this point we'll ignore the value returned by adjustFixupValue as
405 // we are only checking if the fixup can be applied correctly. We have
406 // access to MCContext from here which allows us to report a fatal error
407 // with *possibly* a source code location.
408 (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
412 MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
413 const MCRegisterInfo &MRI,
414 const TargetTuple &TT,
416 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
420 MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
421 const MCRegisterInfo &MRI,
422 const TargetTuple &TT,
424 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
428 MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
429 const MCRegisterInfo &MRI,
430 const TargetTuple &TT,
432 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
435 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
436 const MCRegisterInfo &MRI,
437 const TargetTuple &TT,
439 return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,