lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  61       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  62     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  63   }
  64
  65   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  66   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  67   bool hasMips32r6() const {
  68     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  69   }
  70
  71   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  72
  73   bool hasCOP3() const {
  74     // Only present in MIPS-I and MIPS-II
  75     return !hasMips32() && !hasMips3();
  76   }
  77
  78   /// getInstruction - See MCDisassembler.
  79   DecodeStatus getInstruction(MCInst &instr,
  80                               uint64_t &size,
  81                               const MemoryObject &region,
  82                               uint64_t address,
  83                               raw_ostream &vStream,
  84                               raw_ostream &cStream) const override;
  85 };
  86
  87
  88 /// Mips64Disassembler - a disasembler class for Mips64.
  89 class Mips64Disassembler : public MipsDisassemblerBase {
  90 public:
  91   /// Constructor     - Initializes the disassembler.
  92   ///
  93   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  94                      bool bigEndian) :
  95     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  96
  97   /// getInstruction - See MCDisassembler.
  98   DecodeStatus getInstruction(MCInst &instr,
  99                               uint64_t &size,
 100                               const MemoryObject &region,
 101                               uint64_t address,
 102                               raw_ostream &vStream,
 103                               raw_ostream &cStream) const override;
 104 };
 105
 106 } // end anonymous namespace
 107
 108 // Forward declare these because the autogenerated code will reference them.
 109 // Definitions are further down.
 110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 111                                              unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114
 115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 116                                                  unsigned RegNo,
 117                                                  uint64_t Address,
 118                                                  const void *Decoder);
 119
 120 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 121                                                unsigned RegNo,
 122                                                uint64_t Address,
 123                                                const void *Decoder);
 124
 125 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 126                                              unsigned RegNo,
 127                                              uint64_t Address,
 128                                              const void *Decoder);
 129
 130 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 131                                            unsigned Insn,
 132                                            uint64_t Address,
 133                                            const void *Decoder);
 134
 135 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 136                                             unsigned RegNo,
 137                                             uint64_t Address,
 138                                             const void *Decoder);
 139
 140 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 141                                              unsigned RegNo,
 142                                              uint64_t Address,
 143                                              const void *Decoder);
 144
 145 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 146                                              unsigned RegNo,
 147                                              uint64_t Address,
 148                                              const void *Decoder);
 149
 150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 151                                            unsigned RegNo,
 152                                            uint64_t Address,
 153                                            const void *Decoder);
 154
 155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 156                                            unsigned RegNo,
 157                                            uint64_t Address,
 158                                            const void *Decoder);
 159
 160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 161                                              uint64_t Address,
 162                                              const void *Decoder);
 163
 164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 165                                               unsigned Insn,
 166                                               uint64_t Address,
 167                                               const void *Decoder);
 168
 169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 170                                               unsigned RegNo,
 171                                               uint64_t Address,
 172                                               const void *Decoder);
 173
 174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 175                                                 unsigned RegNo,
 176                                                 uint64_t Address,
 177                                                 const void *Decoder);
 178
 179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 180                                                unsigned RegNo,
 181                                                uint64_t Address,
 182                                                const void *Decoder);
 183
 184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 185                                                unsigned RegNo,
 186                                                uint64_t Address,
 187                                                const void *Decoder);
 188
 189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 190                                                unsigned RegNo,
 191                                                uint64_t Address,
 192                                                const void *Decoder);
 193
 194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 195                                                unsigned RegNo,
 196                                                uint64_t Address,
 197                                                const void *Decoder);
 198
 199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 200                                                unsigned RegNo,
 201                                                uint64_t Address,
 202                                                const void *Decoder);
 203
 204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 205                                                unsigned RegNo,
 206                                                uint64_t Address,
 207                                                const void *Decoder);
 208
 209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 210                                                unsigned RegNo,
 211                                                uint64_t Address,
 212                                                const void *Decoder);
 213
 214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 215                                             unsigned RegNo,
 216                                             uint64_t Address,
 217                                             const void *Decoder);
 218
 219 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 220                                        unsigned Offset,
 221                                        uint64_t Address,
 222                                        const void *Decoder);
 223
 224 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 225                                      unsigned Insn,
 226                                      uint64_t Address,
 227                                      const void *Decoder);
 228
 229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 235                                          unsigned Offset,
 236                                          uint64_t Address,
 237                                          const void *Decoder);
 238
 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 240 // shifted left by 1 bit.
 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 242                                          unsigned Offset,
 243                                          uint64_t Address,
 244                                          const void *Decoder);
 245
 246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 247 // shifted left by 1 bit.
 248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 249                                        unsigned Insn,
 250                                        uint64_t Address,
 251                                        const void *Decoder);
 252
 253 static DecodeStatus DecodeMem(MCInst &Inst,
 254                               unsigned Insn,
 255                               uint64_t Address,
 256                               const void *Decoder);
 257
 258 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 259                               unsigned Insn,
 260                               uint64_t Address,
 261                               const void *Decoder);
 262
 263 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 264                                     uint64_t Address, const void *Decoder);
 265
 266 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 267                                      unsigned Insn,
 268                                      uint64_t Address,
 269                                      const void *Decoder);
 270
 271 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 272                                      unsigned Insn,
 273                                      uint64_t Address,
 274                                      const void *Decoder);
 275
 276 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 277                                uint64_t Address,
 278                                const void *Decoder);
 279
 280 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 281                                uint64_t Address,
 282                                const void *Decoder);
 283
 284 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 285                                uint64_t Address,
 286                                const void *Decoder);
 287
 288 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 289                                        unsigned Insn,
 290                                        uint64_t Address,
 291                                        const void *Decoder);
 292
 293 static DecodeStatus DecodeSimm16(MCInst &Inst,
 294                                  unsigned Insn,
 295                                  uint64_t Address,
 296                                  const void *Decoder);
 297
 298 // Decode the immediate field of an LSA instruction which
 299 // is off by one.
 300 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 301                                  unsigned Insn,
 302                                  uint64_t Address,
 303                                  const void *Decoder);
 304
 305 static DecodeStatus DecodeInsSize(MCInst &Inst,
 306                                   unsigned Insn,
 307                                   uint64_t Address,
 308                                   const void *Decoder);
 309
 310 static DecodeStatus DecodeExtSize(MCInst &Inst,
 311                                   unsigned Insn,
 312                                   uint64_t Address,
 313                                   const void *Decoder);
 314
 315 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 316                                      uint64_t Address, const void *Decoder);
 317
 318 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 319                                      uint64_t Address, const void *Decoder);
 320
 321 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 322 /// handle.
 323 template <typename InsnType>
 324 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 325                                    const void *Decoder);
 326
 327 template <typename InsnType>
 328 static DecodeStatus
 329 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 330                       const void *Decoder);
 331
 332 template <typename InsnType>
 333 static DecodeStatus
 334 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 335                        const void *Decoder);
 336
 337 template <typename InsnType>
 338 static DecodeStatus
 339 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 340                        const void *Decoder);
 341
 342 template <typename InsnType>
 343 static DecodeStatus
 344 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 345                        const void *Decoder);
 346
 347 template <typename InsnType>
 348 static DecodeStatus
 349 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 350                       const void *Decoder);
 351
 352 template <typename InsnType>
 353 static DecodeStatus
 354 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 355                        const void *Decoder);
 356
 357 namespace llvm {
 358 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 359               TheMips64elTarget;
 360 }
 361
 362 static MCDisassembler *createMipsDisassembler(
 363                        const Target &T,
 364                        const MCSubtargetInfo &STI,
 365                        MCContext &Ctx) {
 366   return new MipsDisassembler(STI, Ctx, true);
 367 }
 368
 369 static MCDisassembler *createMipselDisassembler(
 370                        const Target &T,
 371                        const MCSubtargetInfo &STI,
 372                        MCContext &Ctx) {
 373   return new MipsDisassembler(STI, Ctx, false);
 374 }
 375
 376 static MCDisassembler *createMips64Disassembler(
 377                        const Target &T,
 378                        const MCSubtargetInfo &STI,
 379                        MCContext &Ctx) {
 380   return new Mips64Disassembler(STI, Ctx, true);
 381 }
 382
 383 static MCDisassembler *createMips64elDisassembler(
 384                        const Target &T,
 385                        const MCSubtargetInfo &STI,
 386                        MCContext &Ctx) {
 387   return new Mips64Disassembler(STI, Ctx, false);
 388 }
 389
 390 extern "C" void LLVMInitializeMipsDisassembler() {
 391   // Register the disassembler.
 392   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 393                                          createMipsDisassembler);
 394   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 395                                          createMipselDisassembler);
 396   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 397                                          createMips64Disassembler);
 398   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 399                                          createMips64elDisassembler);
 400 }
 401
 402 #include "MipsGenDisassemblerTables.inc"
 403
 404 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 405   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 406   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 407   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 408 }
 409
 410 template <typename InsnType>
 411 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 412                                    const void *Decoder) {
 413   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 414   // The size of the n field depends on the element size
 415   // The register class also depends on this.
 416   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 417   unsigned NSize = 0;
 418   DecodeFN RegDecoder = nullptr;
 419   if ((tmp & 0x18) == 0x00) { // INSVE_B
 420     NSize = 4;
 421     RegDecoder = DecodeMSA128BRegisterClass;
 422   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 423     NSize = 3;
 424     RegDecoder = DecodeMSA128HRegisterClass;
 425   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 426     NSize = 2;
 427     RegDecoder = DecodeMSA128WRegisterClass;
 428   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 429     NSize = 1;
 430     RegDecoder = DecodeMSA128DRegisterClass;
 431   } else
 432     llvm_unreachable("Invalid encoding");
 433
 434   assert(NSize != 0 && RegDecoder != nullptr);
 435
 436   // $wd
 437   tmp = fieldFromInstruction(insn, 6, 5);
 438   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 439     return MCDisassembler::Fail;
 440   // $wd_in
 441   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 442     return MCDisassembler::Fail;
 443   // $n
 444   tmp = fieldFromInstruction(insn, 16, NSize);
 445   MI.addOperand(MCOperand::CreateImm(tmp));
 446   // $ws
 447   tmp = fieldFromInstruction(insn, 11, 5);
 448   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 449     return MCDisassembler::Fail;
 450   // $n2
 451   MI.addOperand(MCOperand::CreateImm(0));
 452
 453   return MCDisassembler::Success;
 454 }
 455
 456 template <typename InsnType>
 457 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 458                                           uint64_t Address,
 459                                           const void *Decoder) {
 460   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 461   // (otherwise we would have matched the ADDI instruction from the earlier
 462   // ISA's instead).
 463   //
 464   // We have:
 465   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 466   //      BOVC if rs >= rt
 467   //      BEQZALC if rs == 0 && rt != 0
 468   //      BEQC if rs < rt && rs != 0
 469
 470   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 471   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 472   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 473   bool HasRs = false;
 474
 475   if (Rs >= Rt) {
 476     MI.setOpcode(Mips::BOVC);
 477     HasRs = true;
 478   } else if (Rs != 0 && Rs < Rt) {
 479     MI.setOpcode(Mips::BEQC);
 480     HasRs = true;
 481   } else
 482     MI.setOpcode(Mips::BEQZALC);
 483
 484   if (HasRs)
 485     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 486                                        Rs)));
 487
 488   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 489                                      Rt)));
 490   MI.addOperand(MCOperand::CreateImm(Imm));
 491
 492   return MCDisassembler::Success;
 493 }
 494
 495 template <typename InsnType>
 496 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 497                                            uint64_t Address,
 498                                            const void *Decoder) {
 499   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 500   // (otherwise we would have matched the ADDI instruction from the earlier
 501   // ISA's instead).
 502   //
 503   // We have:
 504   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 505   //      BNVC if rs >= rt
 506   //      BNEZALC if rs == 0 && rt != 0
 507   //      BNEC if rs < rt && rs != 0
 508
 509   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 510   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 511   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 512   bool HasRs = false;
 513
 514   if (Rs >= Rt) {
 515     MI.setOpcode(Mips::BNVC);
 516     HasRs = true;
 517   } else if (Rs != 0 && Rs < Rt) {
 518     MI.setOpcode(Mips::BNEC);
 519     HasRs = true;
 520   } else
 521     MI.setOpcode(Mips::BNEZALC);
 522
 523   if (HasRs)
 524     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 525                                        Rs)));
 526
 527   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 528                                      Rt)));
 529   MI.addOperand(MCOperand::CreateImm(Imm));
 530
 531   return MCDisassembler::Success;
 532 }
 533
 534 template <typename InsnType>
 535 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 536                                            uint64_t Address,
 537                                            const void *Decoder) {
 538   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 539   // (otherwise we would have matched the BLEZL instruction from the earlier
 540   // ISA's instead).
 541   //
 542   // We have:
 543   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 544   //      Invalid if rs == 0
 545   //      BLEZC   if rs == 0  && rt != 0
 546   //      BGEZC   if rs == rt && rt != 0
 547   //      BGEC    if rs != rt && rs != 0  && rt != 0
 548
 549   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 550   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 551   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 552   bool HasRs = false;
 553
 554   if (Rt == 0)
 555     return MCDisassembler::Fail;
 556   else if (Rs == 0)
 557     MI.setOpcode(Mips::BLEZC);
 558   else if (Rs == Rt)
 559     MI.setOpcode(Mips::BGEZC);
 560   else {
 561     HasRs = true;
 562     MI.setOpcode(Mips::BGEC);
 563   }
 564
 565   if (HasRs)
 566     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 567                                        Rs)));
 568
 569   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 570                                      Rt)));
 571
 572   MI.addOperand(MCOperand::CreateImm(Imm));
 573
 574   return MCDisassembler::Success;
 575 }
 576
 577 template <typename InsnType>
 578 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 579                                            uint64_t Address,
 580                                            const void *Decoder) {
 581   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 582   // (otherwise we would have matched the BGTZL instruction from the earlier
 583   // ISA's instead).
 584   //
 585   // We have:
 586   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 587   //      Invalid if rs == 0
 588   //      BGTZC   if rs == 0  && rt != 0
 589   //      BLTZC   if rs == rt && rt != 0
 590   //      BLTC    if rs != rt && rs != 0  && rt != 0
 591
 592   bool HasRs = false;
 593
 594   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 595   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 596   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 597
 598   if (Rt == 0)
 599     return MCDisassembler::Fail;
 600   else if (Rs == 0)
 601     MI.setOpcode(Mips::BGTZC);
 602   else if (Rs == Rt)
 603     MI.setOpcode(Mips::BLTZC);
 604   else {
 605     MI.setOpcode(Mips::BLTC);
 606     HasRs = true;
 607   }
 608
 609   if (HasRs)
 610     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 611                                               Rs)));
 612
 613   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 614                                      Rt)));
 615
 616   MI.addOperand(MCOperand::CreateImm(Imm));
 617
 618   return MCDisassembler::Success;
 619 }
 620
 621 template <typename InsnType>
 622 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 623                                           uint64_t Address,
 624                                           const void *Decoder) {
 625   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 626   // (otherwise we would have matched the BGTZ instruction from the earlier
 627   // ISA's instead).
 628   //
 629   // We have:
 630   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 631   //      BGTZ    if rt == 0
 632   //      BGTZALC if rs == 0 && rt != 0
 633   //      BLTZALC if rs != 0 && rs == rt
 634   //      BLTUC   if rs != 0 && rs != rt
 635
 636   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 637   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 638   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 639   bool HasRs = false;
 640   bool HasRt = false;
 641
 642   if (Rt == 0) {
 643     MI.setOpcode(Mips::BGTZ);
 644     HasRs = true;
 645   } else if (Rs == 0) {
 646     MI.setOpcode(Mips::BGTZALC);
 647     HasRt = true;
 648   } else if (Rs == Rt) {
 649     MI.setOpcode(Mips::BLTZALC);
 650     HasRs = true;
 651   } else {
 652     MI.setOpcode(Mips::BLTUC);
 653     HasRs = true;
 654     HasRt = true;
 655   }
 656
 657   if (HasRs)
 658     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 659                                        Rs)));
 660
 661   if (HasRt)
 662     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 663                                        Rt)));
 664
 665   MI.addOperand(MCOperand::CreateImm(Imm));
 666
 667   return MCDisassembler::Success;
 668 }
 669
 670 template <typename InsnType>
 671 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 672                                            uint64_t Address,
 673                                            const void *Decoder) {
 674   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 675   // (otherwise we would have matched the BLEZL instruction from the earlier
 676   // ISA's instead).
 677   //
 678   // We have:
 679   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 680   //      Invalid   if rs == 0
 681   //      BLEZALC   if rs == 0  && rt != 0
 682   //      BGEZALC   if rs == rt && rt != 0
 683   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 684
 685   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 686   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 687   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 688   bool HasRs = false;
 689
 690   if (Rt == 0)
 691     return MCDisassembler::Fail;
 692   else if (Rs == 0)
 693     MI.setOpcode(Mips::BLEZALC);
 694   else if (Rs == Rt)
 695     MI.setOpcode(Mips::BGEZALC);
 696   else {
 697     HasRs = true;
 698     MI.setOpcode(Mips::BGEUC);
 699   }
 700
 701   if (HasRs)
 702     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 703                                        Rs)));
 704   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 705                                      Rt)));
 706
 707   MI.addOperand(MCOperand::CreateImm(Imm));
 708
 709   return MCDisassembler::Success;
 710 }
 711
 712   /// readInstruction - read four bytes from the MemoryObject
 713   /// and return 32 bit word sorted according to the given endianess
 714 static DecodeStatus readInstruction32(const MemoryObject &region,
 715                                       uint64_t address,
 716                                       uint64_t &size,
 717                                       uint32_t &insn,
 718                                       bool isBigEndian,
 719                                       bool IsMicroMips) {
 720   uint8_t Bytes[4];
 721
 722   // We want to read exactly 4 Bytes of data.
 723   if (region.readBytes(address, 4, Bytes) == -1) {
 724     size = 0;
 725     return MCDisassembler::Fail;
 726   }
 727
 728   if (isBigEndian) {
 729     // Encoded as a big-endian 32-bit word in the stream.
 730     insn = (Bytes[3] <<  0) |
 731            (Bytes[2] <<  8) |
 732            (Bytes[1] << 16) |
 733            (Bytes[0] << 24);
 734   }
 735   else {
 736     // Encoded as a small-endian 32-bit word in the stream.
 737     // Little-endian byte ordering:
 738     //   mips32r2:   4 | 3 | 2 | 1
 739     //   microMIPS:  2 | 1 | 4 | 3
 740     if (IsMicroMips) {
 741       insn = (Bytes[2] <<  0) |
 742              (Bytes[3] <<  8) |
 743              (Bytes[0] << 16) |
 744              (Bytes[1] << 24);
 745     } else {
 746       insn = (Bytes[0] <<  0) |
 747              (Bytes[1] <<  8) |
 748              (Bytes[2] << 16) |
 749              (Bytes[3] << 24);
 750     }
 751   }
 752
 753   return MCDisassembler::Success;
 754 }
 755
 756 DecodeStatus
 757 MipsDisassembler::getInstruction(MCInst &instr,
 758                                  uint64_t &Size,
 759                                  const MemoryObject &Region,
 760                                  uint64_t Address,
 761                                  raw_ostream &vStream,
 762                                  raw_ostream &cStream) const {
 763   uint32_t Insn;
 764
 765   DecodeStatus Result = readInstruction32(Region, Address, Size,
 766                                           Insn, isBigEndian, IsMicroMips);
 767   if (Result == MCDisassembler::Fail)
 768     return MCDisassembler::Fail;
 769
 770   if (IsMicroMips) {
 771     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 772     // Calling the auto-generated decoder function.
 773     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 774                                this, STI);
 775     if (Result != MCDisassembler::Fail) {
 776       Size = 4;
 777       return Result;
 778     }
 779     return MCDisassembler::Fail;
 780   }
 781
 782   if (hasCOP3()) {
 783     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 784     Result =
 785         decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
 786     if (Result != MCDisassembler::Fail) {
 787       Size = 4;
 788       return Result;
 789     }
 790   }
 791
 792   if (hasMips32r6() && isGP64()) {
 793     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 794     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 795                                Address, this, STI);
 796     if (Result != MCDisassembler::Fail) {
 797       Size = 4;
 798       return Result;
 799     }
 800   }
 801
 802   if (hasMips32r6()) {
 803     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 804     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 805                                Address, this, STI);
 806     if (Result != MCDisassembler::Fail) {
 807       Size = 4;
 808       return Result;
 809     }
 810   }
 811
 812   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 813   // Calling the auto-generated decoder function.
 814   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 815                              this, STI);
 816   if (Result != MCDisassembler::Fail) {
 817     Size = 4;
 818     return Result;
 819   }
 820
 821   return MCDisassembler::Fail;
 822 }
 823
 824 DecodeStatus
 825 Mips64Disassembler::getInstruction(MCInst &instr,
 826                                    uint64_t &Size,
 827                                    const MemoryObject &Region,
 828                                    uint64_t Address,
 829                                    raw_ostream &vStream,
 830                                    raw_ostream &cStream) const {
 831   uint32_t Insn;
 832
 833   DecodeStatus Result = readInstruction32(Region, Address, Size,
 834                                           Insn, isBigEndian, false);
 835   if (Result == MCDisassembler::Fail)
 836     return MCDisassembler::Fail;
 837
 838   // Calling the auto-generated decoder function.
 839   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 840                              this, STI);
 841   if (Result != MCDisassembler::Fail) {
 842     Size = 4;
 843     return Result;
 844   }
 845   // If we fail to decode in Mips64 decoder space we can try in Mips32
 846   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 847                              this, STI);
 848   if (Result != MCDisassembler::Fail) {
 849     Size = 4;
 850     return Result;
 851   }
 852
 853   return MCDisassembler::Fail;
 854 }
 855
 856 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 857                                                  unsigned RegNo,
 858                                                  uint64_t Address,
 859                                                  const void *Decoder) {
 860
 861   return MCDisassembler::Fail;
 862
 863 }
 864
 865 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 866                                              unsigned RegNo,
 867                                              uint64_t Address,
 868                                              const void *Decoder) {
 869
 870   if (RegNo > 31)
 871     return MCDisassembler::Fail;
 872
 873   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 874   Inst.addOperand(MCOperand::CreateReg(Reg));
 875   return MCDisassembler::Success;
 876 }
 877
 878 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 879                                                unsigned RegNo,
 880                                                uint64_t Address,
 881                                                const void *Decoder) {
 882   return MCDisassembler::Fail;
 883 }
 884
 885 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 886                                              unsigned RegNo,
 887                                              uint64_t Address,
 888                                              const void *Decoder) {
 889   if (RegNo > 31)
 890     return MCDisassembler::Fail;
 891   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 892   Inst.addOperand(MCOperand::CreateReg(Reg));
 893   return MCDisassembler::Success;
 894 }
 895
 896 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 897                                            unsigned RegNo,
 898                                            uint64_t Address,
 899                                            const void *Decoder) {
 900   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 901     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 902
 903   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 904 }
 905
 906 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 907                                             unsigned RegNo,
 908                                             uint64_t Address,
 909                                             const void *Decoder) {
 910   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 911 }
 912
 913 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 914                                              unsigned RegNo,
 915                                              uint64_t Address,
 916                                              const void *Decoder) {
 917   if (RegNo > 31)
 918     return MCDisassembler::Fail;
 919
 920   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 921   Inst.addOperand(MCOperand::CreateReg(Reg));
 922   return MCDisassembler::Success;
 923 }
 924
 925 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 926                                              unsigned RegNo,
 927                                              uint64_t Address,
 928                                              const void *Decoder) {
 929   if (RegNo > 31)
 930     return MCDisassembler::Fail;
 931
 932   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 933   Inst.addOperand(MCOperand::CreateReg(Reg));
 934   return MCDisassembler::Success;
 935 }
 936
 937 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 938                                            unsigned RegNo,
 939                                            uint64_t Address,
 940                                            const void *Decoder) {
 941   if (RegNo > 31)
 942     return MCDisassembler::Fail;
 943   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 944   Inst.addOperand(MCOperand::CreateReg(Reg));
 945   return MCDisassembler::Success;
 946 }
 947
 948 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 949                                            unsigned RegNo,
 950                                            uint64_t Address,
 951                                            const void *Decoder) {
 952   if (RegNo > 7)
 953     return MCDisassembler::Fail;
 954   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 955   Inst.addOperand(MCOperand::CreateReg(Reg));
 956   return MCDisassembler::Success;
 957 }
 958
 959 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 960                                              uint64_t Address,
 961                                              const void *Decoder) {
 962   if (RegNo > 31)
 963     return MCDisassembler::Fail;
 964
 965   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 966   Inst.addOperand(MCOperand::CreateReg(Reg));
 967   return MCDisassembler::Success;
 968 }
 969
 970 static DecodeStatus DecodeMem(MCInst &Inst,
 971                               unsigned Insn,
 972                               uint64_t Address,
 973                               const void *Decoder) {
 974   int Offset = SignExtend32<16>(Insn & 0xffff);
 975   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 976   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 977
 978   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 979   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 980
 981   if(Inst.getOpcode() == Mips::SC){
 982     Inst.addOperand(MCOperand::CreateReg(Reg));
 983   }
 984
 985   Inst.addOperand(MCOperand::CreateReg(Reg));
 986   Inst.addOperand(MCOperand::CreateReg(Base));
 987   Inst.addOperand(MCOperand::CreateImm(Offset));
 988
 989   return MCDisassembler::Success;
 990 }
 991
 992 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 993                               unsigned Insn,
 994                               uint64_t Address,
 995                               const void *Decoder) {
 996   int Offset = SignExtend32<16>(Insn & 0xffff);
 997   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
 998   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 999
1000   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1001
1002   Inst.addOperand(MCOperand::CreateReg(Base));
1003   Inst.addOperand(MCOperand::CreateImm(Offset));
1004   Inst.addOperand(MCOperand::CreateImm(Hint));
1005
1006   return MCDisassembler::Success;
1007 }
1008
1009 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1010                                     uint64_t Address, const void *Decoder) {
1011   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1012   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1013   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1014
1015   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1016   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1017
1018   Inst.addOperand(MCOperand::CreateReg(Reg));
1019   Inst.addOperand(MCOperand::CreateReg(Base));
1020
1021   // The immediate field of an LD/ST instruction is scaled which means it must
1022   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1023   // data format.
1024   // .b - 1 byte
1025   // .h - 2 bytes
1026   // .w - 4 bytes
1027   // .d - 8 bytes
1028   switch(Inst.getOpcode())
1029   {
1030   default:
1031     assert (0 && "Unexpected instruction");
1032     return MCDisassembler::Fail;
1033     break;
1034   case Mips::LD_B:
1035   case Mips::ST_B:
1036     Inst.addOperand(MCOperand::CreateImm(Offset));
1037     break;
1038   case Mips::LD_H:
1039   case Mips::ST_H:
1040     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1041     break;
1042   case Mips::LD_W:
1043   case Mips::ST_W:
1044     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1045     break;
1046   case Mips::LD_D:
1047   case Mips::ST_D:
1048     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1049     break;
1050   }
1051
1052   return MCDisassembler::Success;
1053 }
1054
1055 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1056                                      unsigned Insn,
1057                                      uint64_t Address,
1058                                      const void *Decoder) {
1059   int Offset = SignExtend32<12>(Insn & 0x0fff);
1060   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1061   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1062
1063   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1064   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1065
1066   if (Inst.getOpcode() == Mips::SC_MM)
1067     Inst.addOperand(MCOperand::CreateReg(Reg));
1068
1069   Inst.addOperand(MCOperand::CreateReg(Reg));
1070   Inst.addOperand(MCOperand::CreateReg(Base));
1071   Inst.addOperand(MCOperand::CreateImm(Offset));
1072
1073   return MCDisassembler::Success;
1074 }
1075
1076 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1077                                      unsigned Insn,
1078                                      uint64_t Address,
1079                                      const void *Decoder) {
1080   int Offset = SignExtend32<16>(Insn & 0xffff);
1081   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1082   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1083
1084   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1085   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1086
1087   Inst.addOperand(MCOperand::CreateReg(Reg));
1088   Inst.addOperand(MCOperand::CreateReg(Base));
1089   Inst.addOperand(MCOperand::CreateImm(Offset));
1090
1091   return MCDisassembler::Success;
1092 }
1093
1094 static DecodeStatus DecodeFMem(MCInst &Inst,
1095                                unsigned Insn,
1096                                uint64_t Address,
1097                                const void *Decoder) {
1098   int Offset = SignExtend32<16>(Insn & 0xffff);
1099   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1100   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1101
1102   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1103   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1104
1105   Inst.addOperand(MCOperand::CreateReg(Reg));
1106   Inst.addOperand(MCOperand::CreateReg(Base));
1107   Inst.addOperand(MCOperand::CreateImm(Offset));
1108
1109   return MCDisassembler::Success;
1110 }
1111
1112 static DecodeStatus DecodeFMem2(MCInst &Inst,
1113                                unsigned Insn,
1114                                uint64_t Address,
1115                                const void *Decoder) {
1116   int Offset = SignExtend32<16>(Insn & 0xffff);
1117   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1118   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1119
1120   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1121   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1122
1123   Inst.addOperand(MCOperand::CreateReg(Reg));
1124   Inst.addOperand(MCOperand::CreateReg(Base));
1125   Inst.addOperand(MCOperand::CreateImm(Offset));
1126
1127   return MCDisassembler::Success;
1128 }
1129
1130 static DecodeStatus DecodeFMem3(MCInst &Inst,
1131                                unsigned Insn,
1132                                uint64_t Address,
1133                                const void *Decoder) {
1134   int Offset = SignExtend32<16>(Insn & 0xffff);
1135   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1136   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1137
1138   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1139   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1140
1141   Inst.addOperand(MCOperand::CreateReg(Reg));
1142   Inst.addOperand(MCOperand::CreateReg(Base));
1143   Inst.addOperand(MCOperand::CreateImm(Offset));
1144
1145   return MCDisassembler::Success;
1146 }
1147
1148 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1149                                        unsigned Insn,
1150                                        uint64_t Address,
1151                                        const void *Decoder) {
1152   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1153   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1154   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1155
1156   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1157   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1158
1159   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1160     Inst.addOperand(MCOperand::CreateReg(Rt));
1161   }
1162
1163   Inst.addOperand(MCOperand::CreateReg(Rt));
1164   Inst.addOperand(MCOperand::CreateReg(Base));
1165   Inst.addOperand(MCOperand::CreateImm(Offset));
1166
1167   return MCDisassembler::Success;
1168 }
1169
1170 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1171                                               unsigned RegNo,
1172                                               uint64_t Address,
1173                                               const void *Decoder) {
1174   // Currently only hardware register 29 is supported.
1175   if (RegNo != 29)
1176     return  MCDisassembler::Fail;
1177   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1178   return MCDisassembler::Success;
1179 }
1180
1181 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1182                                               unsigned RegNo,
1183                                               uint64_t Address,
1184                                               const void *Decoder) {
1185   if (RegNo > 30 || RegNo %2)
1186     return MCDisassembler::Fail;
1187
1188   ;
1189   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1190   Inst.addOperand(MCOperand::CreateReg(Reg));
1191   return MCDisassembler::Success;
1192 }
1193
1194 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1195                                                 unsigned RegNo,
1196                                                 uint64_t Address,
1197                                                 const void *Decoder) {
1198   if (RegNo >= 4)
1199     return MCDisassembler::Fail;
1200
1201   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1202   Inst.addOperand(MCOperand::CreateReg(Reg));
1203   return MCDisassembler::Success;
1204 }
1205
1206 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1207                                                unsigned RegNo,
1208                                                uint64_t Address,
1209                                                const void *Decoder) {
1210   if (RegNo >= 4)
1211     return MCDisassembler::Fail;
1212
1213   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1214   Inst.addOperand(MCOperand::CreateReg(Reg));
1215   return MCDisassembler::Success;
1216 }
1217
1218 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1219                                                unsigned RegNo,
1220                                                uint64_t Address,
1221                                                const void *Decoder) {
1222   if (RegNo >= 4)
1223     return MCDisassembler::Fail;
1224
1225   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1226   Inst.addOperand(MCOperand::CreateReg(Reg));
1227   return MCDisassembler::Success;
1228 }
1229
1230 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1231                                                unsigned RegNo,
1232                                                uint64_t Address,
1233                                                const void *Decoder) {
1234   if (RegNo > 31)
1235     return MCDisassembler::Fail;
1236
1237   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1238   Inst.addOperand(MCOperand::CreateReg(Reg));
1239   return MCDisassembler::Success;
1240 }
1241
1242 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1243                                                unsigned RegNo,
1244                                                uint64_t Address,
1245                                                const void *Decoder) {
1246   if (RegNo > 31)
1247     return MCDisassembler::Fail;
1248
1249   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1250   Inst.addOperand(MCOperand::CreateReg(Reg));
1251   return MCDisassembler::Success;
1252 }
1253
1254 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1255                                                unsigned RegNo,
1256                                                uint64_t Address,
1257                                                const void *Decoder) {
1258   if (RegNo > 31)
1259     return MCDisassembler::Fail;
1260
1261   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1262   Inst.addOperand(MCOperand::CreateReg(Reg));
1263   return MCDisassembler::Success;
1264 }
1265
1266 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1267                                                unsigned RegNo,
1268                                                uint64_t Address,
1269                                                const void *Decoder) {
1270   if (RegNo > 31)
1271     return MCDisassembler::Fail;
1272
1273   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1274   Inst.addOperand(MCOperand::CreateReg(Reg));
1275   return MCDisassembler::Success;
1276 }
1277
1278 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1279                                                unsigned RegNo,
1280                                                uint64_t Address,
1281                                                const void *Decoder) {
1282   if (RegNo > 7)
1283     return MCDisassembler::Fail;
1284
1285   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1286   Inst.addOperand(MCOperand::CreateReg(Reg));
1287   return MCDisassembler::Success;
1288 }
1289
1290 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1291                                             unsigned RegNo,
1292                                             uint64_t Address,
1293                                             const void *Decoder) {
1294   if (RegNo > 31)
1295     return MCDisassembler::Fail;
1296
1297   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1298   Inst.addOperand(MCOperand::CreateReg(Reg));
1299   return MCDisassembler::Success;
1300 }
1301
1302 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1303                                        unsigned Offset,
1304                                        uint64_t Address,
1305                                        const void *Decoder) {
1306   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1307   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1308   return MCDisassembler::Success;
1309 }
1310
1311 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1312                                      unsigned Insn,
1313                                      uint64_t Address,
1314                                      const void *Decoder) {
1315
1316   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1317   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1318   return MCDisassembler::Success;
1319 }
1320
1321 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1322                                          unsigned Offset,
1323                                          uint64_t Address,
1324                                          const void *Decoder) {
1325   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1326
1327   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1328   return MCDisassembler::Success;
1329 }
1330
1331 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1332                                          unsigned Offset,
1333                                          uint64_t Address,
1334                                          const void *Decoder) {
1335   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1336
1337   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1338   return MCDisassembler::Success;
1339 }
1340
1341 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1342                                          unsigned Offset,
1343                                          uint64_t Address,
1344                                          const void *Decoder) {
1345   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1346   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1347   return MCDisassembler::Success;
1348 }
1349
1350 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1351                                        unsigned Insn,
1352                                        uint64_t Address,
1353                                        const void *Decoder) {
1354   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1355   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1356   return MCDisassembler::Success;
1357 }
1358
1359 static DecodeStatus DecodeSimm16(MCInst &Inst,
1360                                  unsigned Insn,
1361                                  uint64_t Address,
1362                                  const void *Decoder) {
1363   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1364   return MCDisassembler::Success;
1365 }
1366
1367 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1368                                  unsigned Insn,
1369                                  uint64_t Address,
1370                                  const void *Decoder) {
1371   // We add one to the immediate field as it was encoded as 'imm - 1'.
1372   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1373   return MCDisassembler::Success;
1374 }
1375
1376 static DecodeStatus DecodeInsSize(MCInst &Inst,
1377                                   unsigned Insn,
1378                                   uint64_t Address,
1379                                   const void *Decoder) {
1380   // First we need to grab the pos(lsb) from MCInst.
1381   int Pos = Inst.getOperand(2).getImm();
1382   int Size = (int) Insn - Pos + 1;
1383   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1384   return MCDisassembler::Success;
1385 }
1386
1387 static DecodeStatus DecodeExtSize(MCInst &Inst,
1388                                   unsigned Insn,
1389                                   uint64_t Address,
1390                                   const void *Decoder) {
1391   int Size = (int) Insn  + 1;
1392   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1393   return MCDisassembler::Success;
1394 }
1395
1396 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1397                                      uint64_t Address, const void *Decoder) {
1398   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1399   return MCDisassembler::Success;
1400 }
1401
1402 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1403                                      uint64_t Address, const void *Decoder) {
1404   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1405   return MCDisassembler::Success;
1406 }