lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  61       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  62     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  63   }
  64
  65   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  66   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  67   bool hasMips32r6() const {
  68     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  69   }
  70
  71   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  72
  73   bool hasCOP3() const {
  74     // Only present in MIPS-I and MIPS-II
  75     return !hasMips32() && !hasMips3();
  76   }
  77
  78   /// getInstruction - See MCDisassembler.
  79   DecodeStatus getInstruction(MCInst &instr,
  80                               uint64_t &size,
  81                               const MemoryObject &region,
  82                               uint64_t address,
  83                               raw_ostream &vStream,
  84                               raw_ostream &cStream) const override;
  85 };
  86
  87
  88 /// Mips64Disassembler - a disasembler class for Mips64.
  89 class Mips64Disassembler : public MipsDisassemblerBase {
  90 public:
  91   /// Constructor     - Initializes the disassembler.
  92   ///
  93   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  94                      bool bigEndian) :
  95     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  96
  97   /// getInstruction - See MCDisassembler.
  98   DecodeStatus getInstruction(MCInst &instr,
  99                               uint64_t &size,
 100                               const MemoryObject &region,
 101                               uint64_t address,
 102                               raw_ostream &vStream,
 103                               raw_ostream &cStream) const override;
 104 };
 105
 106 } // end anonymous namespace
 107
 108 // Forward declare these because the autogenerated code will reference them.
 109 // Definitions are further down.
 110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 111                                              unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114
 115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 116                                                  unsigned RegNo,
 117                                                  uint64_t Address,
 118                                                  const void *Decoder);
 119
 120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 121                                              unsigned RegNo,
 122                                              uint64_t Address,
 123                                              const void *Decoder);
 124
 125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 126                                            unsigned Insn,
 127                                            uint64_t Address,
 128                                            const void *Decoder);
 129
 130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 131                                             unsigned RegNo,
 132                                             uint64_t Address,
 133                                             const void *Decoder);
 134
 135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 136                                              unsigned RegNo,
 137                                              uint64_t Address,
 138                                              const void *Decoder);
 139
 140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 141                                              unsigned RegNo,
 142                                              uint64_t Address,
 143                                              const void *Decoder);
 144
 145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 146                                               unsigned RegNo,
 147                                               uint64_t Address,
 148                                               const void *Decoder);
 149
 150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 151                                            unsigned RegNo,
 152                                            uint64_t Address,
 153                                            const void *Decoder);
 154
 155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 156                                            unsigned RegNo,
 157                                            uint64_t Address,
 158                                            const void *Decoder);
 159
 160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 161                                              uint64_t Address,
 162                                              const void *Decoder);
 163
 164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 165                                               unsigned Insn,
 166                                               uint64_t Address,
 167                                               const void *Decoder);
 168
 169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 170                                               unsigned RegNo,
 171                                               uint64_t Address,
 172                                               const void *Decoder);
 173
 174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 175                                                 unsigned RegNo,
 176                                                 uint64_t Address,
 177                                                 const void *Decoder);
 178
 179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 180                                                unsigned RegNo,
 181                                                uint64_t Address,
 182                                                const void *Decoder);
 183
 184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 185                                                unsigned RegNo,
 186                                                uint64_t Address,
 187                                                const void *Decoder);
 188
 189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 190                                                unsigned RegNo,
 191                                                uint64_t Address,
 192                                                const void *Decoder);
 193
 194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 195                                                unsigned RegNo,
 196                                                uint64_t Address,
 197                                                const void *Decoder);
 198
 199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 200                                                unsigned RegNo,
 201                                                uint64_t Address,
 202                                                const void *Decoder);
 203
 204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 205                                                unsigned RegNo,
 206                                                uint64_t Address,
 207                                                const void *Decoder);
 208
 209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 210                                                unsigned RegNo,
 211                                                uint64_t Address,
 212                                                const void *Decoder);
 213
 214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 215                                             unsigned RegNo,
 216                                             uint64_t Address,
 217                                             const void *Decoder);
 218
 219 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 220                                        unsigned Offset,
 221                                        uint64_t Address,
 222                                        const void *Decoder);
 223
 224 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 225                                      unsigned Insn,
 226                                      uint64_t Address,
 227                                      const void *Decoder);
 228
 229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 235                                          unsigned Offset,
 236                                          uint64_t Address,
 237                                          const void *Decoder);
 238
 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 240 // shifted left by 1 bit.
 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 242                                          unsigned Offset,
 243                                          uint64_t Address,
 244                                          const void *Decoder);
 245
 246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 247 // shifted left by 1 bit.
 248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 249                                        unsigned Insn,
 250                                        uint64_t Address,
 251                                        const void *Decoder);
 252
 253 static DecodeStatus DecodeMem(MCInst &Inst,
 254                               unsigned Insn,
 255                               uint64_t Address,
 256                               const void *Decoder);
 257
 258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 259                                     uint64_t Address, const void *Decoder);
 260
 261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 262                                      unsigned Insn,
 263                                      uint64_t Address,
 264                                      const void *Decoder);
 265
 266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 267                                      unsigned Insn,
 268                                      uint64_t Address,
 269                                      const void *Decoder);
 270
 271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 272                                uint64_t Address,
 273                                const void *Decoder);
 274
 275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 276                                        unsigned Insn,
 277                                        uint64_t Address,
 278                                        const void *Decoder);
 279
 280 static DecodeStatus DecodeSimm16(MCInst &Inst,
 281                                  unsigned Insn,
 282                                  uint64_t Address,
 283                                  const void *Decoder);
 284
 285 // Decode the immediate field of an LSA instruction which
 286 // is off by one.
 287 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 288                                  unsigned Insn,
 289                                  uint64_t Address,
 290                                  const void *Decoder);
 291
 292 static DecodeStatus DecodeInsSize(MCInst &Inst,
 293                                   unsigned Insn,
 294                                   uint64_t Address,
 295                                   const void *Decoder);
 296
 297 static DecodeStatus DecodeExtSize(MCInst &Inst,
 298                                   unsigned Insn,
 299                                   uint64_t Address,
 300                                   const void *Decoder);
 301
 302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 303                                      uint64_t Address, const void *Decoder);
 304
 305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 306                                      uint64_t Address, const void *Decoder);
 307
 308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 309 /// handle.
 310 template <typename InsnType>
 311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 312                                    const void *Decoder);
 313
 314 template <typename InsnType>
 315 static DecodeStatus
 316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 317                       const void *Decoder);
 318
 319 template <typename InsnType>
 320 static DecodeStatus
 321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 322                        const void *Decoder);
 323
 324 template <typename InsnType>
 325 static DecodeStatus
 326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 327                        const void *Decoder);
 328
 329 template <typename InsnType>
 330 static DecodeStatus
 331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 332                        const void *Decoder);
 333
 334 template <typename InsnType>
 335 static DecodeStatus
 336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 337                       const void *Decoder);
 338
 339 template <typename InsnType>
 340 static DecodeStatus
 341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 342                        const void *Decoder);
 343
 344 namespace llvm {
 345 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 346               TheMips64elTarget;
 347 }
 348
 349 static MCDisassembler *createMipsDisassembler(
 350                        const Target &T,
 351                        const MCSubtargetInfo &STI,
 352                        MCContext &Ctx) {
 353   return new MipsDisassembler(STI, Ctx, true);
 354 }
 355
 356 static MCDisassembler *createMipselDisassembler(
 357                        const Target &T,
 358                        const MCSubtargetInfo &STI,
 359                        MCContext &Ctx) {
 360   return new MipsDisassembler(STI, Ctx, false);
 361 }
 362
 363 static MCDisassembler *createMips64Disassembler(
 364                        const Target &T,
 365                        const MCSubtargetInfo &STI,
 366                        MCContext &Ctx) {
 367   return new Mips64Disassembler(STI, Ctx, true);
 368 }
 369
 370 static MCDisassembler *createMips64elDisassembler(
 371                        const Target &T,
 372                        const MCSubtargetInfo &STI,
 373                        MCContext &Ctx) {
 374   return new Mips64Disassembler(STI, Ctx, false);
 375 }
 376
 377 extern "C" void LLVMInitializeMipsDisassembler() {
 378   // Register the disassembler.
 379   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 380                                          createMipsDisassembler);
 381   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 382                                          createMipselDisassembler);
 383   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 384                                          createMips64Disassembler);
 385   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 386                                          createMips64elDisassembler);
 387 }
 388
 389 #include "MipsGenDisassemblerTables.inc"
 390
 391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 392   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 393   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 394   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 395 }
 396
 397 template <typename InsnType>
 398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 399                                    const void *Decoder) {
 400   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 401   // The size of the n field depends on the element size
 402   // The register class also depends on this.
 403   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 404   unsigned NSize = 0;
 405   DecodeFN RegDecoder = nullptr;
 406   if ((tmp & 0x18) == 0x00) { // INSVE_B
 407     NSize = 4;
 408     RegDecoder = DecodeMSA128BRegisterClass;
 409   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 410     NSize = 3;
 411     RegDecoder = DecodeMSA128HRegisterClass;
 412   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 413     NSize = 2;
 414     RegDecoder = DecodeMSA128WRegisterClass;
 415   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 416     NSize = 1;
 417     RegDecoder = DecodeMSA128DRegisterClass;
 418   } else
 419     llvm_unreachable("Invalid encoding");
 420
 421   assert(NSize != 0 && RegDecoder != nullptr);
 422
 423   // $wd
 424   tmp = fieldFromInstruction(insn, 6, 5);
 425   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 426     return MCDisassembler::Fail;
 427   // $wd_in
 428   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 429     return MCDisassembler::Fail;
 430   // $n
 431   tmp = fieldFromInstruction(insn, 16, NSize);
 432   MI.addOperand(MCOperand::CreateImm(tmp));
 433   // $ws
 434   tmp = fieldFromInstruction(insn, 11, 5);
 435   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 436     return MCDisassembler::Fail;
 437   // $n2
 438   MI.addOperand(MCOperand::CreateImm(0));
 439
 440   return MCDisassembler::Success;
 441 }
 442
 443 template <typename InsnType>
 444 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 445                                           uint64_t Address,
 446                                           const void *Decoder) {
 447   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 448   // (otherwise we would have matched the ADDI instruction from the earlier
 449   // ISA's instead).
 450   //
 451   // We have:
 452   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 453   //      BOVC if rs >= rt
 454   //      BEQZALC if rs == 0 && rt != 0
 455   //      BEQC if rs < rt && rs != 0
 456
 457   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 458   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 459   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 460   bool HasRs = false;
 461
 462   if (Rs >= Rt) {
 463     MI.setOpcode(Mips::BOVC);
 464     HasRs = true;
 465   } else if (Rs != 0 && Rs < Rt) {
 466     MI.setOpcode(Mips::BEQC);
 467     HasRs = true;
 468   } else
 469     MI.setOpcode(Mips::BEQZALC);
 470
 471   if (HasRs)
 472     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 473                                        Rs)));
 474
 475   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 476                                      Rt)));
 477   MI.addOperand(MCOperand::CreateImm(Imm));
 478
 479   return MCDisassembler::Success;
 480 }
 481
 482 template <typename InsnType>
 483 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 484                                            uint64_t Address,
 485                                            const void *Decoder) {
 486   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 487   // (otherwise we would have matched the ADDI instruction from the earlier
 488   // ISA's instead).
 489   //
 490   // We have:
 491   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 492   //      BNVC if rs >= rt
 493   //      BNEZALC if rs == 0 && rt != 0
 494   //      BNEC if rs < rt && rs != 0
 495
 496   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 497   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 498   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 499   bool HasRs = false;
 500
 501   if (Rs >= Rt) {
 502     MI.setOpcode(Mips::BNVC);
 503     HasRs = true;
 504   } else if (Rs != 0 && Rs < Rt) {
 505     MI.setOpcode(Mips::BNEC);
 506     HasRs = true;
 507   } else
 508     MI.setOpcode(Mips::BNEZALC);
 509
 510   if (HasRs)
 511     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 512                                        Rs)));
 513
 514   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 515                                      Rt)));
 516   MI.addOperand(MCOperand::CreateImm(Imm));
 517
 518   return MCDisassembler::Success;
 519 }
 520
 521 template <typename InsnType>
 522 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 523                                            uint64_t Address,
 524                                            const void *Decoder) {
 525   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 526   // (otherwise we would have matched the BLEZL instruction from the earlier
 527   // ISA's instead).
 528   //
 529   // We have:
 530   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 531   //      Invalid if rs == 0
 532   //      BLEZC   if rs == 0  && rt != 0
 533   //      BGEZC   if rs == rt && rt != 0
 534   //      BGEC    if rs != rt && rs != 0  && rt != 0
 535
 536   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 537   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 538   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 539   bool HasRs = false;
 540
 541   if (Rt == 0)
 542     return MCDisassembler::Fail;
 543   else if (Rs == 0)
 544     MI.setOpcode(Mips::BLEZC);
 545   else if (Rs == Rt)
 546     MI.setOpcode(Mips::BGEZC);
 547   else {
 548     HasRs = true;
 549     MI.setOpcode(Mips::BGEC);
 550   }
 551
 552   if (HasRs)
 553     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 554                                        Rs)));
 555
 556   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 557                                      Rt)));
 558
 559   MI.addOperand(MCOperand::CreateImm(Imm));
 560
 561   return MCDisassembler::Success;
 562 }
 563
 564 template <typename InsnType>
 565 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 566                                            uint64_t Address,
 567                                            const void *Decoder) {
 568   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 569   // (otherwise we would have matched the BGTZL instruction from the earlier
 570   // ISA's instead).
 571   //
 572   // We have:
 573   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 574   //      Invalid if rs == 0
 575   //      BGTZC   if rs == 0  && rt != 0
 576   //      BLTZC   if rs == rt && rt != 0
 577   //      BLTC    if rs != rt && rs != 0  && rt != 0
 578
 579   bool HasRs = false;
 580
 581   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 582   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 583   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 584
 585   if (Rt == 0)
 586     return MCDisassembler::Fail;
 587   else if (Rs == 0)
 588     MI.setOpcode(Mips::BGTZC);
 589   else if (Rs == Rt)
 590     MI.setOpcode(Mips::BLTZC);
 591   else {
 592     MI.setOpcode(Mips::BLTC);
 593     HasRs = true;
 594   }
 595
 596   if (HasRs)
 597     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 598                                               Rs)));
 599
 600   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 601                                      Rt)));
 602
 603   MI.addOperand(MCOperand::CreateImm(Imm));
 604
 605   return MCDisassembler::Success;
 606 }
 607
 608 template <typename InsnType>
 609 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 610                                           uint64_t Address,
 611                                           const void *Decoder) {
 612   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 613   // (otherwise we would have matched the BGTZ instruction from the earlier
 614   // ISA's instead).
 615   //
 616   // We have:
 617   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 618   //      BGTZ    if rt == 0
 619   //      BGTZALC if rs == 0 && rt != 0
 620   //      BLTZALC if rs != 0 && rs == rt
 621   //      BLTUC   if rs != 0 && rs != rt
 622
 623   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 624   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 625   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 626   bool HasRs = false;
 627   bool HasRt = false;
 628
 629   if (Rt == 0) {
 630     MI.setOpcode(Mips::BGTZ);
 631     HasRs = true;
 632   } else if (Rs == 0) {
 633     MI.setOpcode(Mips::BGTZALC);
 634     HasRt = true;
 635   } else if (Rs == Rt) {
 636     MI.setOpcode(Mips::BLTZALC);
 637     HasRs = true;
 638   } else {
 639     MI.setOpcode(Mips::BLTUC);
 640     HasRs = true;
 641     HasRt = true;
 642   }
 643
 644   if (HasRs)
 645     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 646                                        Rs)));
 647
 648   if (HasRt)
 649     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 650                                        Rt)));
 651
 652   MI.addOperand(MCOperand::CreateImm(Imm));
 653
 654   return MCDisassembler::Success;
 655 }
 656
 657 template <typename InsnType>
 658 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 659                                            uint64_t Address,
 660                                            const void *Decoder) {
 661   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 662   // (otherwise we would have matched the BLEZL instruction from the earlier
 663   // ISA's instead).
 664   //
 665   // We have:
 666   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 667   //      Invalid   if rs == 0
 668   //      BLEZALC   if rs == 0  && rt != 0
 669   //      BGEZALC   if rs == rt && rt != 0
 670   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 671
 672   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 673   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 674   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 675   bool HasRs = false;
 676
 677   if (Rt == 0)
 678     return MCDisassembler::Fail;
 679   else if (Rs == 0)
 680     MI.setOpcode(Mips::BLEZALC);
 681   else if (Rs == Rt)
 682     MI.setOpcode(Mips::BGEZALC);
 683   else {
 684     HasRs = true;
 685     MI.setOpcode(Mips::BGEUC);
 686   }
 687
 688   if (HasRs)
 689     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 690                                        Rs)));
 691   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 692                                      Rt)));
 693
 694   MI.addOperand(MCOperand::CreateImm(Imm));
 695
 696   return MCDisassembler::Success;
 697 }
 698
 699   /// readInstruction - read four bytes from the MemoryObject
 700   /// and return 32 bit word sorted according to the given endianess
 701 static DecodeStatus readInstruction32(const MemoryObject &region,
 702                                       uint64_t address,
 703                                       uint64_t &size,
 704                                       uint32_t &insn,
 705                                       bool isBigEndian,
 706                                       bool IsMicroMips) {
 707   uint8_t Bytes[4];
 708
 709   // We want to read exactly 4 Bytes of data.
 710   if (region.readBytes(address, 4, Bytes) == -1) {
 711     size = 0;
 712     return MCDisassembler::Fail;
 713   }
 714
 715   if (isBigEndian) {
 716     // Encoded as a big-endian 32-bit word in the stream.
 717     insn = (Bytes[3] <<  0) |
 718            (Bytes[2] <<  8) |
 719            (Bytes[1] << 16) |
 720            (Bytes[0] << 24);
 721   }
 722   else {
 723     // Encoded as a small-endian 32-bit word in the stream.
 724     // Little-endian byte ordering:
 725     //   mips32r2:   4 | 3 | 2 | 1
 726     //   microMIPS:  2 | 1 | 4 | 3
 727     if (IsMicroMips) {
 728       insn = (Bytes[2] <<  0) |
 729              (Bytes[3] <<  8) |
 730              (Bytes[0] << 16) |
 731              (Bytes[1] << 24);
 732     } else {
 733       insn = (Bytes[0] <<  0) |
 734              (Bytes[1] <<  8) |
 735              (Bytes[2] << 16) |
 736              (Bytes[3] << 24);
 737     }
 738   }
 739
 740   return MCDisassembler::Success;
 741 }
 742
 743 DecodeStatus
 744 MipsDisassembler::getInstruction(MCInst &instr,
 745                                  uint64_t &Size,
 746                                  const MemoryObject &Region,
 747                                  uint64_t Address,
 748                                  raw_ostream &vStream,
 749                                  raw_ostream &cStream) const {
 750   uint32_t Insn;
 751
 752   DecodeStatus Result = readInstruction32(Region, Address, Size,
 753                                           Insn, isBigEndian, IsMicroMips);
 754   if (Result == MCDisassembler::Fail)
 755     return MCDisassembler::Fail;
 756
 757   if (IsMicroMips) {
 758     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 759     // Calling the auto-generated decoder function.
 760     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 761                                this, STI);
 762     if (Result != MCDisassembler::Fail) {
 763       Size = 4;
 764       return Result;
 765     }
 766     return MCDisassembler::Fail;
 767   }
 768
 769   if (hasCOP3()) {
 770     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 771     Result =
 772         decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
 773     if (Result != MCDisassembler::Fail) {
 774       Size = 4;
 775       return Result;
 776     }
 777   }
 778
 779   if (hasMips32r6() && isGP64()) {
 780     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 781     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 782                                Address, this, STI);
 783     if (Result != MCDisassembler::Fail) {
 784       Size = 4;
 785       return Result;
 786     }
 787   }
 788
 789   if (hasMips32r6()) {
 790     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 791     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 792                                Address, this, STI);
 793     if (Result != MCDisassembler::Fail) {
 794       Size = 4;
 795       return Result;
 796     }
 797   }
 798
 799   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 800   // Calling the auto-generated decoder function.
 801   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 802                              this, STI);
 803   if (Result != MCDisassembler::Fail) {
 804     Size = 4;
 805     return Result;
 806   }
 807
 808   return MCDisassembler::Fail;
 809 }
 810
 811 DecodeStatus
 812 Mips64Disassembler::getInstruction(MCInst &instr,
 813                                    uint64_t &Size,
 814                                    const MemoryObject &Region,
 815                                    uint64_t Address,
 816                                    raw_ostream &vStream,
 817                                    raw_ostream &cStream) const {
 818   uint32_t Insn;
 819
 820   DecodeStatus Result = readInstruction32(Region, Address, Size,
 821                                           Insn, isBigEndian, false);
 822   if (Result == MCDisassembler::Fail)
 823     return MCDisassembler::Fail;
 824
 825   // Calling the auto-generated decoder function.
 826   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 827                              this, STI);
 828   if (Result != MCDisassembler::Fail) {
 829     Size = 4;
 830     return Result;
 831   }
 832   // If we fail to decode in Mips64 decoder space we can try in Mips32
 833   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 834                              this, STI);
 835   if (Result != MCDisassembler::Fail) {
 836     Size = 4;
 837     return Result;
 838   }
 839
 840   return MCDisassembler::Fail;
 841 }
 842
 843 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 844                                                  unsigned RegNo,
 845                                                  uint64_t Address,
 846                                                  const void *Decoder) {
 847
 848   return MCDisassembler::Fail;
 849
 850 }
 851
 852 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 853                                              unsigned RegNo,
 854                                              uint64_t Address,
 855                                              const void *Decoder) {
 856
 857   if (RegNo > 31)
 858     return MCDisassembler::Fail;
 859
 860   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 861   Inst.addOperand(MCOperand::CreateReg(Reg));
 862   return MCDisassembler::Success;
 863 }
 864
 865 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 866                                              unsigned RegNo,
 867                                              uint64_t Address,
 868                                              const void *Decoder) {
 869   if (RegNo > 31)
 870     return MCDisassembler::Fail;
 871   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 872   Inst.addOperand(MCOperand::CreateReg(Reg));
 873   return MCDisassembler::Success;
 874 }
 875
 876 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 877                                            unsigned RegNo,
 878                                            uint64_t Address,
 879                                            const void *Decoder) {
 880   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 881     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 882
 883   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 884 }
 885
 886 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 887                                             unsigned RegNo,
 888                                             uint64_t Address,
 889                                             const void *Decoder) {
 890   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 891 }
 892
 893 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 894                                              unsigned RegNo,
 895                                              uint64_t Address,
 896                                              const void *Decoder) {
 897   if (RegNo > 31)
 898     return MCDisassembler::Fail;
 899
 900   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 901   Inst.addOperand(MCOperand::CreateReg(Reg));
 902   return MCDisassembler::Success;
 903 }
 904
 905 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 906                                              unsigned RegNo,
 907                                              uint64_t Address,
 908                                              const void *Decoder) {
 909   if (RegNo > 31)
 910     return MCDisassembler::Fail;
 911
 912   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 913   Inst.addOperand(MCOperand::CreateReg(Reg));
 914   return MCDisassembler::Success;
 915 }
 916
 917 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 918                                               unsigned RegNo,
 919                                               uint64_t Address,
 920                                               const void *Decoder) {
 921   if (RegNo > 31)
 922     return MCDisassembler::Fail;
 923
 924   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 925   Inst.addOperand(MCOperand::CreateReg(Reg));
 926   return MCDisassembler::Success;
 927 }
 928
 929 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 930                                            unsigned RegNo,
 931                                            uint64_t Address,
 932                                            const void *Decoder) {
 933   if (RegNo > 31)
 934     return MCDisassembler::Fail;
 935   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 936   Inst.addOperand(MCOperand::CreateReg(Reg));
 937   return MCDisassembler::Success;
 938 }
 939
 940 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 941                                            unsigned RegNo,
 942                                            uint64_t Address,
 943                                            const void *Decoder) {
 944   if (RegNo > 7)
 945     return MCDisassembler::Fail;
 946   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 947   Inst.addOperand(MCOperand::CreateReg(Reg));
 948   return MCDisassembler::Success;
 949 }
 950
 951 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 952                                              uint64_t Address,
 953                                              const void *Decoder) {
 954   if (RegNo > 31)
 955     return MCDisassembler::Fail;
 956
 957   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 958   Inst.addOperand(MCOperand::CreateReg(Reg));
 959   return MCDisassembler::Success;
 960 }
 961
 962 static DecodeStatus DecodeMem(MCInst &Inst,
 963                               unsigned Insn,
 964                               uint64_t Address,
 965                               const void *Decoder) {
 966   int Offset = SignExtend32<16>(Insn & 0xffff);
 967   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 968   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 969
 970   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 971   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 972
 973   if(Inst.getOpcode() == Mips::SC){
 974     Inst.addOperand(MCOperand::CreateReg(Reg));
 975   }
 976
 977   Inst.addOperand(MCOperand::CreateReg(Reg));
 978   Inst.addOperand(MCOperand::CreateReg(Base));
 979   Inst.addOperand(MCOperand::CreateImm(Offset));
 980
 981   return MCDisassembler::Success;
 982 }
 983
 984 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 985                                     uint64_t Address, const void *Decoder) {
 986   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 987   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 988   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 989
 990   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 991   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 992
 993   Inst.addOperand(MCOperand::CreateReg(Reg));
 994   Inst.addOperand(MCOperand::CreateReg(Base));
 995
 996   // The immediate field of an LD/ST instruction is scaled which means it must
 997   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 998   // data format.
 999   // .b - 1 byte
1000   // .h - 2 bytes
1001   // .w - 4 bytes
1002   // .d - 8 bytes
1003   switch(Inst.getOpcode())
1004   {
1005   default:
1006     assert (0 && "Unexpected instruction");
1007     return MCDisassembler::Fail;
1008     break;
1009   case Mips::LD_B:
1010   case Mips::ST_B:
1011     Inst.addOperand(MCOperand::CreateImm(Offset));
1012     break;
1013   case Mips::LD_H:
1014   case Mips::ST_H:
1015     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1016     break;
1017   case Mips::LD_W:
1018   case Mips::ST_W:
1019     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1020     break;
1021   case Mips::LD_D:
1022   case Mips::ST_D:
1023     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
1024     break;
1025   }
1026
1027   return MCDisassembler::Success;
1028 }
1029
1030 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1031                                      unsigned Insn,
1032                                      uint64_t Address,
1033                                      const void *Decoder) {
1034   int Offset = SignExtend32<12>(Insn & 0x0fff);
1035   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1036   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1037
1038   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1039   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1040
1041   if (Inst.getOpcode() == Mips::SC_MM)
1042     Inst.addOperand(MCOperand::CreateReg(Reg));
1043
1044   Inst.addOperand(MCOperand::CreateReg(Reg));
1045   Inst.addOperand(MCOperand::CreateReg(Base));
1046   Inst.addOperand(MCOperand::CreateImm(Offset));
1047
1048   return MCDisassembler::Success;
1049 }
1050
1051 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1052                                      unsigned Insn,
1053                                      uint64_t Address,
1054                                      const void *Decoder) {
1055   int Offset = SignExtend32<16>(Insn & 0xffff);
1056   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1057   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1058
1059   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1060   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1061
1062   Inst.addOperand(MCOperand::CreateReg(Reg));
1063   Inst.addOperand(MCOperand::CreateReg(Base));
1064   Inst.addOperand(MCOperand::CreateImm(Offset));
1065
1066   return MCDisassembler::Success;
1067 }
1068
1069 static DecodeStatus DecodeFMem(MCInst &Inst,
1070                                unsigned Insn,
1071                                uint64_t Address,
1072                                const void *Decoder) {
1073   int Offset = SignExtend32<16>(Insn & 0xffff);
1074   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1075   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1076
1077   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1078   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1079
1080   Inst.addOperand(MCOperand::CreateReg(Reg));
1081   Inst.addOperand(MCOperand::CreateReg(Base));
1082   Inst.addOperand(MCOperand::CreateImm(Offset));
1083
1084   return MCDisassembler::Success;
1085 }
1086
1087 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1088                                        unsigned Insn,
1089                                        uint64_t Address,
1090                                        const void *Decoder) {
1091   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1092   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1093   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1094
1095   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1096   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1097
1098   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1099     Inst.addOperand(MCOperand::CreateReg(Rt));
1100   }
1101
1102   Inst.addOperand(MCOperand::CreateReg(Rt));
1103   Inst.addOperand(MCOperand::CreateReg(Base));
1104   Inst.addOperand(MCOperand::CreateImm(Offset));
1105
1106   return MCDisassembler::Success;
1107 }
1108
1109 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1110                                               unsigned RegNo,
1111                                               uint64_t Address,
1112                                               const void *Decoder) {
1113   // Currently only hardware register 29 is supported.
1114   if (RegNo != 29)
1115     return  MCDisassembler::Fail;
1116   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1117   return MCDisassembler::Success;
1118 }
1119
1120 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1121                                               unsigned RegNo,
1122                                               uint64_t Address,
1123                                               const void *Decoder) {
1124   if (RegNo > 30 || RegNo %2)
1125     return MCDisassembler::Fail;
1126
1127   ;
1128   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1129   Inst.addOperand(MCOperand::CreateReg(Reg));
1130   return MCDisassembler::Success;
1131 }
1132
1133 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1134                                                 unsigned RegNo,
1135                                                 uint64_t Address,
1136                                                 const void *Decoder) {
1137   if (RegNo >= 4)
1138     return MCDisassembler::Fail;
1139
1140   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1141   Inst.addOperand(MCOperand::CreateReg(Reg));
1142   return MCDisassembler::Success;
1143 }
1144
1145 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1146                                                unsigned RegNo,
1147                                                uint64_t Address,
1148                                                const void *Decoder) {
1149   if (RegNo >= 4)
1150     return MCDisassembler::Fail;
1151
1152   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1153   Inst.addOperand(MCOperand::CreateReg(Reg));
1154   return MCDisassembler::Success;
1155 }
1156
1157 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1158                                                unsigned RegNo,
1159                                                uint64_t Address,
1160                                                const void *Decoder) {
1161   if (RegNo >= 4)
1162     return MCDisassembler::Fail;
1163
1164   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1165   Inst.addOperand(MCOperand::CreateReg(Reg));
1166   return MCDisassembler::Success;
1167 }
1168
1169 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1170                                                unsigned RegNo,
1171                                                uint64_t Address,
1172                                                const void *Decoder) {
1173   if (RegNo > 31)
1174     return MCDisassembler::Fail;
1175
1176   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1177   Inst.addOperand(MCOperand::CreateReg(Reg));
1178   return MCDisassembler::Success;
1179 }
1180
1181 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1182                                                unsigned RegNo,
1183                                                uint64_t Address,
1184                                                const void *Decoder) {
1185   if (RegNo > 31)
1186     return MCDisassembler::Fail;
1187
1188   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1189   Inst.addOperand(MCOperand::CreateReg(Reg));
1190   return MCDisassembler::Success;
1191 }
1192
1193 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1194                                                unsigned RegNo,
1195                                                uint64_t Address,
1196                                                const void *Decoder) {
1197   if (RegNo > 31)
1198     return MCDisassembler::Fail;
1199
1200   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1201   Inst.addOperand(MCOperand::CreateReg(Reg));
1202   return MCDisassembler::Success;
1203 }
1204
1205 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1206                                                unsigned RegNo,
1207                                                uint64_t Address,
1208                                                const void *Decoder) {
1209   if (RegNo > 31)
1210     return MCDisassembler::Fail;
1211
1212   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1213   Inst.addOperand(MCOperand::CreateReg(Reg));
1214   return MCDisassembler::Success;
1215 }
1216
1217 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1218                                                unsigned RegNo,
1219                                                uint64_t Address,
1220                                                const void *Decoder) {
1221   if (RegNo > 7)
1222     return MCDisassembler::Fail;
1223
1224   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1225   Inst.addOperand(MCOperand::CreateReg(Reg));
1226   return MCDisassembler::Success;
1227 }
1228
1229 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1230                                             unsigned RegNo,
1231                                             uint64_t Address,
1232                                             const void *Decoder) {
1233   if (RegNo > 31)
1234     return MCDisassembler::Fail;
1235
1236   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1237   Inst.addOperand(MCOperand::CreateReg(Reg));
1238   return MCDisassembler::Success;
1239 }
1240
1241 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1242                                        unsigned Offset,
1243                                        uint64_t Address,
1244                                        const void *Decoder) {
1245   int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1246   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1247   return MCDisassembler::Success;
1248 }
1249
1250 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1251                                      unsigned Insn,
1252                                      uint64_t Address,
1253                                      const void *Decoder) {
1254
1255   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1256   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1257   return MCDisassembler::Success;
1258 }
1259
1260 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1261                                          unsigned Offset,
1262                                          uint64_t Address,
1263                                          const void *Decoder) {
1264   int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1265
1266   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1267   return MCDisassembler::Success;
1268 }
1269
1270 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1271                                          unsigned Offset,
1272                                          uint64_t Address,
1273                                          const void *Decoder) {
1274   int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1275
1276   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1277   return MCDisassembler::Success;
1278 }
1279
1280 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1281                                          unsigned Offset,
1282                                          uint64_t Address,
1283                                          const void *Decoder) {
1284   int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1285   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1286   return MCDisassembler::Success;
1287 }
1288
1289 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1290                                        unsigned Insn,
1291                                        uint64_t Address,
1292                                        const void *Decoder) {
1293   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1294   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1295   return MCDisassembler::Success;
1296 }
1297
1298 static DecodeStatus DecodeSimm16(MCInst &Inst,
1299                                  unsigned Insn,
1300                                  uint64_t Address,
1301                                  const void *Decoder) {
1302   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1303   return MCDisassembler::Success;
1304 }
1305
1306 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1307                                  unsigned Insn,
1308                                  uint64_t Address,
1309                                  const void *Decoder) {
1310   // We add one to the immediate field as it was encoded as 'imm - 1'.
1311   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1312   return MCDisassembler::Success;
1313 }
1314
1315 static DecodeStatus DecodeInsSize(MCInst &Inst,
1316                                   unsigned Insn,
1317                                   uint64_t Address,
1318                                   const void *Decoder) {
1319   // First we need to grab the pos(lsb) from MCInst.
1320   int Pos = Inst.getOperand(2).getImm();
1321   int Size = (int) Insn - Pos + 1;
1322   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1323   return MCDisassembler::Success;
1324 }
1325
1326 static DecodeStatus DecodeExtSize(MCInst &Inst,
1327                                   unsigned Insn,
1328                                   uint64_t Address,
1329                                   const void *Decoder) {
1330   int Size = (int) Insn  + 1;
1331   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1332   return MCDisassembler::Success;
1333 }
1334
1335 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1336                                      uint64_t Address, const void *Decoder) {
1337   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1338   return MCDisassembler::Success;
1339 }
1340
1341 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1342                                      uint64_t Address, const void *Decoder) {
1343   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1344   return MCDisassembler::Success;
1345 }