lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 234                                          unsigned Offset,
 235                                          uint64_t Address,
 236                                          const void *Decoder);
 237
 238 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 241                                        unsigned Insn,
 242                                        uint64_t Address,
 243                                        const void *Decoder);
 244
 245 static DecodeStatus DecodeMem(MCInst &Inst,
 246                               unsigned Insn,
 247                               uint64_t Address,
 248                               const void *Decoder);
 249
 250 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 251                               unsigned Insn,
 252                               uint64_t Address,
 253                               const void *Decoder);
 254
 255 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 256                                     unsigned Insn,
 257                                     uint64_t Address,
 258                                     const void *Decoder);
 259
 260 static DecodeStatus DecodeSyncI(MCInst &Inst,
 261                                 unsigned Insn,
 262                                 uint64_t Address,
 263                                 const void *Decoder);
 264
 265 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 266                                     uint64_t Address, const void *Decoder);
 267
 268 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 269                                     unsigned Insn,
 270                                     uint64_t Address,
 271                                     const void *Decoder);
 272
 273 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 274                                           unsigned Insn,
 275                                           uint64_t Address,
 276                                           const void *Decoder);
 277
 278 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 279                                      unsigned Insn,
 280                                      uint64_t Address,
 281                                      const void *Decoder);
 282
 283 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 284                                      unsigned Insn,
 285                                      uint64_t Address,
 286                                      const void *Decoder);
 287
 288 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 289                                uint64_t Address,
 290                                const void *Decoder);
 291
 292 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 293                                uint64_t Address,
 294                                const void *Decoder);
 295
 296 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 297                                uint64_t Address,
 298                                const void *Decoder);
 299
 300 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 301                                        unsigned Insn,
 302                                        uint64_t Address,
 303                                        const void *Decoder);
 304
 305 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 306                                        unsigned Value,
 307                                        uint64_t Address,
 308                                        const void *Decoder);
 309
 310 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 311                                     unsigned Value,
 312                                     uint64_t Address,
 313                                     const void *Decoder);
 314
 315 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 316                                   unsigned Value,
 317                                   uint64_t Address,
 318                                   const void *Decoder);
 319
 320 static DecodeStatus DecodeSimm4(MCInst &Inst,
 321                                 unsigned Value,
 322                                 uint64_t Address,
 323                                 const void *Decoder);
 324
 325 static DecodeStatus DecodeSimm16(MCInst &Inst,
 326                                  unsigned Insn,
 327                                  uint64_t Address,
 328                                  const void *Decoder);
 329
 330 // Decode the immediate field of an LSA instruction which
 331 // is off by one.
 332 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 333                                  unsigned Insn,
 334                                  uint64_t Address,
 335                                  const void *Decoder);
 336
 337 static DecodeStatus DecodeInsSize(MCInst &Inst,
 338                                   unsigned Insn,
 339                                   uint64_t Address,
 340                                   const void *Decoder);
 341
 342 static DecodeStatus DecodeExtSize(MCInst &Inst,
 343                                   unsigned Insn,
 344                                   uint64_t Address,
 345                                   const void *Decoder);
 346
 347 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 348                                      uint64_t Address, const void *Decoder);
 349
 350 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 351                                      uint64_t Address, const void *Decoder);
 352
 353 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 354                                   uint64_t Address, const void *Decoder);
 355
 356 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 357                                     uint64_t Address, const void *Decoder);
 358
 359 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 360                                    uint64_t Address, const void *Decoder);
 361
 362 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 363 /// handle.
 364 template <typename InsnType>
 365 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 366                                    const void *Decoder);
 367
 368 template <typename InsnType>
 369 static DecodeStatus
 370 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 371                       const void *Decoder);
 372
 373 template <typename InsnType>
 374 static DecodeStatus
 375 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 376                        const void *Decoder);
 377
 378 template <typename InsnType>
 379 static DecodeStatus
 380 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 381                        const void *Decoder);
 382
 383 template <typename InsnType>
 384 static DecodeStatus
 385 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 386                        const void *Decoder);
 387
 388 template <typename InsnType>
 389 static DecodeStatus
 390 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 391                       const void *Decoder);
 392
 393 template <typename InsnType>
 394 static DecodeStatus
 395 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 396                        const void *Decoder);
 397
 398 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 399                                          uint64_t Address,
 400                                          const void *Decoder);
 401
 402 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 403                                            uint64_t Address,
 404                                            const void *Decoder);
 405
 406 namespace llvm {
 407 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 408               TheMips64elTarget;
 409 }
 410
 411 static MCDisassembler *createMipsDisassembler(
 412                        const Target &T,
 413                        const MCSubtargetInfo &STI,
 414                        MCContext &Ctx) {
 415   return new MipsDisassembler(STI, Ctx, true);
 416 }
 417
 418 static MCDisassembler *createMipselDisassembler(
 419                        const Target &T,
 420                        const MCSubtargetInfo &STI,
 421                        MCContext &Ctx) {
 422   return new MipsDisassembler(STI, Ctx, false);
 423 }
 424
 425 static MCDisassembler *createMips64Disassembler(
 426                        const Target &T,
 427                        const MCSubtargetInfo &STI,
 428                        MCContext &Ctx) {
 429   return new Mips64Disassembler(STI, Ctx, true);
 430 }
 431
 432 static MCDisassembler *createMips64elDisassembler(
 433                        const Target &T,
 434                        const MCSubtargetInfo &STI,
 435                        MCContext &Ctx) {
 436   return new Mips64Disassembler(STI, Ctx, false);
 437 }
 438
 439 extern "C" void LLVMInitializeMipsDisassembler() {
 440   // Register the disassembler.
 441   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 442                                          createMipsDisassembler);
 443   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 444                                          createMipselDisassembler);
 445   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 446                                          createMips64Disassembler);
 447   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 448                                          createMips64elDisassembler);
 449 }
 450
 451 #include "MipsGenDisassemblerTables.inc"
 452
 453 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 454   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 455   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 456   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 457 }
 458
 459 template <typename InsnType>
 460 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 461                                    const void *Decoder) {
 462   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 463   // The size of the n field depends on the element size
 464   // The register class also depends on this.
 465   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 466   unsigned NSize = 0;
 467   DecodeFN RegDecoder = nullptr;
 468   if ((tmp & 0x18) == 0x00) { // INSVE_B
 469     NSize = 4;
 470     RegDecoder = DecodeMSA128BRegisterClass;
 471   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 472     NSize = 3;
 473     RegDecoder = DecodeMSA128HRegisterClass;
 474   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 475     NSize = 2;
 476     RegDecoder = DecodeMSA128WRegisterClass;
 477   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 478     NSize = 1;
 479     RegDecoder = DecodeMSA128DRegisterClass;
 480   } else
 481     llvm_unreachable("Invalid encoding");
 482
 483   assert(NSize != 0 && RegDecoder != nullptr);
 484
 485   // $wd
 486   tmp = fieldFromInstruction(insn, 6, 5);
 487   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 488     return MCDisassembler::Fail;
 489   // $wd_in
 490   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 491     return MCDisassembler::Fail;
 492   // $n
 493   tmp = fieldFromInstruction(insn, 16, NSize);
 494   MI.addOperand(MCOperand::CreateImm(tmp));
 495   // $ws
 496   tmp = fieldFromInstruction(insn, 11, 5);
 497   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 498     return MCDisassembler::Fail;
 499   // $n2
 500   MI.addOperand(MCOperand::CreateImm(0));
 501
 502   return MCDisassembler::Success;
 503 }
 504
 505 template <typename InsnType>
 506 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 507                                           uint64_t Address,
 508                                           const void *Decoder) {
 509   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 510   // (otherwise we would have matched the ADDI instruction from the earlier
 511   // ISA's instead).
 512   //
 513   // We have:
 514   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 515   //      BOVC if rs >= rt
 516   //      BEQZALC if rs == 0 && rt != 0
 517   //      BEQC if rs < rt && rs != 0
 518
 519   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 520   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 521   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 522   bool HasRs = false;
 523
 524   if (Rs >= Rt) {
 525     MI.setOpcode(Mips::BOVC);
 526     HasRs = true;
 527   } else if (Rs != 0 && Rs < Rt) {
 528     MI.setOpcode(Mips::BEQC);
 529     HasRs = true;
 530   } else
 531     MI.setOpcode(Mips::BEQZALC);
 532
 533   if (HasRs)
 534     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 535                                        Rs)));
 536
 537   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 538                                      Rt)));
 539   MI.addOperand(MCOperand::CreateImm(Imm));
 540
 541   return MCDisassembler::Success;
 542 }
 543
 544 template <typename InsnType>
 545 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 546                                            uint64_t Address,
 547                                            const void *Decoder) {
 548   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 549   // (otherwise we would have matched the ADDI instruction from the earlier
 550   // ISA's instead).
 551   //
 552   // We have:
 553   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 554   //      BNVC if rs >= rt
 555   //      BNEZALC if rs == 0 && rt != 0
 556   //      BNEC if rs < rt && rs != 0
 557
 558   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 559   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 560   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 561   bool HasRs = false;
 562
 563   if (Rs >= Rt) {
 564     MI.setOpcode(Mips::BNVC);
 565     HasRs = true;
 566   } else if (Rs != 0 && Rs < Rt) {
 567     MI.setOpcode(Mips::BNEC);
 568     HasRs = true;
 569   } else
 570     MI.setOpcode(Mips::BNEZALC);
 571
 572   if (HasRs)
 573     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 574                                        Rs)));
 575
 576   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 577                                      Rt)));
 578   MI.addOperand(MCOperand::CreateImm(Imm));
 579
 580   return MCDisassembler::Success;
 581 }
 582
 583 template <typename InsnType>
 584 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 585                                            uint64_t Address,
 586                                            const void *Decoder) {
 587   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 588   // (otherwise we would have matched the BLEZL instruction from the earlier
 589   // ISA's instead).
 590   //
 591   // We have:
 592   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 593   //      Invalid if rs == 0
 594   //      BLEZC   if rs == 0  && rt != 0
 595   //      BGEZC   if rs == rt && rt != 0
 596   //      BGEC    if rs != rt && rs != 0  && rt != 0
 597
 598   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 599   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 600   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 601   bool HasRs = false;
 602
 603   if (Rt == 0)
 604     return MCDisassembler::Fail;
 605   else if (Rs == 0)
 606     MI.setOpcode(Mips::BLEZC);
 607   else if (Rs == Rt)
 608     MI.setOpcode(Mips::BGEZC);
 609   else {
 610     HasRs = true;
 611     MI.setOpcode(Mips::BGEC);
 612   }
 613
 614   if (HasRs)
 615     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 616                                        Rs)));
 617
 618   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 619                                      Rt)));
 620
 621   MI.addOperand(MCOperand::CreateImm(Imm));
 622
 623   return MCDisassembler::Success;
 624 }
 625
 626 template <typename InsnType>
 627 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 628                                            uint64_t Address,
 629                                            const void *Decoder) {
 630   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 631   // (otherwise we would have matched the BGTZL instruction from the earlier
 632   // ISA's instead).
 633   //
 634   // We have:
 635   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 636   //      Invalid if rs == 0
 637   //      BGTZC   if rs == 0  && rt != 0
 638   //      BLTZC   if rs == rt && rt != 0
 639   //      BLTC    if rs != rt && rs != 0  && rt != 0
 640
 641   bool HasRs = false;
 642
 643   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 644   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 645   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 646
 647   if (Rt == 0)
 648     return MCDisassembler::Fail;
 649   else if (Rs == 0)
 650     MI.setOpcode(Mips::BGTZC);
 651   else if (Rs == Rt)
 652     MI.setOpcode(Mips::BLTZC);
 653   else {
 654     MI.setOpcode(Mips::BLTC);
 655     HasRs = true;
 656   }
 657
 658   if (HasRs)
 659     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 660                                               Rs)));
 661
 662   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 663                                      Rt)));
 664
 665   MI.addOperand(MCOperand::CreateImm(Imm));
 666
 667   return MCDisassembler::Success;
 668 }
 669
 670 template <typename InsnType>
 671 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 672                                           uint64_t Address,
 673                                           const void *Decoder) {
 674   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 675   // (otherwise we would have matched the BGTZ instruction from the earlier
 676   // ISA's instead).
 677   //
 678   // We have:
 679   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 680   //      BGTZ    if rt == 0
 681   //      BGTZALC if rs == 0 && rt != 0
 682   //      BLTZALC if rs != 0 && rs == rt
 683   //      BLTUC   if rs != 0 && rs != rt
 684
 685   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 686   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 687   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 688   bool HasRs = false;
 689   bool HasRt = false;
 690
 691   if (Rt == 0) {
 692     MI.setOpcode(Mips::BGTZ);
 693     HasRs = true;
 694   } else if (Rs == 0) {
 695     MI.setOpcode(Mips::BGTZALC);
 696     HasRt = true;
 697   } else if (Rs == Rt) {
 698     MI.setOpcode(Mips::BLTZALC);
 699     HasRs = true;
 700   } else {
 701     MI.setOpcode(Mips::BLTUC);
 702     HasRs = true;
 703     HasRt = true;
 704   }
 705
 706   if (HasRs)
 707     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 708                                        Rs)));
 709
 710   if (HasRt)
 711     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 712                                        Rt)));
 713
 714   MI.addOperand(MCOperand::CreateImm(Imm));
 715
 716   return MCDisassembler::Success;
 717 }
 718
 719 template <typename InsnType>
 720 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 721                                            uint64_t Address,
 722                                            const void *Decoder) {
 723   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 724   // (otherwise we would have matched the BLEZL instruction from the earlier
 725   // ISA's instead).
 726   //
 727   // We have:
 728   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 729   //      Invalid   if rs == 0
 730   //      BLEZALC   if rs == 0  && rt != 0
 731   //      BGEZALC   if rs == rt && rt != 0
 732   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 733
 734   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 735   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 736   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 737   bool HasRs = false;
 738
 739   if (Rt == 0)
 740     return MCDisassembler::Fail;
 741   else if (Rs == 0)
 742     MI.setOpcode(Mips::BLEZALC);
 743   else if (Rs == Rt)
 744     MI.setOpcode(Mips::BGEZALC);
 745   else {
 746     HasRs = true;
 747     MI.setOpcode(Mips::BGEUC);
 748   }
 749
 750   if (HasRs)
 751     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 752                                        Rs)));
 753   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 754                                      Rt)));
 755
 756   MI.addOperand(MCOperand::CreateImm(Imm));
 757
 758   return MCDisassembler::Success;
 759 }
 760
 761 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 762 /// according to the given endianess.
 763 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 764                                       uint64_t &Size, uint32_t &Insn,
 765                                       bool IsBigEndian) {
 766   // We want to read exactly 2 Bytes of data.
 767   if (Bytes.size() < 2) {
 768     Size = 0;
 769     return MCDisassembler::Fail;
 770   }
 771
 772   if (IsBigEndian) {
 773     Insn = (Bytes[0] << 8) | Bytes[1];
 774   } else {
 775     Insn = (Bytes[1] << 8) | Bytes[0];
 776   }
 777
 778   return MCDisassembler::Success;
 779 }
 780
 781 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 782 /// according to the given endianess
 783 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 784                                       uint64_t &Size, uint32_t &Insn,
 785                                       bool IsBigEndian, bool IsMicroMips) {
 786   // We want to read exactly 4 Bytes of data.
 787   if (Bytes.size() < 4) {
 788     Size = 0;
 789     return MCDisassembler::Fail;
 790   }
 791
 792   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 793   // always precede the low 16 bits in the instruction stream (that is, they
 794   // are placed at lower addresses in the instruction stream).
 795   //
 796   // microMIPS byte ordering:
 797   //   Big-endian:    0 | 1 | 2 | 3
 798   //   Little-endian: 1 | 0 | 3 | 2
 799
 800   if (IsBigEndian) {
 801     // Encoded as a big-endian 32-bit word in the stream.
 802     Insn =
 803         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 804   } else {
 805     if (IsMicroMips) {
 806       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 807              (Bytes[1] << 24);
 808     } else {
 809       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 810              (Bytes[3] << 24);
 811     }
 812   }
 813
 814   return MCDisassembler::Success;
 815 }
 816
 817 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 818                                               ArrayRef<uint8_t> Bytes,
 819                                               uint64_t Address,
 820                                               raw_ostream &VStream,
 821                                               raw_ostream &CStream) const {
 822   uint32_t Insn;
 823   DecodeStatus Result;
 824
 825   if (IsMicroMips) {
 826     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 827
 828     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 829     // Calling the auto-generated decoder function.
 830     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 831                                this, STI);
 832     if (Result != MCDisassembler::Fail) {
 833       Size = 2;
 834       return Result;
 835     }
 836
 837     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 838     if (Result == MCDisassembler::Fail)
 839       return MCDisassembler::Fail;
 840
 841     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 842     // Calling the auto-generated decoder function.
 843     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 844                                this, STI);
 845     if (Result != MCDisassembler::Fail) {
 846       Size = 4;
 847       return Result;
 848     }
 849     return MCDisassembler::Fail;
 850   }
 851
 852   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 853   if (Result == MCDisassembler::Fail)
 854     return MCDisassembler::Fail;
 855
 856   if (hasCOP3()) {
 857     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 858     Result =
 859         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 860     if (Result != MCDisassembler::Fail) {
 861       Size = 4;
 862       return Result;
 863     }
 864   }
 865
 866   if (hasMips32r6() && isGP64()) {
 867     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 868     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 869                                Address, this, STI);
 870     if (Result != MCDisassembler::Fail) {
 871       Size = 4;
 872       return Result;
 873     }
 874   }
 875
 876   if (hasMips32r6()) {
 877     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 878     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 879                                Address, this, STI);
 880     if (Result != MCDisassembler::Fail) {
 881       Size = 4;
 882       return Result;
 883     }
 884   }
 885
 886   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 887   // Calling the auto-generated decoder function.
 888   Result =
 889       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 890   if (Result != MCDisassembler::Fail) {
 891     Size = 4;
 892     return Result;
 893   }
 894
 895   return MCDisassembler::Fail;
 896 }
 897
 898 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 899                                                 ArrayRef<uint8_t> Bytes,
 900                                                 uint64_t Address,
 901                                                 raw_ostream &VStream,
 902                                                 raw_ostream &CStream) const {
 903   uint32_t Insn;
 904
 905   DecodeStatus Result =
 906       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 907   if (Result == MCDisassembler::Fail)
 908     return MCDisassembler::Fail;
 909
 910   // Calling the auto-generated decoder function.
 911   Result =
 912       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 913   if (Result != MCDisassembler::Fail) {
 914     Size = 4;
 915     return Result;
 916   }
 917   // If we fail to decode in Mips64 decoder space we can try in Mips32
 918   Result =
 919       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 920   if (Result != MCDisassembler::Fail) {
 921     Size = 4;
 922     return Result;
 923   }
 924
 925   return MCDisassembler::Fail;
 926 }
 927
 928 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 929                                                  unsigned RegNo,
 930                                                  uint64_t Address,
 931                                                  const void *Decoder) {
 932
 933   return MCDisassembler::Fail;
 934
 935 }
 936
 937 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 938                                              unsigned RegNo,
 939                                              uint64_t Address,
 940                                              const void *Decoder) {
 941
 942   if (RegNo > 31)
 943     return MCDisassembler::Fail;
 944
 945   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 946   Inst.addOperand(MCOperand::CreateReg(Reg));
 947   return MCDisassembler::Success;
 948 }
 949
 950 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 951                                                unsigned RegNo,
 952                                                uint64_t Address,
 953                                                const void *Decoder) {
 954   if (RegNo > 7)
 955     return MCDisassembler::Fail;
 956   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 957   Inst.addOperand(MCOperand::CreateReg(Reg));
 958   return MCDisassembler::Success;
 959 }
 960
 961 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 962                                                    unsigned RegNo,
 963                                                    uint64_t Address,
 964                                                    const void *Decoder) {
 965   if (RegNo > 7)
 966     return MCDisassembler::Fail;
 967   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 968   Inst.addOperand(MCOperand::CreateReg(Reg));
 969   return MCDisassembler::Success;
 970 }
 971
 972 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 973                                              unsigned RegNo,
 974                                              uint64_t Address,
 975                                              const void *Decoder) {
 976   if (RegNo > 31)
 977     return MCDisassembler::Fail;
 978   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 979   Inst.addOperand(MCOperand::CreateReg(Reg));
 980   return MCDisassembler::Success;
 981 }
 982
 983 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 984                                            unsigned RegNo,
 985                                            uint64_t Address,
 986                                            const void *Decoder) {
 987   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
 988     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 989
 990   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 991 }
 992
 993 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 994                                             unsigned RegNo,
 995                                             uint64_t Address,
 996                                             const void *Decoder) {
 997   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 998 }
 999
1000 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1001                                              unsigned RegNo,
1002                                              uint64_t Address,
1003                                              const void *Decoder) {
1004   if (RegNo > 31)
1005     return MCDisassembler::Fail;
1006
1007   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1008   Inst.addOperand(MCOperand::CreateReg(Reg));
1009   return MCDisassembler::Success;
1010 }
1011
1012 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1013                                              unsigned RegNo,
1014                                              uint64_t Address,
1015                                              const void *Decoder) {
1016   if (RegNo > 31)
1017     return MCDisassembler::Fail;
1018
1019   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1020   Inst.addOperand(MCOperand::CreateReg(Reg));
1021   return MCDisassembler::Success;
1022 }
1023
1024 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1025                                            unsigned RegNo,
1026                                            uint64_t Address,
1027                                            const void *Decoder) {
1028   if (RegNo > 31)
1029     return MCDisassembler::Fail;
1030   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1031   Inst.addOperand(MCOperand::CreateReg(Reg));
1032   return MCDisassembler::Success;
1033 }
1034
1035 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1036                                            unsigned RegNo,
1037                                            uint64_t Address,
1038                                            const void *Decoder) {
1039   if (RegNo > 7)
1040     return MCDisassembler::Fail;
1041   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1042   Inst.addOperand(MCOperand::CreateReg(Reg));
1043   return MCDisassembler::Success;
1044 }
1045
1046 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1047                                              uint64_t Address,
1048                                              const void *Decoder) {
1049   if (RegNo > 31)
1050     return MCDisassembler::Fail;
1051
1052   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1053   Inst.addOperand(MCOperand::CreateReg(Reg));
1054   return MCDisassembler::Success;
1055 }
1056
1057 static DecodeStatus DecodeMem(MCInst &Inst,
1058                               unsigned Insn,
1059                               uint64_t Address,
1060                               const void *Decoder) {
1061   int Offset = SignExtend32<16>(Insn & 0xffff);
1062   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1063   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1064
1065   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1066   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1067
1068   if(Inst.getOpcode() == Mips::SC ||
1069      Inst.getOpcode() == Mips::SCD){
1070     Inst.addOperand(MCOperand::CreateReg(Reg));
1071   }
1072
1073   Inst.addOperand(MCOperand::CreateReg(Reg));
1074   Inst.addOperand(MCOperand::CreateReg(Base));
1075   Inst.addOperand(MCOperand::CreateImm(Offset));
1076
1077   return MCDisassembler::Success;
1078 }
1079
1080 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1081                               unsigned Insn,
1082                               uint64_t Address,
1083                               const void *Decoder) {
1084   int Offset = SignExtend32<16>(Insn & 0xffff);
1085   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1086   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1087
1088   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1089
1090   Inst.addOperand(MCOperand::CreateReg(Base));
1091   Inst.addOperand(MCOperand::CreateImm(Offset));
1092   Inst.addOperand(MCOperand::CreateImm(Hint));
1093
1094   return MCDisassembler::Success;
1095 }
1096
1097 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1098                                     unsigned Insn,
1099                                     uint64_t Address,
1100                                     const void *Decoder) {
1101   int Offset = SignExtend32<12>(Insn & 0xfff);
1102   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1103   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1104
1105   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1106
1107   Inst.addOperand(MCOperand::CreateReg(Base));
1108   Inst.addOperand(MCOperand::CreateImm(Offset));
1109   Inst.addOperand(MCOperand::CreateImm(Hint));
1110
1111   return MCDisassembler::Success;
1112 }
1113
1114 static DecodeStatus DecodeSyncI(MCInst &Inst,
1115                               unsigned Insn,
1116                               uint64_t Address,
1117                               const void *Decoder) {
1118   int Offset = SignExtend32<16>(Insn & 0xffff);
1119   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1120
1121   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1122
1123   Inst.addOperand(MCOperand::CreateReg(Base));
1124   Inst.addOperand(MCOperand::CreateImm(Offset));
1125
1126   return MCDisassembler::Success;
1127 }
1128
1129 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1130                                     uint64_t Address, const void *Decoder) {
1131   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1132   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1133   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1134
1135   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1136   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1137
1138   Inst.addOperand(MCOperand::CreateReg(Reg));
1139   Inst.addOperand(MCOperand::CreateReg(Base));
1140
1141   // The immediate field of an LD/ST instruction is scaled which means it must
1142   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1143   // data format.
1144   // .b - 1 byte
1145   // .h - 2 bytes
1146   // .w - 4 bytes
1147   // .d - 8 bytes
1148   switch(Inst.getOpcode())
1149   {
1150   default:
1151     assert (0 && "Unexpected instruction");
1152     return MCDisassembler::Fail;
1153     break;
1154   case Mips::LD_B:
1155   case Mips::ST_B:
1156     Inst.addOperand(MCOperand::CreateImm(Offset));
1157     break;
1158   case Mips::LD_H:
1159   case Mips::ST_H:
1160     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1161     break;
1162   case Mips::LD_W:
1163   case Mips::ST_W:
1164     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1165     break;
1166   case Mips::LD_D:
1167   case Mips::ST_D:
1168     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1169     break;
1170   }
1171
1172   return MCDisassembler::Success;
1173 }
1174
1175 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1176                                     unsigned Insn,
1177                                     uint64_t Address,
1178                                     const void *Decoder) {
1179   unsigned Offset = Insn & 0xf;
1180   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1181   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1182
1183   switch (Inst.getOpcode()) {
1184     case Mips::LBU16_MM:
1185     case Mips::LHU16_MM:
1186     case Mips::LW16_MM:
1187       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1188             == MCDisassembler::Fail)
1189         return MCDisassembler::Fail;
1190       break;
1191     case Mips::SB16_MM:
1192     case Mips::SH16_MM:
1193     case Mips::SW16_MM:
1194       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1195             == MCDisassembler::Fail)
1196         return MCDisassembler::Fail;
1197       break;
1198   }
1199
1200   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1201         == MCDisassembler::Fail)
1202     return MCDisassembler::Fail;
1203
1204   switch (Inst.getOpcode()) {
1205     case Mips::LBU16_MM:
1206       if (Offset == 0xf)
1207         Inst.addOperand(MCOperand::CreateImm(-1));
1208       else
1209         Inst.addOperand(MCOperand::CreateImm(Offset));
1210       break;
1211     case Mips::SB16_MM:
1212       Inst.addOperand(MCOperand::CreateImm(Offset));
1213       break;
1214     case Mips::LHU16_MM:
1215     case Mips::SH16_MM:
1216       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1217       break;
1218     case Mips::LW16_MM:
1219     case Mips::SW16_MM:
1220       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1221       break;
1222   }
1223
1224   return MCDisassembler::Success;
1225 }
1226
1227 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1228                                           unsigned Insn,
1229                                           uint64_t Address,
1230                                           const void *Decoder) {
1231   unsigned Offset = Insn & 0x1F;
1232   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1233
1234   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1235
1236   Inst.addOperand(MCOperand::CreateReg(Reg));
1237   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1238   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1239
1240   return MCDisassembler::Success;
1241 }
1242
1243 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1244                                      unsigned Insn,
1245                                      uint64_t Address,
1246                                      const void *Decoder) {
1247   int Offset = SignExtend32<12>(Insn & 0x0fff);
1248   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1249   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1250
1251   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1252   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1253
1254   switch (Inst.getOpcode()) {
1255   case Mips::SWM32_MM:
1256   case Mips::LWM32_MM:
1257     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1258         == MCDisassembler::Fail)
1259       return MCDisassembler::Fail;
1260     Inst.addOperand(MCOperand::CreateReg(Base));
1261     Inst.addOperand(MCOperand::CreateImm(Offset));
1262     break;
1263   case Mips::SC_MM:
1264     Inst.addOperand(MCOperand::CreateReg(Reg));
1265     // fallthrough
1266   default:
1267     Inst.addOperand(MCOperand::CreateReg(Reg));
1268     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1269       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1270
1271     Inst.addOperand(MCOperand::CreateReg(Base));
1272     Inst.addOperand(MCOperand::CreateImm(Offset));
1273   }
1274
1275   return MCDisassembler::Success;
1276 }
1277
1278 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1279                                      unsigned Insn,
1280                                      uint64_t Address,
1281                                      const void *Decoder) {
1282   int Offset = SignExtend32<16>(Insn & 0xffff);
1283   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1284   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1285
1286   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1287   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1288
1289   Inst.addOperand(MCOperand::CreateReg(Reg));
1290   Inst.addOperand(MCOperand::CreateReg(Base));
1291   Inst.addOperand(MCOperand::CreateImm(Offset));
1292
1293   return MCDisassembler::Success;
1294 }
1295
1296 static DecodeStatus DecodeFMem(MCInst &Inst,
1297                                unsigned Insn,
1298                                uint64_t Address,
1299                                const void *Decoder) {
1300   int Offset = SignExtend32<16>(Insn & 0xffff);
1301   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1302   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1303
1304   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1305   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1306
1307   Inst.addOperand(MCOperand::CreateReg(Reg));
1308   Inst.addOperand(MCOperand::CreateReg(Base));
1309   Inst.addOperand(MCOperand::CreateImm(Offset));
1310
1311   return MCDisassembler::Success;
1312 }
1313
1314 static DecodeStatus DecodeFMem2(MCInst &Inst,
1315                                unsigned Insn,
1316                                uint64_t Address,
1317                                const void *Decoder) {
1318   int Offset = SignExtend32<16>(Insn & 0xffff);
1319   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1320   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1321
1322   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1323   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1324
1325   Inst.addOperand(MCOperand::CreateReg(Reg));
1326   Inst.addOperand(MCOperand::CreateReg(Base));
1327   Inst.addOperand(MCOperand::CreateImm(Offset));
1328
1329   return MCDisassembler::Success;
1330 }
1331
1332 static DecodeStatus DecodeFMem3(MCInst &Inst,
1333                                unsigned Insn,
1334                                uint64_t Address,
1335                                const void *Decoder) {
1336   int Offset = SignExtend32<16>(Insn & 0xffff);
1337   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1338   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1339
1340   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1341   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1342
1343   Inst.addOperand(MCOperand::CreateReg(Reg));
1344   Inst.addOperand(MCOperand::CreateReg(Base));
1345   Inst.addOperand(MCOperand::CreateImm(Offset));
1346
1347   return MCDisassembler::Success;
1348 }
1349
1350 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1351                                        unsigned Insn,
1352                                        uint64_t Address,
1353                                        const void *Decoder) {
1354   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1355   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1356   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1357
1358   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1359   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1360
1361   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1362     Inst.addOperand(MCOperand::CreateReg(Rt));
1363   }
1364
1365   Inst.addOperand(MCOperand::CreateReg(Rt));
1366   Inst.addOperand(MCOperand::CreateReg(Base));
1367   Inst.addOperand(MCOperand::CreateImm(Offset));
1368
1369   return MCDisassembler::Success;
1370 }
1371
1372 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1373                                               unsigned RegNo,
1374                                               uint64_t Address,
1375                                               const void *Decoder) {
1376   // Currently only hardware register 29 is supported.
1377   if (RegNo != 29)
1378     return  MCDisassembler::Fail;
1379   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1380   return MCDisassembler::Success;
1381 }
1382
1383 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1384                                               unsigned RegNo,
1385                                               uint64_t Address,
1386                                               const void *Decoder) {
1387   if (RegNo > 30 || RegNo %2)
1388     return MCDisassembler::Fail;
1389
1390   ;
1391   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1392   Inst.addOperand(MCOperand::CreateReg(Reg));
1393   return MCDisassembler::Success;
1394 }
1395
1396 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1397                                                 unsigned RegNo,
1398                                                 uint64_t Address,
1399                                                 const void *Decoder) {
1400   if (RegNo >= 4)
1401     return MCDisassembler::Fail;
1402
1403   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1404   Inst.addOperand(MCOperand::CreateReg(Reg));
1405   return MCDisassembler::Success;
1406 }
1407
1408 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1409                                                unsigned RegNo,
1410                                                uint64_t Address,
1411                                                const void *Decoder) {
1412   if (RegNo >= 4)
1413     return MCDisassembler::Fail;
1414
1415   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1416   Inst.addOperand(MCOperand::CreateReg(Reg));
1417   return MCDisassembler::Success;
1418 }
1419
1420 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1421                                                unsigned RegNo,
1422                                                uint64_t Address,
1423                                                const void *Decoder) {
1424   if (RegNo >= 4)
1425     return MCDisassembler::Fail;
1426
1427   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1428   Inst.addOperand(MCOperand::CreateReg(Reg));
1429   return MCDisassembler::Success;
1430 }
1431
1432 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1433                                                unsigned RegNo,
1434                                                uint64_t Address,
1435                                                const void *Decoder) {
1436   if (RegNo > 31)
1437     return MCDisassembler::Fail;
1438
1439   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1440   Inst.addOperand(MCOperand::CreateReg(Reg));
1441   return MCDisassembler::Success;
1442 }
1443
1444 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1445                                                unsigned RegNo,
1446                                                uint64_t Address,
1447                                                const void *Decoder) {
1448   if (RegNo > 31)
1449     return MCDisassembler::Fail;
1450
1451   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1452   Inst.addOperand(MCOperand::CreateReg(Reg));
1453   return MCDisassembler::Success;
1454 }
1455
1456 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1457                                                unsigned RegNo,
1458                                                uint64_t Address,
1459                                                const void *Decoder) {
1460   if (RegNo > 31)
1461     return MCDisassembler::Fail;
1462
1463   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1464   Inst.addOperand(MCOperand::CreateReg(Reg));
1465   return MCDisassembler::Success;
1466 }
1467
1468 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1469                                                unsigned RegNo,
1470                                                uint64_t Address,
1471                                                const void *Decoder) {
1472   if (RegNo > 31)
1473     return MCDisassembler::Fail;
1474
1475   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1476   Inst.addOperand(MCOperand::CreateReg(Reg));
1477   return MCDisassembler::Success;
1478 }
1479
1480 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1481                                                unsigned RegNo,
1482                                                uint64_t Address,
1483                                                const void *Decoder) {
1484   if (RegNo > 7)
1485     return MCDisassembler::Fail;
1486
1487   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1488   Inst.addOperand(MCOperand::CreateReg(Reg));
1489   return MCDisassembler::Success;
1490 }
1491
1492 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1493                                             unsigned RegNo,
1494                                             uint64_t Address,
1495                                             const void *Decoder) {
1496   if (RegNo > 31)
1497     return MCDisassembler::Fail;
1498
1499   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1500   Inst.addOperand(MCOperand::CreateReg(Reg));
1501   return MCDisassembler::Success;
1502 }
1503
1504 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1505                                        unsigned Offset,
1506                                        uint64_t Address,
1507                                        const void *Decoder) {
1508   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1509   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1510   return MCDisassembler::Success;
1511 }
1512
1513 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1514                                      unsigned Insn,
1515                                      uint64_t Address,
1516                                      const void *Decoder) {
1517
1518   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1519   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1520   return MCDisassembler::Success;
1521 }
1522
1523 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1524                                          unsigned Offset,
1525                                          uint64_t Address,
1526                                          const void *Decoder) {
1527   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1528
1529   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1530   return MCDisassembler::Success;
1531 }
1532
1533 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1534                                          unsigned Offset,
1535                                          uint64_t Address,
1536                                          const void *Decoder) {
1537   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1538
1539   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1540   return MCDisassembler::Success;
1541 }
1542
1543 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1544                                          unsigned Offset,
1545                                          uint64_t Address,
1546                                          const void *Decoder) {
1547   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1548   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1549   return MCDisassembler::Success;
1550 }
1551
1552 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1553                                        unsigned Insn,
1554                                        uint64_t Address,
1555                                        const void *Decoder) {
1556   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1557   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1558   return MCDisassembler::Success;
1559 }
1560
1561 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1562                                        unsigned Value,
1563                                        uint64_t Address,
1564                                        const void *Decoder) {
1565   if (Value == 0)
1566     Inst.addOperand(MCOperand::CreateImm(1));
1567   else if (Value == 0x7)
1568     Inst.addOperand(MCOperand::CreateImm(-1));
1569   else
1570     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1571   return MCDisassembler::Success;
1572 }
1573
1574 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1575                                     unsigned Value,
1576                                     uint64_t Address,
1577                                     const void *Decoder) {
1578   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1579   return MCDisassembler::Success;
1580 }
1581
1582 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1583                                   unsigned Value,
1584                                   uint64_t Address,
1585                                   const void *Decoder) {
1586   if (Value == 0x7F)
1587     Inst.addOperand(MCOperand::CreateImm(-1));
1588   else
1589     Inst.addOperand(MCOperand::CreateImm(Value));
1590   return MCDisassembler::Success;
1591 }
1592
1593 static DecodeStatus DecodeSimm4(MCInst &Inst,
1594                                 unsigned Value,
1595                                 uint64_t Address,
1596                                 const void *Decoder) {
1597   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1598   return MCDisassembler::Success;
1599 }
1600
1601 static DecodeStatus DecodeSimm16(MCInst &Inst,
1602                                  unsigned Insn,
1603                                  uint64_t Address,
1604                                  const void *Decoder) {
1605   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1606   return MCDisassembler::Success;
1607 }
1608
1609 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1610                                  unsigned Insn,
1611                                  uint64_t Address,
1612                                  const void *Decoder) {
1613   // We add one to the immediate field as it was encoded as 'imm - 1'.
1614   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1615   return MCDisassembler::Success;
1616 }
1617
1618 static DecodeStatus DecodeInsSize(MCInst &Inst,
1619                                   unsigned Insn,
1620                                   uint64_t Address,
1621                                   const void *Decoder) {
1622   // First we need to grab the pos(lsb) from MCInst.
1623   int Pos = Inst.getOperand(2).getImm();
1624   int Size = (int) Insn - Pos + 1;
1625   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1626   return MCDisassembler::Success;
1627 }
1628
1629 static DecodeStatus DecodeExtSize(MCInst &Inst,
1630                                   unsigned Insn,
1631                                   uint64_t Address,
1632                                   const void *Decoder) {
1633   int Size = (int) Insn  + 1;
1634   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1635   return MCDisassembler::Success;
1636 }
1637
1638 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1639                                      uint64_t Address, const void *Decoder) {
1640   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1641   return MCDisassembler::Success;
1642 }
1643
1644 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1645                                      uint64_t Address, const void *Decoder) {
1646   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1647   return MCDisassembler::Success;
1648 }
1649
1650 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1651                                   uint64_t Address, const void *Decoder) {
1652   int32_t DecodedValue;
1653   switch (Insn) {
1654   case 0: DecodedValue = 256; break;
1655   case 1: DecodedValue = 257; break;
1656   case 510: DecodedValue = -258; break;
1657   case 511: DecodedValue = -257; break;
1658   default: DecodedValue = SignExtend32<9>(Insn); break;
1659   }
1660   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1661   return MCDisassembler::Success;
1662 }
1663
1664 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1665                                     uint64_t Address, const void *Decoder) {
1666   // Insn must be >= 0, since it is unsigned that condition is always true.
1667   assert(Insn < 16);
1668   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1669                              255, 32768, 65535};
1670   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1671   return MCDisassembler::Success;
1672 }
1673
1674 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1675                                     uint64_t Address, const void *Decoder) {
1676   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1677   return MCDisassembler::Success;
1678 }
1679
1680 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1681                                          unsigned Insn,
1682                                          uint64_t Address,
1683                                          const void *Decoder) {
1684   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1685                      Mips::S6, Mips::FP};
1686   unsigned RegNum;
1687
1688   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1689   // Empty register lists are not allowed.
1690   if (RegLst == 0)
1691     return MCDisassembler::Fail;
1692
1693   RegNum = RegLst & 0xf;
1694   for (unsigned i = 0; i < RegNum; i++)
1695     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1696
1697   if (RegLst & 0x10)
1698     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1699
1700   return MCDisassembler::Success;
1701 }
1702
1703 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1704                                            uint64_t Address,
1705                                            const void *Decoder) {
1706   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1707   unsigned RegNum;
1708
1709   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1710   // Empty register lists are not allowed.
1711   if (RegLst == 0)
1712     return MCDisassembler::Fail;
1713
1714   RegNum = RegLst & 0x3;
1715   for (unsigned i = 0; i < RegNum - 1; i++)
1716     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1717
1718   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1719
1720   return MCDisassembler::Success;
1721 }