lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MathExtras.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 typedef MCDisassembler::DecodeStatus DecodeStatus;
  28
  29 namespace {
  30
  31 /// MipsDisassemblerBase - a disasembler class for Mips.
  32 class MipsDisassemblerBase : public MCDisassembler {
  33 public:
  34   /// Constructor     - Initializes the disassembler.
  35   ///
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  37                        bool bigEndian) :
  38     MCDisassembler(STI), RegInfo(Info),
  39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  40
  41   virtual ~MipsDisassemblerBase() {}
  42
  43   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   OwningPtr<const MCRegisterInfo> RegInfo;
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Info, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Info, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 209 // shifted left by 1 bit.
 210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 211                                          unsigned Offset,
 212                                          uint64_t Address,
 213                                          const void *Decoder);
 214
 215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 216 // shifted left by 1 bit.
 217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 218                                        unsigned Insn,
 219                                        uint64_t Address,
 220                                        const void *Decoder);
 221
 222 static DecodeStatus DecodeMem(MCInst &Inst,
 223                               unsigned Insn,
 224                               uint64_t Address,
 225                               const void *Decoder);
 226
 227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 228                                     uint64_t Address, const void *Decoder);
 229
 230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 231                                      unsigned Insn,
 232                                      uint64_t Address,
 233                                      const void *Decoder);
 234
 235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 236                                      unsigned Insn,
 237                                      uint64_t Address,
 238                                      const void *Decoder);
 239
 240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 241                                uint64_t Address,
 242                                const void *Decoder);
 243
 244 static DecodeStatus DecodeSimm16(MCInst &Inst,
 245                                  unsigned Insn,
 246                                  uint64_t Address,
 247                                  const void *Decoder);
 248
 249 // Decode the immediate field of an LSA instruction which
 250 // is off by one.
 251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 252                                  unsigned Insn,
 253                                  uint64_t Address,
 254                                  const void *Decoder);
 255
 256 static DecodeStatus DecodeInsSize(MCInst &Inst,
 257                                   unsigned Insn,
 258                                   uint64_t Address,
 259                                   const void *Decoder);
 260
 261 static DecodeStatus DecodeExtSize(MCInst &Inst,
 262                                   unsigned Insn,
 263                                   uint64_t Address,
 264                                   const void *Decoder);
 265
 266 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 267 /// handle.
 268 template <typename InsnType>
 269 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 270                                    const void *Decoder);
 271 namespace llvm {
 272 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 273               TheMips64elTarget;
 274 }
 275
 276 static MCDisassembler *createMipsDisassembler(
 277                        const Target &T,
 278                        const MCSubtargetInfo &STI) {
 279   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 280 }
 281
 282 static MCDisassembler *createMipselDisassembler(
 283                        const Target &T,
 284                        const MCSubtargetInfo &STI) {
 285   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 286 }
 287
 288 static MCDisassembler *createMips64Disassembler(
 289                        const Target &T,
 290                        const MCSubtargetInfo &STI) {
 291   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 292 }
 293
 294 static MCDisassembler *createMips64elDisassembler(
 295                        const Target &T,
 296                        const MCSubtargetInfo &STI) {
 297   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 298 }
 299
 300 extern "C" void LLVMInitializeMipsDisassembler() {
 301   // Register the disassembler.
 302   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 303                                          createMipsDisassembler);
 304   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 305                                          createMipselDisassembler);
 306   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 307                                          createMips64Disassembler);
 308   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 309                                          createMips64elDisassembler);
 310 }
 311
 312 #include "MipsGenDisassemblerTables.inc"
 313
 314 template <typename InsnType>
 315 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 316                                    const void *Decoder) {
 317   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 318   // The size of the n field depends on the element size
 319   // The register class also depends on this.
 320   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 321   unsigned NSize = 0;
 322   DecodeFN RegDecoder = nullptr;
 323   if ((tmp & 0x18) == 0x00) { // INSVE_B
 324     NSize = 4;
 325     RegDecoder = DecodeMSA128BRegisterClass;
 326   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 327     NSize = 3;
 328     RegDecoder = DecodeMSA128HRegisterClass;
 329   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 330     NSize = 2;
 331     RegDecoder = DecodeMSA128WRegisterClass;
 332   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 333     NSize = 1;
 334     RegDecoder = DecodeMSA128DRegisterClass;
 335   } else
 336     llvm_unreachable("Invalid encoding");
 337
 338   assert(NSize != 0 && RegDecoder != nullptr);
 339
 340   // $wd
 341   tmp = fieldFromInstruction(insn, 6, 5);
 342   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 343     return MCDisassembler::Fail;
 344   // $wd_in
 345   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 346     return MCDisassembler::Fail;
 347   // $n
 348   tmp = fieldFromInstruction(insn, 16, NSize);
 349   MI.addOperand(MCOperand::CreateImm(tmp));
 350   // $ws
 351   tmp = fieldFromInstruction(insn, 11, 5);
 352   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 353     return MCDisassembler::Fail;
 354   // $n2
 355   MI.addOperand(MCOperand::CreateImm(0));
 356
 357   return MCDisassembler::Success;
 358 }
 359
 360   /// readInstruction - read four bytes from the MemoryObject
 361   /// and return 32 bit word sorted according to the given endianess
 362 static DecodeStatus readInstruction32(const MemoryObject &region,
 363                                       uint64_t address,
 364                                       uint64_t &size,
 365                                       uint32_t &insn,
 366                                       bool isBigEndian,
 367                                       bool IsMicroMips) {
 368   uint8_t Bytes[4];
 369
 370   // We want to read exactly 4 Bytes of data.
 371   if (region.readBytes(address, 4, Bytes) == -1) {
 372     size = 0;
 373     return MCDisassembler::Fail;
 374   }
 375
 376   if (isBigEndian) {
 377     // Encoded as a big-endian 32-bit word in the stream.
 378     insn = (Bytes[3] <<  0) |
 379            (Bytes[2] <<  8) |
 380            (Bytes[1] << 16) |
 381            (Bytes[0] << 24);
 382   }
 383   else {
 384     // Encoded as a small-endian 32-bit word in the stream.
 385     // Little-endian byte ordering:
 386     //   mips32r2:   4 | 3 | 2 | 1
 387     //   microMIPS:  2 | 1 | 4 | 3
 388     if (IsMicroMips) {
 389       insn = (Bytes[2] <<  0) |
 390              (Bytes[3] <<  8) |
 391              (Bytes[0] << 16) |
 392              (Bytes[1] << 24);
 393     } else {
 394       insn = (Bytes[0] <<  0) |
 395              (Bytes[1] <<  8) |
 396              (Bytes[2] << 16) |
 397              (Bytes[3] << 24);
 398     }
 399   }
 400
 401   return MCDisassembler::Success;
 402 }
 403
 404 DecodeStatus
 405 MipsDisassembler::getInstruction(MCInst &instr,
 406                                  uint64_t &Size,
 407                                  const MemoryObject &Region,
 408                                  uint64_t Address,
 409                                  raw_ostream &vStream,
 410                                  raw_ostream &cStream) const {
 411   uint32_t Insn;
 412
 413   DecodeStatus Result = readInstruction32(Region, Address, Size,
 414                                           Insn, isBigEndian, IsMicroMips);
 415   if (Result == MCDisassembler::Fail)
 416     return MCDisassembler::Fail;
 417
 418   if (IsMicroMips) {
 419     // Calling the auto-generated decoder function.
 420     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 421                                this, STI);
 422     if (Result != MCDisassembler::Fail) {
 423       Size = 4;
 424       return Result;
 425     }
 426     return MCDisassembler::Fail;
 427   }
 428
 429   // Calling the auto-generated decoder function.
 430   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 431                              this, STI);
 432   if (Result != MCDisassembler::Fail) {
 433     Size = 4;
 434     return Result;
 435   }
 436
 437   return MCDisassembler::Fail;
 438 }
 439
 440 DecodeStatus
 441 Mips64Disassembler::getInstruction(MCInst &instr,
 442                                    uint64_t &Size,
 443                                    const MemoryObject &Region,
 444                                    uint64_t Address,
 445                                    raw_ostream &vStream,
 446                                    raw_ostream &cStream) const {
 447   uint32_t Insn;
 448
 449   DecodeStatus Result = readInstruction32(Region, Address, Size,
 450                                           Insn, isBigEndian, false);
 451   if (Result == MCDisassembler::Fail)
 452     return MCDisassembler::Fail;
 453
 454   // Calling the auto-generated decoder function.
 455   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 456                              this, STI);
 457   if (Result != MCDisassembler::Fail) {
 458     Size = 4;
 459     return Result;
 460   }
 461   // If we fail to decode in Mips64 decoder space we can try in Mips32
 462   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 463                              this, STI);
 464   if (Result != MCDisassembler::Fail) {
 465     Size = 4;
 466     return Result;
 467   }
 468
 469   return MCDisassembler::Fail;
 470 }
 471
 472 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 473   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 474   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 475 }
 476
 477 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 478                                                  unsigned RegNo,
 479                                                  uint64_t Address,
 480                                                  const void *Decoder) {
 481
 482   return MCDisassembler::Fail;
 483
 484 }
 485
 486 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 487                                              unsigned RegNo,
 488                                              uint64_t Address,
 489                                              const void *Decoder) {
 490
 491   if (RegNo > 31)
 492     return MCDisassembler::Fail;
 493
 494   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 495   Inst.addOperand(MCOperand::CreateReg(Reg));
 496   return MCDisassembler::Success;
 497 }
 498
 499 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 500                                              unsigned RegNo,
 501                                              uint64_t Address,
 502                                              const void *Decoder) {
 503   if (RegNo > 31)
 504     return MCDisassembler::Fail;
 505   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 506   Inst.addOperand(MCOperand::CreateReg(Reg));
 507   return MCDisassembler::Success;
 508 }
 509
 510 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 511                                            unsigned RegNo,
 512                                            uint64_t Address,
 513                                            const void *Decoder) {
 514   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 515     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 516
 517   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 518 }
 519
 520 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 521                                             unsigned RegNo,
 522                                             uint64_t Address,
 523                                             const void *Decoder) {
 524   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 525 }
 526
 527 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 528                                              unsigned RegNo,
 529                                              uint64_t Address,
 530                                              const void *Decoder) {
 531   if (RegNo > 31)
 532     return MCDisassembler::Fail;
 533
 534   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 535   Inst.addOperand(MCOperand::CreateReg(Reg));
 536   return MCDisassembler::Success;
 537 }
 538
 539 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 540                                              unsigned RegNo,
 541                                              uint64_t Address,
 542                                              const void *Decoder) {
 543   if (RegNo > 31)
 544     return MCDisassembler::Fail;
 545
 546   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 547   Inst.addOperand(MCOperand::CreateReg(Reg));
 548   return MCDisassembler::Success;
 549 }
 550
 551 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 552                                               unsigned RegNo,
 553                                               uint64_t Address,
 554                                               const void *Decoder) {
 555   if (RegNo > 31)
 556     return MCDisassembler::Fail;
 557
 558   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 559   Inst.addOperand(MCOperand::CreateReg(Reg));
 560   return MCDisassembler::Success;
 561 }
 562
 563 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 564                                            unsigned RegNo,
 565                                            uint64_t Address,
 566                                            const void *Decoder) {
 567   if (RegNo > 31)
 568     return MCDisassembler::Fail;
 569   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 570   Inst.addOperand(MCOperand::CreateReg(Reg));
 571   return MCDisassembler::Success;
 572 }
 573
 574 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 575                                            unsigned RegNo,
 576                                            uint64_t Address,
 577                                            const void *Decoder) {
 578   if (RegNo > 7)
 579     return MCDisassembler::Fail;
 580   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 581   Inst.addOperand(MCOperand::CreateReg(Reg));
 582   return MCDisassembler::Success;
 583 }
 584
 585 static DecodeStatus DecodeMem(MCInst &Inst,
 586                               unsigned Insn,
 587                               uint64_t Address,
 588                               const void *Decoder) {
 589   int Offset = SignExtend32<16>(Insn & 0xffff);
 590   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 591   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 592
 593   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 594   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 595
 596   if(Inst.getOpcode() == Mips::SC){
 597     Inst.addOperand(MCOperand::CreateReg(Reg));
 598   }
 599
 600   Inst.addOperand(MCOperand::CreateReg(Reg));
 601   Inst.addOperand(MCOperand::CreateReg(Base));
 602   Inst.addOperand(MCOperand::CreateImm(Offset));
 603
 604   return MCDisassembler::Success;
 605 }
 606
 607 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 608                                     uint64_t Address, const void *Decoder) {
 609   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 610   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 611   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 612
 613   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 614   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 615
 616   Inst.addOperand(MCOperand::CreateReg(Reg));
 617   Inst.addOperand(MCOperand::CreateReg(Base));
 618
 619   // The immediate field of an LD/ST instruction is scaled which means it must
 620   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 621   // data format.
 622   // .b - 1 byte
 623   // .h - 2 bytes
 624   // .w - 4 bytes
 625   // .d - 8 bytes
 626   switch(Inst.getOpcode())
 627   {
 628   default:
 629     assert (0 && "Unexpected instruction");
 630     return MCDisassembler::Fail;
 631     break;
 632   case Mips::LD_B:
 633   case Mips::ST_B:
 634     Inst.addOperand(MCOperand::CreateImm(Offset));
 635     break;
 636   case Mips::LD_H:
 637   case Mips::ST_H:
 638     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 639     break;
 640   case Mips::LD_W:
 641   case Mips::ST_W:
 642     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 643     break;
 644   case Mips::LD_D:
 645   case Mips::ST_D:
 646     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 647     break;
 648   }
 649
 650   return MCDisassembler::Success;
 651 }
 652
 653 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 654                                      unsigned Insn,
 655                                      uint64_t Address,
 656                                      const void *Decoder) {
 657   int Offset = SignExtend32<12>(Insn & 0x0fff);
 658   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 659   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 660
 661   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 662   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 663
 664   if (Inst.getOpcode() == Mips::SC_MM)
 665     Inst.addOperand(MCOperand::CreateReg(Reg));
 666
 667   Inst.addOperand(MCOperand::CreateReg(Reg));
 668   Inst.addOperand(MCOperand::CreateReg(Base));
 669   Inst.addOperand(MCOperand::CreateImm(Offset));
 670
 671   return MCDisassembler::Success;
 672 }
 673
 674 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 675                                      unsigned Insn,
 676                                      uint64_t Address,
 677                                      const void *Decoder) {
 678   int Offset = SignExtend32<16>(Insn & 0xffff);
 679   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 680   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 681
 682   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 683   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 684
 685   Inst.addOperand(MCOperand::CreateReg(Reg));
 686   Inst.addOperand(MCOperand::CreateReg(Base));
 687   Inst.addOperand(MCOperand::CreateImm(Offset));
 688
 689   return MCDisassembler::Success;
 690 }
 691
 692 static DecodeStatus DecodeFMem(MCInst &Inst,
 693                                unsigned Insn,
 694                                uint64_t Address,
 695                                const void *Decoder) {
 696   int Offset = SignExtend32<16>(Insn & 0xffff);
 697   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 698   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 699
 700   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 701   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 702
 703   Inst.addOperand(MCOperand::CreateReg(Reg));
 704   Inst.addOperand(MCOperand::CreateReg(Base));
 705   Inst.addOperand(MCOperand::CreateImm(Offset));
 706
 707   return MCDisassembler::Success;
 708 }
 709
 710
 711 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 712                                               unsigned RegNo,
 713                                               uint64_t Address,
 714                                               const void *Decoder) {
 715   // Currently only hardware register 29 is supported.
 716   if (RegNo != 29)
 717     return  MCDisassembler::Fail;
 718   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 719   return MCDisassembler::Success;
 720 }
 721
 722 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 723                                               unsigned RegNo,
 724                                               uint64_t Address,
 725                                               const void *Decoder) {
 726   if (RegNo > 30 || RegNo %2)
 727     return MCDisassembler::Fail;
 728
 729   ;
 730   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 731   Inst.addOperand(MCOperand::CreateReg(Reg));
 732   return MCDisassembler::Success;
 733 }
 734
 735 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 736                                                 unsigned RegNo,
 737                                                 uint64_t Address,
 738                                                 const void *Decoder) {
 739   if (RegNo >= 4)
 740     return MCDisassembler::Fail;
 741
 742   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 743   Inst.addOperand(MCOperand::CreateReg(Reg));
 744   return MCDisassembler::Success;
 745 }
 746
 747 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 748                                                unsigned RegNo,
 749                                                uint64_t Address,
 750                                                const void *Decoder) {
 751   if (RegNo >= 4)
 752     return MCDisassembler::Fail;
 753
 754   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 755   Inst.addOperand(MCOperand::CreateReg(Reg));
 756   return MCDisassembler::Success;
 757 }
 758
 759 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 760                                                unsigned RegNo,
 761                                                uint64_t Address,
 762                                                const void *Decoder) {
 763   if (RegNo >= 4)
 764     return MCDisassembler::Fail;
 765
 766   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 767   Inst.addOperand(MCOperand::CreateReg(Reg));
 768   return MCDisassembler::Success;
 769 }
 770
 771 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 772                                                unsigned RegNo,
 773                                                uint64_t Address,
 774                                                const void *Decoder) {
 775   if (RegNo > 31)
 776     return MCDisassembler::Fail;
 777
 778   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 779   Inst.addOperand(MCOperand::CreateReg(Reg));
 780   return MCDisassembler::Success;
 781 }
 782
 783 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 784                                                unsigned RegNo,
 785                                                uint64_t Address,
 786                                                const void *Decoder) {
 787   if (RegNo > 31)
 788     return MCDisassembler::Fail;
 789
 790   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 791   Inst.addOperand(MCOperand::CreateReg(Reg));
 792   return MCDisassembler::Success;
 793 }
 794
 795 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 796                                                unsigned RegNo,
 797                                                uint64_t Address,
 798                                                const void *Decoder) {
 799   if (RegNo > 31)
 800     return MCDisassembler::Fail;
 801
 802   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 803   Inst.addOperand(MCOperand::CreateReg(Reg));
 804   return MCDisassembler::Success;
 805 }
 806
 807 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 808                                                unsigned RegNo,
 809                                                uint64_t Address,
 810                                                const void *Decoder) {
 811   if (RegNo > 31)
 812     return MCDisassembler::Fail;
 813
 814   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 815   Inst.addOperand(MCOperand::CreateReg(Reg));
 816   return MCDisassembler::Success;
 817 }
 818
 819 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 820                                                unsigned RegNo,
 821                                                uint64_t Address,
 822                                                const void *Decoder) {
 823   if (RegNo > 7)
 824     return MCDisassembler::Fail;
 825
 826   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 827   Inst.addOperand(MCOperand::CreateReg(Reg));
 828   return MCDisassembler::Success;
 829 }
 830
 831 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 832                                        unsigned Offset,
 833                                        uint64_t Address,
 834                                        const void *Decoder) {
 835   unsigned BranchOffset = Offset & 0xffff;
 836   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 837   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 838   return MCDisassembler::Success;
 839 }
 840
 841 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 842                                      unsigned Insn,
 843                                      uint64_t Address,
 844                                      const void *Decoder) {
 845
 846   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 847   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 848   return MCDisassembler::Success;
 849 }
 850
 851 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 852                                          unsigned Offset,
 853                                          uint64_t Address,
 854                                          const void *Decoder) {
 855   unsigned BranchOffset = Offset & 0xffff;
 856   BranchOffset = SignExtend32<18>(BranchOffset << 1);
 857   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 858   return MCDisassembler::Success;
 859 }
 860
 861 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 862                                        unsigned Insn,
 863                                        uint64_t Address,
 864                                        const void *Decoder) {
 865   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 866   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 867   return MCDisassembler::Success;
 868 }
 869
 870 static DecodeStatus DecodeSimm16(MCInst &Inst,
 871                                  unsigned Insn,
 872                                  uint64_t Address,
 873                                  const void *Decoder) {
 874   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 875   return MCDisassembler::Success;
 876 }
 877
 878 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 879                                  unsigned Insn,
 880                                  uint64_t Address,
 881                                  const void *Decoder) {
 882   // We add one to the immediate field as it was encoded as 'imm - 1'.
 883   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
 884   return MCDisassembler::Success;
 885 }
 886
 887 static DecodeStatus DecodeInsSize(MCInst &Inst,
 888                                   unsigned Insn,
 889                                   uint64_t Address,
 890                                   const void *Decoder) {
 891   // First we need to grab the pos(lsb) from MCInst.
 892   int Pos = Inst.getOperand(2).getImm();
 893   int Size = (int) Insn - Pos + 1;
 894   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 895   return MCDisassembler::Success;
 896 }
 897
 898 static DecodeStatus DecodeExtSize(MCInst &Inst,
 899                                   unsigned Insn,
 900                                   uint64_t Address,
 901                                   const void *Decoder) {
 902   int Size = (int) Insn  + 1;
 903   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 904   return MCDisassembler::Success;
 905 }