lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Ctx, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   bool isMips32r6() const {
  67     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  68   }
  69
  70   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  71
  72   /// getInstruction - See MCDisassembler.
  73   DecodeStatus getInstruction(MCInst &instr,
  74                               uint64_t &size,
  75                               const MemoryObject &region,
  76                               uint64_t address,
  77                               raw_ostream &vStream,
  78                               raw_ostream &cStream) const override;
  79 };
  80
  81
  82 /// Mips64Disassembler - a disasembler class for Mips64.
  83 class Mips64Disassembler : public MipsDisassemblerBase {
  84 public:
  85   /// Constructor     - Initializes the disassembler.
  86   ///
  87   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  88                      bool bigEndian) :
  89     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  90
  91   /// getInstruction - See MCDisassembler.
  92   DecodeStatus getInstruction(MCInst &instr,
  93                               uint64_t &size,
  94                               const MemoryObject &region,
  95                               uint64_t address,
  96                               raw_ostream &vStream,
  97                               raw_ostream &cStream) const override;
  98 };
  99
 100 } // end anonymous namespace
 101
 102 // Forward declare these because the autogenerated code will reference them.
 103 // Definitions are further down.
 104 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 105                                              unsigned RegNo,
 106                                              uint64_t Address,
 107                                              const void *Decoder);
 108
 109 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 110                                                  unsigned RegNo,
 111                                                  uint64_t Address,
 112                                                  const void *Decoder);
 113
 114 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 115                                              unsigned RegNo,
 116                                              uint64_t Address,
 117                                              const void *Decoder);
 118
 119 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 120                                            unsigned Insn,
 121                                            uint64_t Address,
 122                                            const void *Decoder);
 123
 124 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 125                                             unsigned RegNo,
 126                                             uint64_t Address,
 127                                             const void *Decoder);
 128
 129 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 130                                              unsigned RegNo,
 131                                              uint64_t Address,
 132                                              const void *Decoder);
 133
 134 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 135                                              unsigned RegNo,
 136                                              uint64_t Address,
 137                                              const void *Decoder);
 138
 139 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 140                                               unsigned RegNo,
 141                                               uint64_t Address,
 142                                               const void *Decoder);
 143
 144 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 145                                            unsigned RegNo,
 146                                            uint64_t Address,
 147                                            const void *Decoder);
 148
 149 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 150                                            unsigned RegNo,
 151                                            uint64_t Address,
 152                                            const void *Decoder);
 153
 154 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 155                                              uint64_t Address,
 156                                              const void *Decoder);
 157
 158 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 159                                               unsigned Insn,
 160                                               uint64_t Address,
 161                                               const void *Decoder);
 162
 163 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 164                                               unsigned RegNo,
 165                                               uint64_t Address,
 166                                               const void *Decoder);
 167
 168 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 169                                                 unsigned RegNo,
 170                                                 uint64_t Address,
 171                                                 const void *Decoder);
 172
 173 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 199                                                unsigned RegNo,
 200                                                uint64_t Address,
 201                                                const void *Decoder);
 202
 203 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 204                                                unsigned RegNo,
 205                                                uint64_t Address,
 206                                                const void *Decoder);
 207
 208 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 209                                             unsigned RegNo,
 210                                             uint64_t Address,
 211                                             const void *Decoder);
 212
 213 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 214                                        unsigned Offset,
 215                                        uint64_t Address,
 216                                        const void *Decoder);
 217
 218 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 219                                      unsigned Insn,
 220                                      uint64_t Address,
 221                                      const void *Decoder);
 222
 223 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 224                                          unsigned Offset,
 225                                          uint64_t Address,
 226                                          const void *Decoder);
 227
 228 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 229                                          unsigned Offset,
 230                                          uint64_t Address,
 231                                          const void *Decoder);
 232
 233 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 234 // shifted left by 1 bit.
 235 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 236                                          unsigned Offset,
 237                                          uint64_t Address,
 238                                          const void *Decoder);
 239
 240 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 241 // shifted left by 1 bit.
 242 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 243                                        unsigned Insn,
 244                                        uint64_t Address,
 245                                        const void *Decoder);
 246
 247 static DecodeStatus DecodeMem(MCInst &Inst,
 248                               unsigned Insn,
 249                               uint64_t Address,
 250                               const void *Decoder);
 251
 252 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 253                                     uint64_t Address, const void *Decoder);
 254
 255 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 256                                      unsigned Insn,
 257                                      uint64_t Address,
 258                                      const void *Decoder);
 259
 260 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 261                                      unsigned Insn,
 262                                      uint64_t Address,
 263                                      const void *Decoder);
 264
 265 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 266                                uint64_t Address,
 267                                const void *Decoder);
 268
 269 static DecodeStatus DecodeSimm16(MCInst &Inst,
 270                                  unsigned Insn,
 271                                  uint64_t Address,
 272                                  const void *Decoder);
 273
 274 // Decode the immediate field of an LSA instruction which
 275 // is off by one.
 276 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 277                                  unsigned Insn,
 278                                  uint64_t Address,
 279                                  const void *Decoder);
 280
 281 static DecodeStatus DecodeInsSize(MCInst &Inst,
 282                                   unsigned Insn,
 283                                   uint64_t Address,
 284                                   const void *Decoder);
 285
 286 static DecodeStatus DecodeExtSize(MCInst &Inst,
 287                                   unsigned Insn,
 288                                   uint64_t Address,
 289                                   const void *Decoder);
 290
 291 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 292                                      uint64_t Address, const void *Decoder);
 293
 294 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 295                                      uint64_t Address, const void *Decoder);
 296
 297 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 298 /// handle.
 299 template <typename InsnType>
 300 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 301                                    const void *Decoder);
 302
 303 template <typename InsnType>
 304 static DecodeStatus
 305 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 306                       const void *Decoder);
 307
 308 template <typename InsnType>
 309 static DecodeStatus
 310 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 311                        const void *Decoder);
 312
 313 template <typename InsnType>
 314 static DecodeStatus
 315 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 316                        const void *Decoder);
 317
 318 template <typename InsnType>
 319 static DecodeStatus
 320 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 321                        const void *Decoder);
 322
 323 template <typename InsnType>
 324 static DecodeStatus
 325 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 326                       const void *Decoder);
 327
 328 template <typename InsnType>
 329 static DecodeStatus
 330 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 331                        const void *Decoder);
 332
 333 namespace llvm {
 334 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 335               TheMips64elTarget;
 336 }
 337
 338 static MCDisassembler *createMipsDisassembler(
 339                        const Target &T,
 340                        const MCSubtargetInfo &STI,
 341                        MCContext &Ctx) {
 342   return new MipsDisassembler(STI, Ctx, true);
 343 }
 344
 345 static MCDisassembler *createMipselDisassembler(
 346                        const Target &T,
 347                        const MCSubtargetInfo &STI,
 348                        MCContext &Ctx) {
 349   return new MipsDisassembler(STI, Ctx, false);
 350 }
 351
 352 static MCDisassembler *createMips64Disassembler(
 353                        const Target &T,
 354                        const MCSubtargetInfo &STI,
 355                        MCContext &Ctx) {
 356   return new Mips64Disassembler(STI, Ctx, true);
 357 }
 358
 359 static MCDisassembler *createMips64elDisassembler(
 360                        const Target &T,
 361                        const MCSubtargetInfo &STI,
 362                        MCContext &Ctx) {
 363   return new Mips64Disassembler(STI, Ctx, false);
 364 }
 365
 366 extern "C" void LLVMInitializeMipsDisassembler() {
 367   // Register the disassembler.
 368   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 369                                          createMipsDisassembler);
 370   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 371                                          createMipselDisassembler);
 372   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 373                                          createMips64Disassembler);
 374   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 375                                          createMips64elDisassembler);
 376 }
 377
 378 #include "MipsGenDisassemblerTables.inc"
 379
 380 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 381   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 382   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 383   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 384 }
 385
 386 template <typename InsnType>
 387 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 388                                    const void *Decoder) {
 389   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 390   // The size of the n field depends on the element size
 391   // The register class also depends on this.
 392   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 393   unsigned NSize = 0;
 394   DecodeFN RegDecoder = nullptr;
 395   if ((tmp & 0x18) == 0x00) { // INSVE_B
 396     NSize = 4;
 397     RegDecoder = DecodeMSA128BRegisterClass;
 398   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 399     NSize = 3;
 400     RegDecoder = DecodeMSA128HRegisterClass;
 401   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 402     NSize = 2;
 403     RegDecoder = DecodeMSA128WRegisterClass;
 404   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 405     NSize = 1;
 406     RegDecoder = DecodeMSA128DRegisterClass;
 407   } else
 408     llvm_unreachable("Invalid encoding");
 409
 410   assert(NSize != 0 && RegDecoder != nullptr);
 411
 412   // $wd
 413   tmp = fieldFromInstruction(insn, 6, 5);
 414   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 415     return MCDisassembler::Fail;
 416   // $wd_in
 417   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 418     return MCDisassembler::Fail;
 419   // $n
 420   tmp = fieldFromInstruction(insn, 16, NSize);
 421   MI.addOperand(MCOperand::CreateImm(tmp));
 422   // $ws
 423   tmp = fieldFromInstruction(insn, 11, 5);
 424   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 425     return MCDisassembler::Fail;
 426   // $n2
 427   MI.addOperand(MCOperand::CreateImm(0));
 428
 429   return MCDisassembler::Success;
 430 }
 431
 432 template <typename InsnType>
 433 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 434                                           uint64_t Address,
 435                                           const void *Decoder) {
 436   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 437   // (otherwise we would have matched the ADDI instruction from the earlier
 438   // ISA's instead).
 439   //
 440   // We have:
 441   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 442   //      BOVC if rs >= rt
 443   //      BEQZALC if rs == 0 && rt != 0
 444   //      BEQC if rs < rt && rs != 0
 445
 446   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 447   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 448   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 449   bool HasRs = false;
 450
 451   if (Rs >= Rt) {
 452     MI.setOpcode(Mips::BOVC);
 453     HasRs = true;
 454   } else if (Rs != 0 && Rs < Rt) {
 455     MI.setOpcode(Mips::BEQC);
 456     HasRs = true;
 457   } else
 458     MI.setOpcode(Mips::BEQZALC);
 459
 460   if (HasRs)
 461     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 462                                        Rs)));
 463
 464   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 465                                      Rt)));
 466   MI.addOperand(MCOperand::CreateImm(Imm));
 467
 468   return MCDisassembler::Success;
 469 }
 470
 471 template <typename InsnType>
 472 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 473                                            uint64_t Address,
 474                                            const void *Decoder) {
 475   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 476   // (otherwise we would have matched the ADDI instruction from the earlier
 477   // ISA's instead).
 478   //
 479   // We have:
 480   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 481   //      BNVC if rs >= rt
 482   //      BNEZALC if rs == 0 && rt != 0
 483   //      BNEC if rs < rt && rs != 0
 484
 485   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 486   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 487   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 488   bool HasRs = false;
 489
 490   if (Rs >= Rt) {
 491     MI.setOpcode(Mips::BNVC);
 492     HasRs = true;
 493   } else if (Rs != 0 && Rs < Rt) {
 494     MI.setOpcode(Mips::BNEC);
 495     HasRs = true;
 496   } else
 497     MI.setOpcode(Mips::BNEZALC);
 498
 499   if (HasRs)
 500     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 501                                        Rs)));
 502
 503   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 504                                      Rt)));
 505   MI.addOperand(MCOperand::CreateImm(Imm));
 506
 507   return MCDisassembler::Success;
 508 }
 509
 510 template <typename InsnType>
 511 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 512                                            uint64_t Address,
 513                                            const void *Decoder) {
 514   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 515   // (otherwise we would have matched the BLEZL instruction from the earlier
 516   // ISA's instead).
 517   //
 518   // We have:
 519   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 520   //      Invalid if rs == 0
 521   //      BLEZC   if rs == 0  && rt != 0
 522   //      BGEZC   if rs == rt && rt != 0
 523   //      BGEC    if rs != rt && rs != 0  && rt != 0
 524
 525   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 526   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 527   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 528   bool HasRs = false;
 529
 530   if (Rt == 0)
 531     return MCDisassembler::Fail;
 532   else if (Rs == 0)
 533     MI.setOpcode(Mips::BLEZC);
 534   else if (Rs == Rt)
 535     MI.setOpcode(Mips::BGEZC);
 536   else {
 537     HasRs = true;
 538     MI.setOpcode(Mips::BGEC);
 539   }
 540
 541   if (HasRs)
 542     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 543                                        Rs)));
 544
 545   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 546                                      Rt)));
 547
 548   MI.addOperand(MCOperand::CreateImm(Imm));
 549
 550   return MCDisassembler::Success;
 551 }
 552
 553 template <typename InsnType>
 554 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 555                                            uint64_t Address,
 556                                            const void *Decoder) {
 557   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 558   // (otherwise we would have matched the BGTZL instruction from the earlier
 559   // ISA's instead).
 560   //
 561   // We have:
 562   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 563   //      Invalid if rs == 0
 564   //      BGTZC   if rs == 0  && rt != 0
 565   //      BLTZC   if rs == rt && rt != 0
 566   //      BLTC    if rs != rt && rs != 0  && rt != 0
 567
 568   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 569   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 570   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 571
 572   if (Rt == 0)
 573     return MCDisassembler::Fail;
 574   else if (Rs == 0)
 575     MI.setOpcode(Mips::BGTZC);
 576   else if (Rs == Rt)
 577     MI.setOpcode(Mips::BLTZC);
 578   else
 579     return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
 580
 581   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 582                                      Rt)));
 583
 584   MI.addOperand(MCOperand::CreateImm(Imm));
 585
 586   return MCDisassembler::Success;
 587 }
 588
 589 template <typename InsnType>
 590 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 591                                           uint64_t Address,
 592                                           const void *Decoder) {
 593   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 594   // (otherwise we would have matched the BGTZ instruction from the earlier
 595   // ISA's instead).
 596   //
 597   // We have:
 598   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 599   //      BGTZ    if rt == 0
 600   //      BGTZALC if rs == 0 && rt != 0
 601   //      BLTZALC if rs != 0 && rs == rt
 602   //      BLTUC   if rs != 0 && rs != rt
 603
 604   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 605   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 606   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 607   bool HasRs = false;
 608   bool HasRt = false;
 609
 610   if (Rt == 0) {
 611     MI.setOpcode(Mips::BGTZ);
 612     HasRs = true;
 613   } else if (Rs == 0) {
 614     MI.setOpcode(Mips::BGTZALC);
 615     HasRt = true;
 616   } else if (Rs == Rt) {
 617     MI.setOpcode(Mips::BLTZALC);
 618     HasRs = true;
 619   } else
 620     return MCDisassembler::Fail; // BLTUC not implemented yet
 621
 622   if (HasRs)
 623     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 624                                        Rs)));
 625
 626   if (HasRt)
 627     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 628                                        Rt)));
 629
 630   MI.addOperand(MCOperand::CreateImm(Imm));
 631
 632   return MCDisassembler::Success;
 633 }
 634
 635 template <typename InsnType>
 636 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 637                                            uint64_t Address,
 638                                            const void *Decoder) {
 639   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 640   // (otherwise we would have matched the BLEZL instruction from the earlier
 641   // ISA's instead).
 642   //
 643   // We have:
 644   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 645   //      Invalid   if rs == 0
 646   //      BLEZALC   if rs == 0  && rt != 0
 647   //      BGEZALC   if rs == rt && rt != 0
 648   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 649
 650   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 651   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 652   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 653   bool HasRs = false;
 654
 655   if (Rt == 0)
 656     return MCDisassembler::Fail;
 657   else if (Rs == 0)
 658     MI.setOpcode(Mips::BLEZALC);
 659   else if (Rs == Rt)
 660     MI.setOpcode(Mips::BGEZALC);
 661   else {
 662     HasRs = true;
 663     MI.setOpcode(Mips::BGEUC);
 664   }
 665
 666   if (HasRs)
 667     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 668                                        Rs)));
 669   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 670                                      Rt)));
 671
 672   MI.addOperand(MCOperand::CreateImm(Imm));
 673
 674   return MCDisassembler::Success;
 675 }
 676
 677   /// readInstruction - read four bytes from the MemoryObject
 678   /// and return 32 bit word sorted according to the given endianess
 679 static DecodeStatus readInstruction32(const MemoryObject &region,
 680                                       uint64_t address,
 681                                       uint64_t &size,
 682                                       uint32_t &insn,
 683                                       bool isBigEndian,
 684                                       bool IsMicroMips) {
 685   uint8_t Bytes[4];
 686
 687   // We want to read exactly 4 Bytes of data.
 688   if (region.readBytes(address, 4, Bytes) == -1) {
 689     size = 0;
 690     return MCDisassembler::Fail;
 691   }
 692
 693   if (isBigEndian) {
 694     // Encoded as a big-endian 32-bit word in the stream.
 695     insn = (Bytes[3] <<  0) |
 696            (Bytes[2] <<  8) |
 697            (Bytes[1] << 16) |
 698            (Bytes[0] << 24);
 699   }
 700   else {
 701     // Encoded as a small-endian 32-bit word in the stream.
 702     // Little-endian byte ordering:
 703     //   mips32r2:   4 | 3 | 2 | 1
 704     //   microMIPS:  2 | 1 | 4 | 3
 705     if (IsMicroMips) {
 706       insn = (Bytes[2] <<  0) |
 707              (Bytes[3] <<  8) |
 708              (Bytes[0] << 16) |
 709              (Bytes[1] << 24);
 710     } else {
 711       insn = (Bytes[0] <<  0) |
 712              (Bytes[1] <<  8) |
 713              (Bytes[2] << 16) |
 714              (Bytes[3] << 24);
 715     }
 716   }
 717
 718   return MCDisassembler::Success;
 719 }
 720
 721 DecodeStatus
 722 MipsDisassembler::getInstruction(MCInst &instr,
 723                                  uint64_t &Size,
 724                                  const MemoryObject &Region,
 725                                  uint64_t Address,
 726                                  raw_ostream &vStream,
 727                                  raw_ostream &cStream) const {
 728   uint32_t Insn;
 729
 730   DecodeStatus Result = readInstruction32(Region, Address, Size,
 731                                           Insn, isBigEndian, IsMicroMips);
 732   if (Result == MCDisassembler::Fail)
 733     return MCDisassembler::Fail;
 734
 735   if (IsMicroMips) {
 736     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 737     // Calling the auto-generated decoder function.
 738     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 739                                this, STI);
 740     if (Result != MCDisassembler::Fail) {
 741       Size = 4;
 742       return Result;
 743     }
 744     return MCDisassembler::Fail;
 745   }
 746
 747   if (isMips32r6() && isGP64()) {
 748     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 749     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 750                                Address, this, STI);
 751     if (Result != MCDisassembler::Fail) {
 752       Size = 4;
 753       return Result;
 754     }
 755   }
 756
 757   if (isMips32r6()) {
 758     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 759     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 760                                Address, this, STI);
 761     if (Result != MCDisassembler::Fail) {
 762       Size = 4;
 763       return Result;
 764     }
 765   }
 766
 767   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 768   // Calling the auto-generated decoder function.
 769   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 770                              this, STI);
 771   if (Result != MCDisassembler::Fail) {
 772     Size = 4;
 773     return Result;
 774   }
 775
 776   return MCDisassembler::Fail;
 777 }
 778
 779 DecodeStatus
 780 Mips64Disassembler::getInstruction(MCInst &instr,
 781                                    uint64_t &Size,
 782                                    const MemoryObject &Region,
 783                                    uint64_t Address,
 784                                    raw_ostream &vStream,
 785                                    raw_ostream &cStream) const {
 786   uint32_t Insn;
 787
 788   DecodeStatus Result = readInstruction32(Region, Address, Size,
 789                                           Insn, isBigEndian, false);
 790   if (Result == MCDisassembler::Fail)
 791     return MCDisassembler::Fail;
 792
 793   // Calling the auto-generated decoder function.
 794   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 795                              this, STI);
 796   if (Result != MCDisassembler::Fail) {
 797     Size = 4;
 798     return Result;
 799   }
 800   // If we fail to decode in Mips64 decoder space we can try in Mips32
 801   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 802                              this, STI);
 803   if (Result != MCDisassembler::Fail) {
 804     Size = 4;
 805     return Result;
 806   }
 807
 808   return MCDisassembler::Fail;
 809 }
 810
 811 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 812                                                  unsigned RegNo,
 813                                                  uint64_t Address,
 814                                                  const void *Decoder) {
 815
 816   return MCDisassembler::Fail;
 817
 818 }
 819
 820 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 821                                              unsigned RegNo,
 822                                              uint64_t Address,
 823                                              const void *Decoder) {
 824
 825   if (RegNo > 31)
 826     return MCDisassembler::Fail;
 827
 828   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 829   Inst.addOperand(MCOperand::CreateReg(Reg));
 830   return MCDisassembler::Success;
 831 }
 832
 833 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 834                                              unsigned RegNo,
 835                                              uint64_t Address,
 836                                              const void *Decoder) {
 837   if (RegNo > 31)
 838     return MCDisassembler::Fail;
 839   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 840   Inst.addOperand(MCOperand::CreateReg(Reg));
 841   return MCDisassembler::Success;
 842 }
 843
 844 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 845                                            unsigned RegNo,
 846                                            uint64_t Address,
 847                                            const void *Decoder) {
 848   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 849     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 850
 851   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 852 }
 853
 854 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 855                                             unsigned RegNo,
 856                                             uint64_t Address,
 857                                             const void *Decoder) {
 858   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 859 }
 860
 861 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 862                                              unsigned RegNo,
 863                                              uint64_t Address,
 864                                              const void *Decoder) {
 865   if (RegNo > 31)
 866     return MCDisassembler::Fail;
 867
 868   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 869   Inst.addOperand(MCOperand::CreateReg(Reg));
 870   return MCDisassembler::Success;
 871 }
 872
 873 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 874                                              unsigned RegNo,
 875                                              uint64_t Address,
 876                                              const void *Decoder) {
 877   if (RegNo > 31)
 878     return MCDisassembler::Fail;
 879
 880   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 881   Inst.addOperand(MCOperand::CreateReg(Reg));
 882   return MCDisassembler::Success;
 883 }
 884
 885 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 886                                               unsigned RegNo,
 887                                               uint64_t Address,
 888                                               const void *Decoder) {
 889   if (RegNo > 31)
 890     return MCDisassembler::Fail;
 891
 892   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 893   Inst.addOperand(MCOperand::CreateReg(Reg));
 894   return MCDisassembler::Success;
 895 }
 896
 897 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 898                                            unsigned RegNo,
 899                                            uint64_t Address,
 900                                            const void *Decoder) {
 901   if (RegNo > 31)
 902     return MCDisassembler::Fail;
 903   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 904   Inst.addOperand(MCOperand::CreateReg(Reg));
 905   return MCDisassembler::Success;
 906 }
 907
 908 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 909                                            unsigned RegNo,
 910                                            uint64_t Address,
 911                                            const void *Decoder) {
 912   if (RegNo > 7)
 913     return MCDisassembler::Fail;
 914   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 915   Inst.addOperand(MCOperand::CreateReg(Reg));
 916   return MCDisassembler::Success;
 917 }
 918
 919 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 920                                              uint64_t Address,
 921                                              const void *Decoder) {
 922   if (RegNo > 31)
 923     return MCDisassembler::Fail;
 924
 925   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 926   Inst.addOperand(MCOperand::CreateReg(Reg));
 927   return MCDisassembler::Success;
 928 }
 929
 930 static DecodeStatus DecodeMem(MCInst &Inst,
 931                               unsigned Insn,
 932                               uint64_t Address,
 933                               const void *Decoder) {
 934   int Offset = SignExtend32<16>(Insn & 0xffff);
 935   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 936   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 937
 938   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 939   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 940
 941   if(Inst.getOpcode() == Mips::SC){
 942     Inst.addOperand(MCOperand::CreateReg(Reg));
 943   }
 944
 945   Inst.addOperand(MCOperand::CreateReg(Reg));
 946   Inst.addOperand(MCOperand::CreateReg(Base));
 947   Inst.addOperand(MCOperand::CreateImm(Offset));
 948
 949   return MCDisassembler::Success;
 950 }
 951
 952 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 953                                     uint64_t Address, const void *Decoder) {
 954   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 955   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 956   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 957
 958   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 959   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 960
 961   Inst.addOperand(MCOperand::CreateReg(Reg));
 962   Inst.addOperand(MCOperand::CreateReg(Base));
 963
 964   // The immediate field of an LD/ST instruction is scaled which means it must
 965   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 966   // data format.
 967   // .b - 1 byte
 968   // .h - 2 bytes
 969   // .w - 4 bytes
 970   // .d - 8 bytes
 971   switch(Inst.getOpcode())
 972   {
 973   default:
 974     assert (0 && "Unexpected instruction");
 975     return MCDisassembler::Fail;
 976     break;
 977   case Mips::LD_B:
 978   case Mips::ST_B:
 979     Inst.addOperand(MCOperand::CreateImm(Offset));
 980     break;
 981   case Mips::LD_H:
 982   case Mips::ST_H:
 983     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 984     break;
 985   case Mips::LD_W:
 986   case Mips::ST_W:
 987     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 988     break;
 989   case Mips::LD_D:
 990   case Mips::ST_D:
 991     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 992     break;
 993   }
 994
 995   return MCDisassembler::Success;
 996 }
 997
 998 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 999                                      unsigned Insn,
1000                                      uint64_t Address,
1001                                      const void *Decoder) {
1002   int Offset = SignExtend32<12>(Insn & 0x0fff);
1003   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1004   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1005
1006   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1007   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1008
1009   if (Inst.getOpcode() == Mips::SC_MM)
1010     Inst.addOperand(MCOperand::CreateReg(Reg));
1011
1012   Inst.addOperand(MCOperand::CreateReg(Reg));
1013   Inst.addOperand(MCOperand::CreateReg(Base));
1014   Inst.addOperand(MCOperand::CreateImm(Offset));
1015
1016   return MCDisassembler::Success;
1017 }
1018
1019 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1020                                      unsigned Insn,
1021                                      uint64_t Address,
1022                                      const void *Decoder) {
1023   int Offset = SignExtend32<16>(Insn & 0xffff);
1024   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1025   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1026
1027   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1028   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1029
1030   Inst.addOperand(MCOperand::CreateReg(Reg));
1031   Inst.addOperand(MCOperand::CreateReg(Base));
1032   Inst.addOperand(MCOperand::CreateImm(Offset));
1033
1034   return MCDisassembler::Success;
1035 }
1036
1037 static DecodeStatus DecodeFMem(MCInst &Inst,
1038                                unsigned Insn,
1039                                uint64_t Address,
1040                                const void *Decoder) {
1041   int Offset = SignExtend32<16>(Insn & 0xffff);
1042   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1043   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1044
1045   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1046   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1047
1048   Inst.addOperand(MCOperand::CreateReg(Reg));
1049   Inst.addOperand(MCOperand::CreateReg(Base));
1050   Inst.addOperand(MCOperand::CreateImm(Offset));
1051
1052   return MCDisassembler::Success;
1053 }
1054
1055
1056 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1057                                               unsigned RegNo,
1058                                               uint64_t Address,
1059                                               const void *Decoder) {
1060   // Currently only hardware register 29 is supported.
1061   if (RegNo != 29)
1062     return  MCDisassembler::Fail;
1063   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1064   return MCDisassembler::Success;
1065 }
1066
1067 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1068                                               unsigned RegNo,
1069                                               uint64_t Address,
1070                                               const void *Decoder) {
1071   if (RegNo > 30 || RegNo %2)
1072     return MCDisassembler::Fail;
1073
1074   ;
1075   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1076   Inst.addOperand(MCOperand::CreateReg(Reg));
1077   return MCDisassembler::Success;
1078 }
1079
1080 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1081                                                 unsigned RegNo,
1082                                                 uint64_t Address,
1083                                                 const void *Decoder) {
1084   if (RegNo >= 4)
1085     return MCDisassembler::Fail;
1086
1087   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1088   Inst.addOperand(MCOperand::CreateReg(Reg));
1089   return MCDisassembler::Success;
1090 }
1091
1092 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1093                                                unsigned RegNo,
1094                                                uint64_t Address,
1095                                                const void *Decoder) {
1096   if (RegNo >= 4)
1097     return MCDisassembler::Fail;
1098
1099   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1100   Inst.addOperand(MCOperand::CreateReg(Reg));
1101   return MCDisassembler::Success;
1102 }
1103
1104 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1105                                                unsigned RegNo,
1106                                                uint64_t Address,
1107                                                const void *Decoder) {
1108   if (RegNo >= 4)
1109     return MCDisassembler::Fail;
1110
1111   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1112   Inst.addOperand(MCOperand::CreateReg(Reg));
1113   return MCDisassembler::Success;
1114 }
1115
1116 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1117                                                unsigned RegNo,
1118                                                uint64_t Address,
1119                                                const void *Decoder) {
1120   if (RegNo > 31)
1121     return MCDisassembler::Fail;
1122
1123   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1124   Inst.addOperand(MCOperand::CreateReg(Reg));
1125   return MCDisassembler::Success;
1126 }
1127
1128 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1129                                                unsigned RegNo,
1130                                                uint64_t Address,
1131                                                const void *Decoder) {
1132   if (RegNo > 31)
1133     return MCDisassembler::Fail;
1134
1135   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1136   Inst.addOperand(MCOperand::CreateReg(Reg));
1137   return MCDisassembler::Success;
1138 }
1139
1140 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1141                                                unsigned RegNo,
1142                                                uint64_t Address,
1143                                                const void *Decoder) {
1144   if (RegNo > 31)
1145     return MCDisassembler::Fail;
1146
1147   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1148   Inst.addOperand(MCOperand::CreateReg(Reg));
1149   return MCDisassembler::Success;
1150 }
1151
1152 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1153                                                unsigned RegNo,
1154                                                uint64_t Address,
1155                                                const void *Decoder) {
1156   if (RegNo > 31)
1157     return MCDisassembler::Fail;
1158
1159   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1160   Inst.addOperand(MCOperand::CreateReg(Reg));
1161   return MCDisassembler::Success;
1162 }
1163
1164 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1165                                                unsigned RegNo,
1166                                                uint64_t Address,
1167                                                const void *Decoder) {
1168   if (RegNo > 7)
1169     return MCDisassembler::Fail;
1170
1171   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1172   Inst.addOperand(MCOperand::CreateReg(Reg));
1173   return MCDisassembler::Success;
1174 }
1175
1176 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1177                                             unsigned RegNo,
1178                                             uint64_t Address,
1179                                             const void *Decoder) {
1180   if (RegNo > 31)
1181     return MCDisassembler::Fail;
1182
1183   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1184   Inst.addOperand(MCOperand::CreateReg(Reg));
1185   return MCDisassembler::Success;
1186 }
1187
1188 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1189                                        unsigned Offset,
1190                                        uint64_t Address,
1191                                        const void *Decoder) {
1192   int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1193   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1194   return MCDisassembler::Success;
1195 }
1196
1197 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1198                                      unsigned Insn,
1199                                      uint64_t Address,
1200                                      const void *Decoder) {
1201
1202   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1203   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1204   return MCDisassembler::Success;
1205 }
1206
1207 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1208                                          unsigned Offset,
1209                                          uint64_t Address,
1210                                          const void *Decoder) {
1211   int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1212
1213   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1214   return MCDisassembler::Success;
1215 }
1216
1217 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1218                                          unsigned Offset,
1219                                          uint64_t Address,
1220                                          const void *Decoder) {
1221   int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1222
1223   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1224   return MCDisassembler::Success;
1225 }
1226
1227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1228                                          unsigned Offset,
1229                                          uint64_t Address,
1230                                          const void *Decoder) {
1231   int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1232   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1233   return MCDisassembler::Success;
1234 }
1235
1236 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1237                                        unsigned Insn,
1238                                        uint64_t Address,
1239                                        const void *Decoder) {
1240   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1241   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1242   return MCDisassembler::Success;
1243 }
1244
1245 static DecodeStatus DecodeSimm16(MCInst &Inst,
1246                                  unsigned Insn,
1247                                  uint64_t Address,
1248                                  const void *Decoder) {
1249   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1250   return MCDisassembler::Success;
1251 }
1252
1253 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1254                                  unsigned Insn,
1255                                  uint64_t Address,
1256                                  const void *Decoder) {
1257   // We add one to the immediate field as it was encoded as 'imm - 1'.
1258   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1259   return MCDisassembler::Success;
1260 }
1261
1262 static DecodeStatus DecodeInsSize(MCInst &Inst,
1263                                   unsigned Insn,
1264                                   uint64_t Address,
1265                                   const void *Decoder) {
1266   // First we need to grab the pos(lsb) from MCInst.
1267   int Pos = Inst.getOperand(2).getImm();
1268   int Size = (int) Insn - Pos + 1;
1269   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1270   return MCDisassembler::Success;
1271 }
1272
1273 static DecodeStatus DecodeExtSize(MCInst &Inst,
1274                                   unsigned Insn,
1275                                   uint64_t Address,
1276                                   const void *Decoder) {
1277   int Size = (int) Insn  + 1;
1278   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1279   return MCDisassembler::Success;
1280 }
1281
1282 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1283                                      uint64_t Address, const void *Decoder) {
1284   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1285   return MCDisassembler::Success;
1286 }
1287
1288 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1289                                      uint64_t Address, const void *Decoder) {
1290   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1291   return MCDisassembler::Success;
1292 }