lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  61       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  62     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  63   }
  64
  65   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  66   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  67   bool hasMips32r6() const {
  68     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  69   }
  70
  71   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  72
  73   bool hasCOP3() const {
  74     // Only present in MIPS-I and MIPS-II
  75     return !hasMips32() && !hasMips3();
  76   }
  77
  78   /// getInstruction - See MCDisassembler.
  79   DecodeStatus getInstruction(MCInst &instr,
  80                               uint64_t &size,
  81                               const MemoryObject &region,
  82                               uint64_t address,
  83                               raw_ostream &vStream,
  84                               raw_ostream &cStream) const override;
  85 };
  86
  87
  88 /// Mips64Disassembler - a disasembler class for Mips64.
  89 class Mips64Disassembler : public MipsDisassemblerBase {
  90 public:
  91   /// Constructor     - Initializes the disassembler.
  92   ///
  93   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  94                      bool bigEndian) :
  95     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  96
  97   /// getInstruction - See MCDisassembler.
  98   DecodeStatus getInstruction(MCInst &instr,
  99                               uint64_t &size,
 100                               const MemoryObject &region,
 101                               uint64_t address,
 102                               raw_ostream &vStream,
 103                               raw_ostream &cStream) const override;
 104 };
 105
 106 } // end anonymous namespace
 107
 108 // Forward declare these because the autogenerated code will reference them.
 109 // Definitions are further down.
 110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 111                                              unsigned RegNo,
 112                                              uint64_t Address,
 113                                              const void *Decoder);
 114
 115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 116                                                  unsigned RegNo,
 117                                                  uint64_t Address,
 118                                                  const void *Decoder);
 119
 120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 121                                              unsigned RegNo,
 122                                              uint64_t Address,
 123                                              const void *Decoder);
 124
 125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 126                                            unsigned Insn,
 127                                            uint64_t Address,
 128                                            const void *Decoder);
 129
 130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 131                                             unsigned RegNo,
 132                                             uint64_t Address,
 133                                             const void *Decoder);
 134
 135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 136                                              unsigned RegNo,
 137                                              uint64_t Address,
 138                                              const void *Decoder);
 139
 140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 141                                              unsigned RegNo,
 142                                              uint64_t Address,
 143                                              const void *Decoder);
 144
 145 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 146                                               unsigned RegNo,
 147                                               uint64_t Address,
 148                                               const void *Decoder);
 149
 150 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 151                                            unsigned RegNo,
 152                                            uint64_t Address,
 153                                            const void *Decoder);
 154
 155 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 156                                            unsigned RegNo,
 157                                            uint64_t Address,
 158                                            const void *Decoder);
 159
 160 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 161                                              uint64_t Address,
 162                                              const void *Decoder);
 163
 164 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 165                                               unsigned Insn,
 166                                               uint64_t Address,
 167                                               const void *Decoder);
 168
 169 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 170                                               unsigned RegNo,
 171                                               uint64_t Address,
 172                                               const void *Decoder);
 173
 174 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 175                                                 unsigned RegNo,
 176                                                 uint64_t Address,
 177                                                 const void *Decoder);
 178
 179 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 180                                                unsigned RegNo,
 181                                                uint64_t Address,
 182                                                const void *Decoder);
 183
 184 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 185                                                unsigned RegNo,
 186                                                uint64_t Address,
 187                                                const void *Decoder);
 188
 189 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 190                                                unsigned RegNo,
 191                                                uint64_t Address,
 192                                                const void *Decoder);
 193
 194 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 195                                                unsigned RegNo,
 196                                                uint64_t Address,
 197                                                const void *Decoder);
 198
 199 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 200                                                unsigned RegNo,
 201                                                uint64_t Address,
 202                                                const void *Decoder);
 203
 204 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 205                                                unsigned RegNo,
 206                                                uint64_t Address,
 207                                                const void *Decoder);
 208
 209 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 210                                                unsigned RegNo,
 211                                                uint64_t Address,
 212                                                const void *Decoder);
 213
 214 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 215                                             unsigned RegNo,
 216                                             uint64_t Address,
 217                                             const void *Decoder);
 218
 219 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 220                                        unsigned Offset,
 221                                        uint64_t Address,
 222                                        const void *Decoder);
 223
 224 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 225                                      unsigned Insn,
 226                                      uint64_t Address,
 227                                      const void *Decoder);
 228
 229 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 235                                          unsigned Offset,
 236                                          uint64_t Address,
 237                                          const void *Decoder);
 238
 239 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 240 // shifted left by 1 bit.
 241 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 242                                          unsigned Offset,
 243                                          uint64_t Address,
 244                                          const void *Decoder);
 245
 246 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 247 // shifted left by 1 bit.
 248 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 249                                        unsigned Insn,
 250                                        uint64_t Address,
 251                                        const void *Decoder);
 252
 253 static DecodeStatus DecodeMem(MCInst &Inst,
 254                               unsigned Insn,
 255                               uint64_t Address,
 256                               const void *Decoder);
 257
 258 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 259                                     uint64_t Address, const void *Decoder);
 260
 261 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 262                                      unsigned Insn,
 263                                      uint64_t Address,
 264                                      const void *Decoder);
 265
 266 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 267                                      unsigned Insn,
 268                                      uint64_t Address,
 269                                      const void *Decoder);
 270
 271 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 272                                uint64_t Address,
 273                                const void *Decoder);
 274
 275 static DecodeStatus DecodeSimm16(MCInst &Inst,
 276                                  unsigned Insn,
 277                                  uint64_t Address,
 278                                  const void *Decoder);
 279
 280 // Decode the immediate field of an LSA instruction which
 281 // is off by one.
 282 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 283                                  unsigned Insn,
 284                                  uint64_t Address,
 285                                  const void *Decoder);
 286
 287 static DecodeStatus DecodeInsSize(MCInst &Inst,
 288                                   unsigned Insn,
 289                                   uint64_t Address,
 290                                   const void *Decoder);
 291
 292 static DecodeStatus DecodeExtSize(MCInst &Inst,
 293                                   unsigned Insn,
 294                                   uint64_t Address,
 295                                   const void *Decoder);
 296
 297 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 298                                      uint64_t Address, const void *Decoder);
 299
 300 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 301                                      uint64_t Address, const void *Decoder);
 302
 303 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 304 /// handle.
 305 template <typename InsnType>
 306 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 307                                    const void *Decoder);
 308
 309 template <typename InsnType>
 310 static DecodeStatus
 311 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 312                       const void *Decoder);
 313
 314 template <typename InsnType>
 315 static DecodeStatus
 316 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 317                        const void *Decoder);
 318
 319 template <typename InsnType>
 320 static DecodeStatus
 321 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 322                        const void *Decoder);
 323
 324 template <typename InsnType>
 325 static DecodeStatus
 326 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 327                        const void *Decoder);
 328
 329 template <typename InsnType>
 330 static DecodeStatus
 331 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 332                       const void *Decoder);
 333
 334 template <typename InsnType>
 335 static DecodeStatus
 336 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 337                        const void *Decoder);
 338
 339 namespace llvm {
 340 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 341               TheMips64elTarget;
 342 }
 343
 344 static MCDisassembler *createMipsDisassembler(
 345                        const Target &T,
 346                        const MCSubtargetInfo &STI,
 347                        MCContext &Ctx) {
 348   return new MipsDisassembler(STI, Ctx, true);
 349 }
 350
 351 static MCDisassembler *createMipselDisassembler(
 352                        const Target &T,
 353                        const MCSubtargetInfo &STI,
 354                        MCContext &Ctx) {
 355   return new MipsDisassembler(STI, Ctx, false);
 356 }
 357
 358 static MCDisassembler *createMips64Disassembler(
 359                        const Target &T,
 360                        const MCSubtargetInfo &STI,
 361                        MCContext &Ctx) {
 362   return new Mips64Disassembler(STI, Ctx, true);
 363 }
 364
 365 static MCDisassembler *createMips64elDisassembler(
 366                        const Target &T,
 367                        const MCSubtargetInfo &STI,
 368                        MCContext &Ctx) {
 369   return new Mips64Disassembler(STI, Ctx, false);
 370 }
 371
 372 extern "C" void LLVMInitializeMipsDisassembler() {
 373   // Register the disassembler.
 374   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 375                                          createMipsDisassembler);
 376   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 377                                          createMipselDisassembler);
 378   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 379                                          createMips64Disassembler);
 380   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 381                                          createMips64elDisassembler);
 382 }
 383
 384 #include "MipsGenDisassemblerTables.inc"
 385
 386 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 387   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 388   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 389   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 390 }
 391
 392 template <typename InsnType>
 393 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 394                                    const void *Decoder) {
 395   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 396   // The size of the n field depends on the element size
 397   // The register class also depends on this.
 398   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 399   unsigned NSize = 0;
 400   DecodeFN RegDecoder = nullptr;
 401   if ((tmp & 0x18) == 0x00) { // INSVE_B
 402     NSize = 4;
 403     RegDecoder = DecodeMSA128BRegisterClass;
 404   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 405     NSize = 3;
 406     RegDecoder = DecodeMSA128HRegisterClass;
 407   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 408     NSize = 2;
 409     RegDecoder = DecodeMSA128WRegisterClass;
 410   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 411     NSize = 1;
 412     RegDecoder = DecodeMSA128DRegisterClass;
 413   } else
 414     llvm_unreachable("Invalid encoding");
 415
 416   assert(NSize != 0 && RegDecoder != nullptr);
 417
 418   // $wd
 419   tmp = fieldFromInstruction(insn, 6, 5);
 420   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 421     return MCDisassembler::Fail;
 422   // $wd_in
 423   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 424     return MCDisassembler::Fail;
 425   // $n
 426   tmp = fieldFromInstruction(insn, 16, NSize);
 427   MI.addOperand(MCOperand::CreateImm(tmp));
 428   // $ws
 429   tmp = fieldFromInstruction(insn, 11, 5);
 430   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 431     return MCDisassembler::Fail;
 432   // $n2
 433   MI.addOperand(MCOperand::CreateImm(0));
 434
 435   return MCDisassembler::Success;
 436 }
 437
 438 template <typename InsnType>
 439 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 440                                           uint64_t Address,
 441                                           const void *Decoder) {
 442   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 443   // (otherwise we would have matched the ADDI instruction from the earlier
 444   // ISA's instead).
 445   //
 446   // We have:
 447   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 448   //      BOVC if rs >= rt
 449   //      BEQZALC if rs == 0 && rt != 0
 450   //      BEQC if rs < rt && rs != 0
 451
 452   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 453   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 454   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 455   bool HasRs = false;
 456
 457   if (Rs >= Rt) {
 458     MI.setOpcode(Mips::BOVC);
 459     HasRs = true;
 460   } else if (Rs != 0 && Rs < Rt) {
 461     MI.setOpcode(Mips::BEQC);
 462     HasRs = true;
 463   } else
 464     MI.setOpcode(Mips::BEQZALC);
 465
 466   if (HasRs)
 467     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 468                                        Rs)));
 469
 470   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 471                                      Rt)));
 472   MI.addOperand(MCOperand::CreateImm(Imm));
 473
 474   return MCDisassembler::Success;
 475 }
 476
 477 template <typename InsnType>
 478 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 479                                            uint64_t Address,
 480                                            const void *Decoder) {
 481   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 482   // (otherwise we would have matched the ADDI instruction from the earlier
 483   // ISA's instead).
 484   //
 485   // We have:
 486   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 487   //      BNVC if rs >= rt
 488   //      BNEZALC if rs == 0 && rt != 0
 489   //      BNEC if rs < rt && rs != 0
 490
 491   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 492   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 493   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 494   bool HasRs = false;
 495
 496   if (Rs >= Rt) {
 497     MI.setOpcode(Mips::BNVC);
 498     HasRs = true;
 499   } else if (Rs != 0 && Rs < Rt) {
 500     MI.setOpcode(Mips::BNEC);
 501     HasRs = true;
 502   } else
 503     MI.setOpcode(Mips::BNEZALC);
 504
 505   if (HasRs)
 506     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 507                                        Rs)));
 508
 509   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 510                                      Rt)));
 511   MI.addOperand(MCOperand::CreateImm(Imm));
 512
 513   return MCDisassembler::Success;
 514 }
 515
 516 template <typename InsnType>
 517 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 518                                            uint64_t Address,
 519                                            const void *Decoder) {
 520   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 521   // (otherwise we would have matched the BLEZL instruction from the earlier
 522   // ISA's instead).
 523   //
 524   // We have:
 525   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 526   //      Invalid if rs == 0
 527   //      BLEZC   if rs == 0  && rt != 0
 528   //      BGEZC   if rs == rt && rt != 0
 529   //      BGEC    if rs != rt && rs != 0  && rt != 0
 530
 531   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 532   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 533   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 534   bool HasRs = false;
 535
 536   if (Rt == 0)
 537     return MCDisassembler::Fail;
 538   else if (Rs == 0)
 539     MI.setOpcode(Mips::BLEZC);
 540   else if (Rs == Rt)
 541     MI.setOpcode(Mips::BGEZC);
 542   else {
 543     HasRs = true;
 544     MI.setOpcode(Mips::BGEC);
 545   }
 546
 547   if (HasRs)
 548     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 549                                        Rs)));
 550
 551   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 552                                      Rt)));
 553
 554   MI.addOperand(MCOperand::CreateImm(Imm));
 555
 556   return MCDisassembler::Success;
 557 }
 558
 559 template <typename InsnType>
 560 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 561                                            uint64_t Address,
 562                                            const void *Decoder) {
 563   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 564   // (otherwise we would have matched the BGTZL instruction from the earlier
 565   // ISA's instead).
 566   //
 567   // We have:
 568   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 569   //      Invalid if rs == 0
 570   //      BGTZC   if rs == 0  && rt != 0
 571   //      BLTZC   if rs == rt && rt != 0
 572   //      BLTC    if rs != rt && rs != 0  && rt != 0
 573
 574   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 575   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 576   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 577
 578   if (Rt == 0)
 579     return MCDisassembler::Fail;
 580   else if (Rs == 0)
 581     MI.setOpcode(Mips::BGTZC);
 582   else if (Rs == Rt)
 583     MI.setOpcode(Mips::BLTZC);
 584   else
 585     return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
 586
 587   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 588                                      Rt)));
 589
 590   MI.addOperand(MCOperand::CreateImm(Imm));
 591
 592   return MCDisassembler::Success;
 593 }
 594
 595 template <typename InsnType>
 596 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 597                                           uint64_t Address,
 598                                           const void *Decoder) {
 599   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 600   // (otherwise we would have matched the BGTZ instruction from the earlier
 601   // ISA's instead).
 602   //
 603   // We have:
 604   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 605   //      BGTZ    if rt == 0
 606   //      BGTZALC if rs == 0 && rt != 0
 607   //      BLTZALC if rs != 0 && rs == rt
 608   //      BLTUC   if rs != 0 && rs != rt
 609
 610   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 611   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 612   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 613   bool HasRs = false;
 614   bool HasRt = false;
 615
 616   if (Rt == 0) {
 617     MI.setOpcode(Mips::BGTZ);
 618     HasRs = true;
 619   } else if (Rs == 0) {
 620     MI.setOpcode(Mips::BGTZALC);
 621     HasRt = true;
 622   } else if (Rs == Rt) {
 623     MI.setOpcode(Mips::BLTZALC);
 624     HasRs = true;
 625   } else
 626     return MCDisassembler::Fail; // BLTUC not implemented yet
 627
 628   if (HasRs)
 629     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 630                                        Rs)));
 631
 632   if (HasRt)
 633     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 634                                        Rt)));
 635
 636   MI.addOperand(MCOperand::CreateImm(Imm));
 637
 638   return MCDisassembler::Success;
 639 }
 640
 641 template <typename InsnType>
 642 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 643                                            uint64_t Address,
 644                                            const void *Decoder) {
 645   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 646   // (otherwise we would have matched the BLEZL instruction from the earlier
 647   // ISA's instead).
 648   //
 649   // We have:
 650   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 651   //      Invalid   if rs == 0
 652   //      BLEZALC   if rs == 0  && rt != 0
 653   //      BGEZALC   if rs == rt && rt != 0
 654   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 655
 656   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 657   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 658   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 659   bool HasRs = false;
 660
 661   if (Rt == 0)
 662     return MCDisassembler::Fail;
 663   else if (Rs == 0)
 664     MI.setOpcode(Mips::BLEZALC);
 665   else if (Rs == Rt)
 666     MI.setOpcode(Mips::BGEZALC);
 667   else {
 668     HasRs = true;
 669     MI.setOpcode(Mips::BGEUC);
 670   }
 671
 672   if (HasRs)
 673     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 674                                        Rs)));
 675   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 676                                      Rt)));
 677
 678   MI.addOperand(MCOperand::CreateImm(Imm));
 679
 680   return MCDisassembler::Success;
 681 }
 682
 683   /// readInstruction - read four bytes from the MemoryObject
 684   /// and return 32 bit word sorted according to the given endianess
 685 static DecodeStatus readInstruction32(const MemoryObject &region,
 686                                       uint64_t address,
 687                                       uint64_t &size,
 688                                       uint32_t &insn,
 689                                       bool isBigEndian,
 690                                       bool IsMicroMips) {
 691   uint8_t Bytes[4];
 692
 693   // We want to read exactly 4 Bytes of data.
 694   if (region.readBytes(address, 4, Bytes) == -1) {
 695     size = 0;
 696     return MCDisassembler::Fail;
 697   }
 698
 699   if (isBigEndian) {
 700     // Encoded as a big-endian 32-bit word in the stream.
 701     insn = (Bytes[3] <<  0) |
 702            (Bytes[2] <<  8) |
 703            (Bytes[1] << 16) |
 704            (Bytes[0] << 24);
 705   }
 706   else {
 707     // Encoded as a small-endian 32-bit word in the stream.
 708     // Little-endian byte ordering:
 709     //   mips32r2:   4 | 3 | 2 | 1
 710     //   microMIPS:  2 | 1 | 4 | 3
 711     if (IsMicroMips) {
 712       insn = (Bytes[2] <<  0) |
 713              (Bytes[3] <<  8) |
 714              (Bytes[0] << 16) |
 715              (Bytes[1] << 24);
 716     } else {
 717       insn = (Bytes[0] <<  0) |
 718              (Bytes[1] <<  8) |
 719              (Bytes[2] << 16) |
 720              (Bytes[3] << 24);
 721     }
 722   }
 723
 724   return MCDisassembler::Success;
 725 }
 726
 727 DecodeStatus
 728 MipsDisassembler::getInstruction(MCInst &instr,
 729                                  uint64_t &Size,
 730                                  const MemoryObject &Region,
 731                                  uint64_t Address,
 732                                  raw_ostream &vStream,
 733                                  raw_ostream &cStream) const {
 734   uint32_t Insn;
 735
 736   DecodeStatus Result = readInstruction32(Region, Address, Size,
 737                                           Insn, isBigEndian, IsMicroMips);
 738   if (Result == MCDisassembler::Fail)
 739     return MCDisassembler::Fail;
 740
 741   if (IsMicroMips) {
 742     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 743     // Calling the auto-generated decoder function.
 744     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 745                                this, STI);
 746     if (Result != MCDisassembler::Fail) {
 747       Size = 4;
 748       return Result;
 749     }
 750     return MCDisassembler::Fail;
 751   }
 752
 753   if (hasCOP3()) {
 754     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 755     Result =
 756         decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
 757     if (Result != MCDisassembler::Fail) {
 758       Size = 4;
 759       return Result;
 760     }
 761   }
 762
 763   if (hasMips32r6() && isGP64()) {
 764     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 765     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 766                                Address, this, STI);
 767     if (Result != MCDisassembler::Fail) {
 768       Size = 4;
 769       return Result;
 770     }
 771   }
 772
 773   if (hasMips32r6()) {
 774     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 775     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 776                                Address, this, STI);
 777     if (Result != MCDisassembler::Fail) {
 778       Size = 4;
 779       return Result;
 780     }
 781   }
 782
 783   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 784   // Calling the auto-generated decoder function.
 785   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 786                              this, STI);
 787   if (Result != MCDisassembler::Fail) {
 788     Size = 4;
 789     return Result;
 790   }
 791
 792   return MCDisassembler::Fail;
 793 }
 794
 795 DecodeStatus
 796 Mips64Disassembler::getInstruction(MCInst &instr,
 797                                    uint64_t &Size,
 798                                    const MemoryObject &Region,
 799                                    uint64_t Address,
 800                                    raw_ostream &vStream,
 801                                    raw_ostream &cStream) const {
 802   uint32_t Insn;
 803
 804   DecodeStatus Result = readInstruction32(Region, Address, Size,
 805                                           Insn, isBigEndian, false);
 806   if (Result == MCDisassembler::Fail)
 807     return MCDisassembler::Fail;
 808
 809   // Calling the auto-generated decoder function.
 810   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 811                              this, STI);
 812   if (Result != MCDisassembler::Fail) {
 813     Size = 4;
 814     return Result;
 815   }
 816   // If we fail to decode in Mips64 decoder space we can try in Mips32
 817   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 818                              this, STI);
 819   if (Result != MCDisassembler::Fail) {
 820     Size = 4;
 821     return Result;
 822   }
 823
 824   return MCDisassembler::Fail;
 825 }
 826
 827 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 828                                                  unsigned RegNo,
 829                                                  uint64_t Address,
 830                                                  const void *Decoder) {
 831
 832   return MCDisassembler::Fail;
 833
 834 }
 835
 836 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 837                                              unsigned RegNo,
 838                                              uint64_t Address,
 839                                              const void *Decoder) {
 840
 841   if (RegNo > 31)
 842     return MCDisassembler::Fail;
 843
 844   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 845   Inst.addOperand(MCOperand::CreateReg(Reg));
 846   return MCDisassembler::Success;
 847 }
 848
 849 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 850                                              unsigned RegNo,
 851                                              uint64_t Address,
 852                                              const void *Decoder) {
 853   if (RegNo > 31)
 854     return MCDisassembler::Fail;
 855   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 856   Inst.addOperand(MCOperand::CreateReg(Reg));
 857   return MCDisassembler::Success;
 858 }
 859
 860 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 861                                            unsigned RegNo,
 862                                            uint64_t Address,
 863                                            const void *Decoder) {
 864   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 865     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 866
 867   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 868 }
 869
 870 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 871                                             unsigned RegNo,
 872                                             uint64_t Address,
 873                                             const void *Decoder) {
 874   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 875 }
 876
 877 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 878                                              unsigned RegNo,
 879                                              uint64_t Address,
 880                                              const void *Decoder) {
 881   if (RegNo > 31)
 882     return MCDisassembler::Fail;
 883
 884   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 885   Inst.addOperand(MCOperand::CreateReg(Reg));
 886   return MCDisassembler::Success;
 887 }
 888
 889 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 890                                              unsigned RegNo,
 891                                              uint64_t Address,
 892                                              const void *Decoder) {
 893   if (RegNo > 31)
 894     return MCDisassembler::Fail;
 895
 896   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 897   Inst.addOperand(MCOperand::CreateReg(Reg));
 898   return MCDisassembler::Success;
 899 }
 900
 901 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 902                                               unsigned RegNo,
 903                                               uint64_t Address,
 904                                               const void *Decoder) {
 905   if (RegNo > 31)
 906     return MCDisassembler::Fail;
 907
 908   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 909   Inst.addOperand(MCOperand::CreateReg(Reg));
 910   return MCDisassembler::Success;
 911 }
 912
 913 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 914                                            unsigned RegNo,
 915                                            uint64_t Address,
 916                                            const void *Decoder) {
 917   if (RegNo > 31)
 918     return MCDisassembler::Fail;
 919   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 920   Inst.addOperand(MCOperand::CreateReg(Reg));
 921   return MCDisassembler::Success;
 922 }
 923
 924 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 925                                            unsigned RegNo,
 926                                            uint64_t Address,
 927                                            const void *Decoder) {
 928   if (RegNo > 7)
 929     return MCDisassembler::Fail;
 930   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 931   Inst.addOperand(MCOperand::CreateReg(Reg));
 932   return MCDisassembler::Success;
 933 }
 934
 935 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 936                                              uint64_t Address,
 937                                              const void *Decoder) {
 938   if (RegNo > 31)
 939     return MCDisassembler::Fail;
 940
 941   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 942   Inst.addOperand(MCOperand::CreateReg(Reg));
 943   return MCDisassembler::Success;
 944 }
 945
 946 static DecodeStatus DecodeMem(MCInst &Inst,
 947                               unsigned Insn,
 948                               uint64_t Address,
 949                               const void *Decoder) {
 950   int Offset = SignExtend32<16>(Insn & 0xffff);
 951   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 952   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 953
 954   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 955   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 956
 957   if(Inst.getOpcode() == Mips::SC){
 958     Inst.addOperand(MCOperand::CreateReg(Reg));
 959   }
 960
 961   Inst.addOperand(MCOperand::CreateReg(Reg));
 962   Inst.addOperand(MCOperand::CreateReg(Base));
 963   Inst.addOperand(MCOperand::CreateImm(Offset));
 964
 965   return MCDisassembler::Success;
 966 }
 967
 968 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 969                                     uint64_t Address, const void *Decoder) {
 970   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 971   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 972   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 973
 974   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 975   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 976
 977   Inst.addOperand(MCOperand::CreateReg(Reg));
 978   Inst.addOperand(MCOperand::CreateReg(Base));
 979
 980   // The immediate field of an LD/ST instruction is scaled which means it must
 981   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 982   // data format.
 983   // .b - 1 byte
 984   // .h - 2 bytes
 985   // .w - 4 bytes
 986   // .d - 8 bytes
 987   switch(Inst.getOpcode())
 988   {
 989   default:
 990     assert (0 && "Unexpected instruction");
 991     return MCDisassembler::Fail;
 992     break;
 993   case Mips::LD_B:
 994   case Mips::ST_B:
 995     Inst.addOperand(MCOperand::CreateImm(Offset));
 996     break;
 997   case Mips::LD_H:
 998   case Mips::ST_H:
 999     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1000     break;
1001   case Mips::LD_W:
1002   case Mips::ST_W:
1003     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1004     break;
1005   case Mips::LD_D:
1006   case Mips::ST_D:
1007     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
1008     break;
1009   }
1010
1011   return MCDisassembler::Success;
1012 }
1013
1014 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1015                                      unsigned Insn,
1016                                      uint64_t Address,
1017                                      const void *Decoder) {
1018   int Offset = SignExtend32<12>(Insn & 0x0fff);
1019   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1020   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1021
1022   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1023   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1024
1025   if (Inst.getOpcode() == Mips::SC_MM)
1026     Inst.addOperand(MCOperand::CreateReg(Reg));
1027
1028   Inst.addOperand(MCOperand::CreateReg(Reg));
1029   Inst.addOperand(MCOperand::CreateReg(Base));
1030   Inst.addOperand(MCOperand::CreateImm(Offset));
1031
1032   return MCDisassembler::Success;
1033 }
1034
1035 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1036                                      unsigned Insn,
1037                                      uint64_t Address,
1038                                      const void *Decoder) {
1039   int Offset = SignExtend32<16>(Insn & 0xffff);
1040   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1041   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1042
1043   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1044   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1045
1046   Inst.addOperand(MCOperand::CreateReg(Reg));
1047   Inst.addOperand(MCOperand::CreateReg(Base));
1048   Inst.addOperand(MCOperand::CreateImm(Offset));
1049
1050   return MCDisassembler::Success;
1051 }
1052
1053 static DecodeStatus DecodeFMem(MCInst &Inst,
1054                                unsigned Insn,
1055                                uint64_t Address,
1056                                const void *Decoder) {
1057   int Offset = SignExtend32<16>(Insn & 0xffff);
1058   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1059   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1060
1061   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1062   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1063
1064   Inst.addOperand(MCOperand::CreateReg(Reg));
1065   Inst.addOperand(MCOperand::CreateReg(Base));
1066   Inst.addOperand(MCOperand::CreateImm(Offset));
1067
1068   return MCDisassembler::Success;
1069 }
1070
1071
1072 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1073                                               unsigned RegNo,
1074                                               uint64_t Address,
1075                                               const void *Decoder) {
1076   // Currently only hardware register 29 is supported.
1077   if (RegNo != 29)
1078     return  MCDisassembler::Fail;
1079   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1080   return MCDisassembler::Success;
1081 }
1082
1083 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1084                                               unsigned RegNo,
1085                                               uint64_t Address,
1086                                               const void *Decoder) {
1087   if (RegNo > 30 || RegNo %2)
1088     return MCDisassembler::Fail;
1089
1090   ;
1091   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1092   Inst.addOperand(MCOperand::CreateReg(Reg));
1093   return MCDisassembler::Success;
1094 }
1095
1096 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1097                                                 unsigned RegNo,
1098                                                 uint64_t Address,
1099                                                 const void *Decoder) {
1100   if (RegNo >= 4)
1101     return MCDisassembler::Fail;
1102
1103   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1104   Inst.addOperand(MCOperand::CreateReg(Reg));
1105   return MCDisassembler::Success;
1106 }
1107
1108 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1109                                                unsigned RegNo,
1110                                                uint64_t Address,
1111                                                const void *Decoder) {
1112   if (RegNo >= 4)
1113     return MCDisassembler::Fail;
1114
1115   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1116   Inst.addOperand(MCOperand::CreateReg(Reg));
1117   return MCDisassembler::Success;
1118 }
1119
1120 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1121                                                unsigned RegNo,
1122                                                uint64_t Address,
1123                                                const void *Decoder) {
1124   if (RegNo >= 4)
1125     return MCDisassembler::Fail;
1126
1127   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1128   Inst.addOperand(MCOperand::CreateReg(Reg));
1129   return MCDisassembler::Success;
1130 }
1131
1132 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1133                                                unsigned RegNo,
1134                                                uint64_t Address,
1135                                                const void *Decoder) {
1136   if (RegNo > 31)
1137     return MCDisassembler::Fail;
1138
1139   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1140   Inst.addOperand(MCOperand::CreateReg(Reg));
1141   return MCDisassembler::Success;
1142 }
1143
1144 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1145                                                unsigned RegNo,
1146                                                uint64_t Address,
1147                                                const void *Decoder) {
1148   if (RegNo > 31)
1149     return MCDisassembler::Fail;
1150
1151   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1152   Inst.addOperand(MCOperand::CreateReg(Reg));
1153   return MCDisassembler::Success;
1154 }
1155
1156 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1157                                                unsigned RegNo,
1158                                                uint64_t Address,
1159                                                const void *Decoder) {
1160   if (RegNo > 31)
1161     return MCDisassembler::Fail;
1162
1163   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1164   Inst.addOperand(MCOperand::CreateReg(Reg));
1165   return MCDisassembler::Success;
1166 }
1167
1168 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1169                                                unsigned RegNo,
1170                                                uint64_t Address,
1171                                                const void *Decoder) {
1172   if (RegNo > 31)
1173     return MCDisassembler::Fail;
1174
1175   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1176   Inst.addOperand(MCOperand::CreateReg(Reg));
1177   return MCDisassembler::Success;
1178 }
1179
1180 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1181                                                unsigned RegNo,
1182                                                uint64_t Address,
1183                                                const void *Decoder) {
1184   if (RegNo > 7)
1185     return MCDisassembler::Fail;
1186
1187   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1188   Inst.addOperand(MCOperand::CreateReg(Reg));
1189   return MCDisassembler::Success;
1190 }
1191
1192 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1193                                             unsigned RegNo,
1194                                             uint64_t Address,
1195                                             const void *Decoder) {
1196   if (RegNo > 31)
1197     return MCDisassembler::Fail;
1198
1199   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1200   Inst.addOperand(MCOperand::CreateReg(Reg));
1201   return MCDisassembler::Success;
1202 }
1203
1204 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1205                                        unsigned Offset,
1206                                        uint64_t Address,
1207                                        const void *Decoder) {
1208   int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1209   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1210   return MCDisassembler::Success;
1211 }
1212
1213 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1214                                      unsigned Insn,
1215                                      uint64_t Address,
1216                                      const void *Decoder) {
1217
1218   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1219   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1220   return MCDisassembler::Success;
1221 }
1222
1223 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1224                                          unsigned Offset,
1225                                          uint64_t Address,
1226                                          const void *Decoder) {
1227   int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1228
1229   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1230   return MCDisassembler::Success;
1231 }
1232
1233 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1234                                          unsigned Offset,
1235                                          uint64_t Address,
1236                                          const void *Decoder) {
1237   int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1238
1239   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1240   return MCDisassembler::Success;
1241 }
1242
1243 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1244                                          unsigned Offset,
1245                                          uint64_t Address,
1246                                          const void *Decoder) {
1247   int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1248   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1249   return MCDisassembler::Success;
1250 }
1251
1252 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1253                                        unsigned Insn,
1254                                        uint64_t Address,
1255                                        const void *Decoder) {
1256   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1257   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1258   return MCDisassembler::Success;
1259 }
1260
1261 static DecodeStatus DecodeSimm16(MCInst &Inst,
1262                                  unsigned Insn,
1263                                  uint64_t Address,
1264                                  const void *Decoder) {
1265   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1266   return MCDisassembler::Success;
1267 }
1268
1269 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1270                                  unsigned Insn,
1271                                  uint64_t Address,
1272                                  const void *Decoder) {
1273   // We add one to the immediate field as it was encoded as 'imm - 1'.
1274   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1275   return MCDisassembler::Success;
1276 }
1277
1278 static DecodeStatus DecodeInsSize(MCInst &Inst,
1279                                   unsigned Insn,
1280                                   uint64_t Address,
1281                                   const void *Decoder) {
1282   // First we need to grab the pos(lsb) from MCInst.
1283   int Pos = Inst.getOperand(2).getImm();
1284   int Size = (int) Insn - Pos + 1;
1285   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1286   return MCDisassembler::Success;
1287 }
1288
1289 static DecodeStatus DecodeExtSize(MCInst &Inst,
1290                                   unsigned Insn,
1291                                   uint64_t Address,
1292                                   const void *Decoder) {
1293   int Size = (int) Insn  + 1;
1294   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1295   return MCDisassembler::Success;
1296 }
1297
1298 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1299                                      uint64_t Address, const void *Decoder) {
1300   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1301   return MCDisassembler::Success;
1302 }
1303
1304 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1305                                      uint64_t Address, const void *Decoder) {
1306   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1307   return MCDisassembler::Success;
1308 }