lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsN64(STI.getFeatureBits() & Mips::FeatureN64),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isN64() const { return IsN64; }
  45
  46 private:
  47   bool IsN64;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 118                                            unsigned Insn,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 123                                             unsigned RegNo,
 124                                             uint64_t Address,
 125                                             const void *Decoder);
 126
 127 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 128                                              unsigned RegNo,
 129                                              uint64_t Address,
 130                                              const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 138                                            unsigned RegNo,
 139                                            uint64_t Address,
 140                                            const void *Decoder);
 141
 142 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 148                                              uint64_t Address,
 149                                              const void *Decoder);
 150
 151 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 152                                               unsigned Insn,
 153                                               uint64_t Address,
 154                                               const void *Decoder);
 155
 156 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 157                                               unsigned RegNo,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 162                                                 unsigned RegNo,
 163                                                 uint64_t Address,
 164                                                 const void *Decoder);
 165
 166 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 202                                             unsigned RegNo,
 203                                             uint64_t Address,
 204                                             const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 207                                        unsigned Offset,
 208                                        uint64_t Address,
 209                                        const void *Decoder);
 210
 211 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 212                                      unsigned Insn,
 213                                      uint64_t Address,
 214                                      const void *Decoder);
 215
 216 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 217                                          unsigned Offset,
 218                                          uint64_t Address,
 219                                          const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 227 // shifted left by 1 bit.
 228 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 229                                          unsigned Offset,
 230                                          uint64_t Address,
 231                                          const void *Decoder);
 232
 233 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 234 // shifted left by 1 bit.
 235 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 236                                        unsigned Insn,
 237                                        uint64_t Address,
 238                                        const void *Decoder);
 239
 240 static DecodeStatus DecodeMem(MCInst &Inst,
 241                               unsigned Insn,
 242                               uint64_t Address,
 243                               const void *Decoder);
 244
 245 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 246                               unsigned Insn,
 247                               uint64_t Address,
 248                               const void *Decoder);
 249
 250 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 251                                     uint64_t Address, const void *Decoder);
 252
 253 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 254                                      unsigned Insn,
 255                                      uint64_t Address,
 256                                      const void *Decoder);
 257
 258 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 259                                      unsigned Insn,
 260                                      uint64_t Address,
 261                                      const void *Decoder);
 262
 263 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 264                                uint64_t Address,
 265                                const void *Decoder);
 266
 267 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 268                                uint64_t Address,
 269                                const void *Decoder);
 270
 271 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 272                                uint64_t Address,
 273                                const void *Decoder);
 274
 275 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 276                                        unsigned Insn,
 277                                        uint64_t Address,
 278                                        const void *Decoder);
 279
 280 static DecodeStatus DecodeSimm16(MCInst &Inst,
 281                                  unsigned Insn,
 282                                  uint64_t Address,
 283                                  const void *Decoder);
 284
 285 // Decode the immediate field of an LSA instruction which
 286 // is off by one.
 287 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 288                                  unsigned Insn,
 289                                  uint64_t Address,
 290                                  const void *Decoder);
 291
 292 static DecodeStatus DecodeInsSize(MCInst &Inst,
 293                                   unsigned Insn,
 294                                   uint64_t Address,
 295                                   const void *Decoder);
 296
 297 static DecodeStatus DecodeExtSize(MCInst &Inst,
 298                                   unsigned Insn,
 299                                   uint64_t Address,
 300                                   const void *Decoder);
 301
 302 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 303                                      uint64_t Address, const void *Decoder);
 304
 305 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 306                                      uint64_t Address, const void *Decoder);
 307
 308 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 309 /// handle.
 310 template <typename InsnType>
 311 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 312                                    const void *Decoder);
 313
 314 template <typename InsnType>
 315 static DecodeStatus
 316 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 317                       const void *Decoder);
 318
 319 template <typename InsnType>
 320 static DecodeStatus
 321 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 322                        const void *Decoder);
 323
 324 template <typename InsnType>
 325 static DecodeStatus
 326 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 327                        const void *Decoder);
 328
 329 template <typename InsnType>
 330 static DecodeStatus
 331 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 332                        const void *Decoder);
 333
 334 template <typename InsnType>
 335 static DecodeStatus
 336 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 337                       const void *Decoder);
 338
 339 template <typename InsnType>
 340 static DecodeStatus
 341 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 342                        const void *Decoder);
 343
 344 namespace llvm {
 345 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 346               TheMips64elTarget;
 347 }
 348
 349 static MCDisassembler *createMipsDisassembler(
 350                        const Target &T,
 351                        const MCSubtargetInfo &STI,
 352                        MCContext &Ctx) {
 353   return new MipsDisassembler(STI, Ctx, true);
 354 }
 355
 356 static MCDisassembler *createMipselDisassembler(
 357                        const Target &T,
 358                        const MCSubtargetInfo &STI,
 359                        MCContext &Ctx) {
 360   return new MipsDisassembler(STI, Ctx, false);
 361 }
 362
 363 static MCDisassembler *createMips64Disassembler(
 364                        const Target &T,
 365                        const MCSubtargetInfo &STI,
 366                        MCContext &Ctx) {
 367   return new Mips64Disassembler(STI, Ctx, true);
 368 }
 369
 370 static MCDisassembler *createMips64elDisassembler(
 371                        const Target &T,
 372                        const MCSubtargetInfo &STI,
 373                        MCContext &Ctx) {
 374   return new Mips64Disassembler(STI, Ctx, false);
 375 }
 376
 377 extern "C" void LLVMInitializeMipsDisassembler() {
 378   // Register the disassembler.
 379   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 380                                          createMipsDisassembler);
 381   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 382                                          createMipselDisassembler);
 383   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 384                                          createMips64Disassembler);
 385   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 386                                          createMips64elDisassembler);
 387 }
 388
 389 #include "MipsGenDisassemblerTables.inc"
 390
 391 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 392   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 393   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 394   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 395 }
 396
 397 template <typename InsnType>
 398 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 399                                    const void *Decoder) {
 400   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 401   // The size of the n field depends on the element size
 402   // The register class also depends on this.
 403   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 404   unsigned NSize = 0;
 405   DecodeFN RegDecoder = nullptr;
 406   if ((tmp & 0x18) == 0x00) { // INSVE_B
 407     NSize = 4;
 408     RegDecoder = DecodeMSA128BRegisterClass;
 409   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 410     NSize = 3;
 411     RegDecoder = DecodeMSA128HRegisterClass;
 412   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 413     NSize = 2;
 414     RegDecoder = DecodeMSA128WRegisterClass;
 415   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 416     NSize = 1;
 417     RegDecoder = DecodeMSA128DRegisterClass;
 418   } else
 419     llvm_unreachable("Invalid encoding");
 420
 421   assert(NSize != 0 && RegDecoder != nullptr);
 422
 423   // $wd
 424   tmp = fieldFromInstruction(insn, 6, 5);
 425   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 426     return MCDisassembler::Fail;
 427   // $wd_in
 428   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 429     return MCDisassembler::Fail;
 430   // $n
 431   tmp = fieldFromInstruction(insn, 16, NSize);
 432   MI.addOperand(MCOperand::CreateImm(tmp));
 433   // $ws
 434   tmp = fieldFromInstruction(insn, 11, 5);
 435   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 436     return MCDisassembler::Fail;
 437   // $n2
 438   MI.addOperand(MCOperand::CreateImm(0));
 439
 440   return MCDisassembler::Success;
 441 }
 442
 443 template <typename InsnType>
 444 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 445                                           uint64_t Address,
 446                                           const void *Decoder) {
 447   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 448   // (otherwise we would have matched the ADDI instruction from the earlier
 449   // ISA's instead).
 450   //
 451   // We have:
 452   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 453   //      BOVC if rs >= rt
 454   //      BEQZALC if rs == 0 && rt != 0
 455   //      BEQC if rs < rt && rs != 0
 456
 457   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 458   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 459   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 460   bool HasRs = false;
 461
 462   if (Rs >= Rt) {
 463     MI.setOpcode(Mips::BOVC);
 464     HasRs = true;
 465   } else if (Rs != 0 && Rs < Rt) {
 466     MI.setOpcode(Mips::BEQC);
 467     HasRs = true;
 468   } else
 469     MI.setOpcode(Mips::BEQZALC);
 470
 471   if (HasRs)
 472     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 473                                        Rs)));
 474
 475   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 476                                      Rt)));
 477   MI.addOperand(MCOperand::CreateImm(Imm));
 478
 479   return MCDisassembler::Success;
 480 }
 481
 482 template <typename InsnType>
 483 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 484                                            uint64_t Address,
 485                                            const void *Decoder) {
 486   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 487   // (otherwise we would have matched the ADDI instruction from the earlier
 488   // ISA's instead).
 489   //
 490   // We have:
 491   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 492   //      BNVC if rs >= rt
 493   //      BNEZALC if rs == 0 && rt != 0
 494   //      BNEC if rs < rt && rs != 0
 495
 496   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 497   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 498   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 499   bool HasRs = false;
 500
 501   if (Rs >= Rt) {
 502     MI.setOpcode(Mips::BNVC);
 503     HasRs = true;
 504   } else if (Rs != 0 && Rs < Rt) {
 505     MI.setOpcode(Mips::BNEC);
 506     HasRs = true;
 507   } else
 508     MI.setOpcode(Mips::BNEZALC);
 509
 510   if (HasRs)
 511     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 512                                        Rs)));
 513
 514   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 515                                      Rt)));
 516   MI.addOperand(MCOperand::CreateImm(Imm));
 517
 518   return MCDisassembler::Success;
 519 }
 520
 521 template <typename InsnType>
 522 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 523                                            uint64_t Address,
 524                                            const void *Decoder) {
 525   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 526   // (otherwise we would have matched the BLEZL instruction from the earlier
 527   // ISA's instead).
 528   //
 529   // We have:
 530   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 531   //      Invalid if rs == 0
 532   //      BLEZC   if rs == 0  && rt != 0
 533   //      BGEZC   if rs == rt && rt != 0
 534   //      BGEC    if rs != rt && rs != 0  && rt != 0
 535
 536   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 537   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 538   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 539   bool HasRs = false;
 540
 541   if (Rt == 0)
 542     return MCDisassembler::Fail;
 543   else if (Rs == 0)
 544     MI.setOpcode(Mips::BLEZC);
 545   else if (Rs == Rt)
 546     MI.setOpcode(Mips::BGEZC);
 547   else {
 548     HasRs = true;
 549     MI.setOpcode(Mips::BGEC);
 550   }
 551
 552   if (HasRs)
 553     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 554                                        Rs)));
 555
 556   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 557                                      Rt)));
 558
 559   MI.addOperand(MCOperand::CreateImm(Imm));
 560
 561   return MCDisassembler::Success;
 562 }
 563
 564 template <typename InsnType>
 565 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 566                                            uint64_t Address,
 567                                            const void *Decoder) {
 568   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 569   // (otherwise we would have matched the BGTZL instruction from the earlier
 570   // ISA's instead).
 571   //
 572   // We have:
 573   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 574   //      Invalid if rs == 0
 575   //      BGTZC   if rs == 0  && rt != 0
 576   //      BLTZC   if rs == rt && rt != 0
 577   //      BLTC    if rs != rt && rs != 0  && rt != 0
 578
 579   bool HasRs = false;
 580
 581   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 582   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 583   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 584
 585   if (Rt == 0)
 586     return MCDisassembler::Fail;
 587   else if (Rs == 0)
 588     MI.setOpcode(Mips::BGTZC);
 589   else if (Rs == Rt)
 590     MI.setOpcode(Mips::BLTZC);
 591   else {
 592     MI.setOpcode(Mips::BLTC);
 593     HasRs = true;
 594   }
 595
 596   if (HasRs)
 597     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 598                                               Rs)));
 599
 600   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 601                                      Rt)));
 602
 603   MI.addOperand(MCOperand::CreateImm(Imm));
 604
 605   return MCDisassembler::Success;
 606 }
 607
 608 template <typename InsnType>
 609 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 610                                           uint64_t Address,
 611                                           const void *Decoder) {
 612   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 613   // (otherwise we would have matched the BGTZ instruction from the earlier
 614   // ISA's instead).
 615   //
 616   // We have:
 617   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 618   //      BGTZ    if rt == 0
 619   //      BGTZALC if rs == 0 && rt != 0
 620   //      BLTZALC if rs != 0 && rs == rt
 621   //      BLTUC   if rs != 0 && rs != rt
 622
 623   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 624   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 625   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 626   bool HasRs = false;
 627   bool HasRt = false;
 628
 629   if (Rt == 0) {
 630     MI.setOpcode(Mips::BGTZ);
 631     HasRs = true;
 632   } else if (Rs == 0) {
 633     MI.setOpcode(Mips::BGTZALC);
 634     HasRt = true;
 635   } else if (Rs == Rt) {
 636     MI.setOpcode(Mips::BLTZALC);
 637     HasRs = true;
 638   } else {
 639     MI.setOpcode(Mips::BLTUC);
 640     HasRs = true;
 641     HasRt = true;
 642   }
 643
 644   if (HasRs)
 645     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 646                                        Rs)));
 647
 648   if (HasRt)
 649     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 650                                        Rt)));
 651
 652   MI.addOperand(MCOperand::CreateImm(Imm));
 653
 654   return MCDisassembler::Success;
 655 }
 656
 657 template <typename InsnType>
 658 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 659                                            uint64_t Address,
 660                                            const void *Decoder) {
 661   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 662   // (otherwise we would have matched the BLEZL instruction from the earlier
 663   // ISA's instead).
 664   //
 665   // We have:
 666   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 667   //      Invalid   if rs == 0
 668   //      BLEZALC   if rs == 0  && rt != 0
 669   //      BGEZALC   if rs == rt && rt != 0
 670   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 671
 672   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 673   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 674   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 675   bool HasRs = false;
 676
 677   if (Rt == 0)
 678     return MCDisassembler::Fail;
 679   else if (Rs == 0)
 680     MI.setOpcode(Mips::BLEZALC);
 681   else if (Rs == Rt)
 682     MI.setOpcode(Mips::BGEZALC);
 683   else {
 684     HasRs = true;
 685     MI.setOpcode(Mips::BGEUC);
 686   }
 687
 688   if (HasRs)
 689     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 690                                        Rs)));
 691   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 692                                      Rt)));
 693
 694   MI.addOperand(MCOperand::CreateImm(Imm));
 695
 696   return MCDisassembler::Success;
 697 }
 698
 699 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 700 /// according to the given endianess
 701 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 702                                       uint64_t &Size, uint32_t &Insn,
 703                                       bool IsBigEndian, bool IsMicroMips) {
 704   // We want to read exactly 4 Bytes of data.
 705   if (Bytes.size() < 4) {
 706     Size = 0;
 707     return MCDisassembler::Fail;
 708   }
 709
 710   if (IsBigEndian) {
 711     // Encoded as a big-endian 32-bit word in the stream.
 712     Insn =
 713         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 714   } else {
 715     // Encoded as a small-endian 32-bit word in the stream.
 716     // Little-endian byte ordering:
 717     //   mips32r2:   4 | 3 | 2 | 1
 718     //   microMIPS:  2 | 1 | 4 | 3
 719     if (IsMicroMips) {
 720       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 721              (Bytes[1] << 24);
 722     } else {
 723       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 724              (Bytes[3] << 24);
 725     }
 726   }
 727
 728   return MCDisassembler::Success;
 729 }
 730
 731 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 732                                               ArrayRef<uint8_t> Bytes,
 733                                               uint64_t Address,
 734                                               raw_ostream &VStream,
 735                                               raw_ostream &CStream) const {
 736   uint32_t Insn;
 737
 738   DecodeStatus Result =
 739       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips);
 740   if (Result == MCDisassembler::Fail)
 741     return MCDisassembler::Fail;
 742
 743   if (IsMicroMips) {
 744     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 745     // Calling the auto-generated decoder function.
 746     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 747                                this, STI);
 748     if (Result != MCDisassembler::Fail) {
 749       Size = 4;
 750       return Result;
 751     }
 752     return MCDisassembler::Fail;
 753   }
 754
 755   if (hasCOP3()) {
 756     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 757     Result =
 758         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 759     if (Result != MCDisassembler::Fail) {
 760       Size = 4;
 761       return Result;
 762     }
 763   }
 764
 765   if (hasMips32r6() && isGP64()) {
 766     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 767     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 768                                Address, this, STI);
 769     if (Result != MCDisassembler::Fail) {
 770       Size = 4;
 771       return Result;
 772     }
 773   }
 774
 775   if (hasMips32r6()) {
 776     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 777     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 778                                Address, this, STI);
 779     if (Result != MCDisassembler::Fail) {
 780       Size = 4;
 781       return Result;
 782     }
 783   }
 784
 785   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 786   // Calling the auto-generated decoder function.
 787   Result =
 788       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 789   if (Result != MCDisassembler::Fail) {
 790     Size = 4;
 791     return Result;
 792   }
 793
 794   return MCDisassembler::Fail;
 795 }
 796
 797 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 798                                                 ArrayRef<uint8_t> Bytes,
 799                                                 uint64_t Address,
 800                                                 raw_ostream &VStream,
 801                                                 raw_ostream &CStream) const {
 802   uint32_t Insn;
 803
 804   DecodeStatus Result =
 805       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 806   if (Result == MCDisassembler::Fail)
 807     return MCDisassembler::Fail;
 808
 809   // Calling the auto-generated decoder function.
 810   Result =
 811       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 812   if (Result != MCDisassembler::Fail) {
 813     Size = 4;
 814     return Result;
 815   }
 816   // If we fail to decode in Mips64 decoder space we can try in Mips32
 817   Result =
 818       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 819   if (Result != MCDisassembler::Fail) {
 820     Size = 4;
 821     return Result;
 822   }
 823
 824   return MCDisassembler::Fail;
 825 }
 826
 827 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 828                                                  unsigned RegNo,
 829                                                  uint64_t Address,
 830                                                  const void *Decoder) {
 831
 832   return MCDisassembler::Fail;
 833
 834 }
 835
 836 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 837                                              unsigned RegNo,
 838                                              uint64_t Address,
 839                                              const void *Decoder) {
 840
 841   if (RegNo > 31)
 842     return MCDisassembler::Fail;
 843
 844   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 845   Inst.addOperand(MCOperand::CreateReg(Reg));
 846   return MCDisassembler::Success;
 847 }
 848
 849 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 850                                                unsigned RegNo,
 851                                                uint64_t Address,
 852                                                const void *Decoder) {
 853   return MCDisassembler::Fail;
 854 }
 855
 856 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 857                                              unsigned RegNo,
 858                                              uint64_t Address,
 859                                              const void *Decoder) {
 860   if (RegNo > 31)
 861     return MCDisassembler::Fail;
 862   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 863   Inst.addOperand(MCOperand::CreateReg(Reg));
 864   return MCDisassembler::Success;
 865 }
 866
 867 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 868                                            unsigned RegNo,
 869                                            uint64_t Address,
 870                                            const void *Decoder) {
 871   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 872     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 873
 874   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 875 }
 876
 877 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 878                                             unsigned RegNo,
 879                                             uint64_t Address,
 880                                             const void *Decoder) {
 881   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 882 }
 883
 884 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 885                                              unsigned RegNo,
 886                                              uint64_t Address,
 887                                              const void *Decoder) {
 888   if (RegNo > 31)
 889     return MCDisassembler::Fail;
 890
 891   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 892   Inst.addOperand(MCOperand::CreateReg(Reg));
 893   return MCDisassembler::Success;
 894 }
 895
 896 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 897                                              unsigned RegNo,
 898                                              uint64_t Address,
 899                                              const void *Decoder) {
 900   if (RegNo > 31)
 901     return MCDisassembler::Fail;
 902
 903   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 904   Inst.addOperand(MCOperand::CreateReg(Reg));
 905   return MCDisassembler::Success;
 906 }
 907
 908 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 909                                            unsigned RegNo,
 910                                            uint64_t Address,
 911                                            const void *Decoder) {
 912   if (RegNo > 31)
 913     return MCDisassembler::Fail;
 914   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 915   Inst.addOperand(MCOperand::CreateReg(Reg));
 916   return MCDisassembler::Success;
 917 }
 918
 919 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 920                                            unsigned RegNo,
 921                                            uint64_t Address,
 922                                            const void *Decoder) {
 923   if (RegNo > 7)
 924     return MCDisassembler::Fail;
 925   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 926   Inst.addOperand(MCOperand::CreateReg(Reg));
 927   return MCDisassembler::Success;
 928 }
 929
 930 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 931                                              uint64_t Address,
 932                                              const void *Decoder) {
 933   if (RegNo > 31)
 934     return MCDisassembler::Fail;
 935
 936   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 937   Inst.addOperand(MCOperand::CreateReg(Reg));
 938   return MCDisassembler::Success;
 939 }
 940
 941 static DecodeStatus DecodeMem(MCInst &Inst,
 942                               unsigned Insn,
 943                               uint64_t Address,
 944                               const void *Decoder) {
 945   int Offset = SignExtend32<16>(Insn & 0xffff);
 946   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 947   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 948
 949   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 950   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 951
 952   if(Inst.getOpcode() == Mips::SC){
 953     Inst.addOperand(MCOperand::CreateReg(Reg));
 954   }
 955
 956   Inst.addOperand(MCOperand::CreateReg(Reg));
 957   Inst.addOperand(MCOperand::CreateReg(Base));
 958   Inst.addOperand(MCOperand::CreateImm(Offset));
 959
 960   return MCDisassembler::Success;
 961 }
 962
 963 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 964                               unsigned Insn,
 965                               uint64_t Address,
 966                               const void *Decoder) {
 967   int Offset = SignExtend32<16>(Insn & 0xffff);
 968   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
 969   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 970
 971   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 972
 973   Inst.addOperand(MCOperand::CreateReg(Base));
 974   Inst.addOperand(MCOperand::CreateImm(Offset));
 975   Inst.addOperand(MCOperand::CreateImm(Hint));
 976
 977   return MCDisassembler::Success;
 978 }
 979
 980 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 981                                     uint64_t Address, const void *Decoder) {
 982   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 983   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 984   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 985
 986   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 987   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 988
 989   Inst.addOperand(MCOperand::CreateReg(Reg));
 990   Inst.addOperand(MCOperand::CreateReg(Base));
 991
 992   // The immediate field of an LD/ST instruction is scaled which means it must
 993   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 994   // data format.
 995   // .b - 1 byte
 996   // .h - 2 bytes
 997   // .w - 4 bytes
 998   // .d - 8 bytes
 999   switch(Inst.getOpcode())
1000   {
1001   default:
1002     assert (0 && "Unexpected instruction");
1003     return MCDisassembler::Fail;
1004     break;
1005   case Mips::LD_B:
1006   case Mips::ST_B:
1007     Inst.addOperand(MCOperand::CreateImm(Offset));
1008     break;
1009   case Mips::LD_H:
1010   case Mips::ST_H:
1011     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1012     break;
1013   case Mips::LD_W:
1014   case Mips::ST_W:
1015     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1016     break;
1017   case Mips::LD_D:
1018   case Mips::ST_D:
1019     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1020     break;
1021   }
1022
1023   return MCDisassembler::Success;
1024 }
1025
1026 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1027                                      unsigned Insn,
1028                                      uint64_t Address,
1029                                      const void *Decoder) {
1030   int Offset = SignExtend32<12>(Insn & 0x0fff);
1031   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1032   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1033
1034   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1035   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1036
1037   if (Inst.getOpcode() == Mips::SC_MM)
1038     Inst.addOperand(MCOperand::CreateReg(Reg));
1039
1040   Inst.addOperand(MCOperand::CreateReg(Reg));
1041   Inst.addOperand(MCOperand::CreateReg(Base));
1042   Inst.addOperand(MCOperand::CreateImm(Offset));
1043
1044   return MCDisassembler::Success;
1045 }
1046
1047 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1048                                      unsigned Insn,
1049                                      uint64_t Address,
1050                                      const void *Decoder) {
1051   int Offset = SignExtend32<16>(Insn & 0xffff);
1052   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1053   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1054
1055   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1056   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1057
1058   Inst.addOperand(MCOperand::CreateReg(Reg));
1059   Inst.addOperand(MCOperand::CreateReg(Base));
1060   Inst.addOperand(MCOperand::CreateImm(Offset));
1061
1062   return MCDisassembler::Success;
1063 }
1064
1065 static DecodeStatus DecodeFMem(MCInst &Inst,
1066                                unsigned Insn,
1067                                uint64_t Address,
1068                                const void *Decoder) {
1069   int Offset = SignExtend32<16>(Insn & 0xffff);
1070   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1071   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1072
1073   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1074   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1075
1076   Inst.addOperand(MCOperand::CreateReg(Reg));
1077   Inst.addOperand(MCOperand::CreateReg(Base));
1078   Inst.addOperand(MCOperand::CreateImm(Offset));
1079
1080   return MCDisassembler::Success;
1081 }
1082
1083 static DecodeStatus DecodeFMem2(MCInst &Inst,
1084                                unsigned Insn,
1085                                uint64_t Address,
1086                                const void *Decoder) {
1087   int Offset = SignExtend32<16>(Insn & 0xffff);
1088   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1089   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1090
1091   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1092   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1093
1094   Inst.addOperand(MCOperand::CreateReg(Reg));
1095   Inst.addOperand(MCOperand::CreateReg(Base));
1096   Inst.addOperand(MCOperand::CreateImm(Offset));
1097
1098   return MCDisassembler::Success;
1099 }
1100
1101 static DecodeStatus DecodeFMem3(MCInst &Inst,
1102                                unsigned Insn,
1103                                uint64_t Address,
1104                                const void *Decoder) {
1105   int Offset = SignExtend32<16>(Insn & 0xffff);
1106   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1107   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1108
1109   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1110   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1111
1112   Inst.addOperand(MCOperand::CreateReg(Reg));
1113   Inst.addOperand(MCOperand::CreateReg(Base));
1114   Inst.addOperand(MCOperand::CreateImm(Offset));
1115
1116   return MCDisassembler::Success;
1117 }
1118
1119 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1120                                        unsigned Insn,
1121                                        uint64_t Address,
1122                                        const void *Decoder) {
1123   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1124   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1125   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1126
1127   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1128   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1129
1130   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1131     Inst.addOperand(MCOperand::CreateReg(Rt));
1132   }
1133
1134   Inst.addOperand(MCOperand::CreateReg(Rt));
1135   Inst.addOperand(MCOperand::CreateReg(Base));
1136   Inst.addOperand(MCOperand::CreateImm(Offset));
1137
1138   return MCDisassembler::Success;
1139 }
1140
1141 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1142                                               unsigned RegNo,
1143                                               uint64_t Address,
1144                                               const void *Decoder) {
1145   // Currently only hardware register 29 is supported.
1146   if (RegNo != 29)
1147     return  MCDisassembler::Fail;
1148   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1149   return MCDisassembler::Success;
1150 }
1151
1152 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1153                                               unsigned RegNo,
1154                                               uint64_t Address,
1155                                               const void *Decoder) {
1156   if (RegNo > 30 || RegNo %2)
1157     return MCDisassembler::Fail;
1158
1159   ;
1160   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1161   Inst.addOperand(MCOperand::CreateReg(Reg));
1162   return MCDisassembler::Success;
1163 }
1164
1165 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1166                                                 unsigned RegNo,
1167                                                 uint64_t Address,
1168                                                 const void *Decoder) {
1169   if (RegNo >= 4)
1170     return MCDisassembler::Fail;
1171
1172   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1173   Inst.addOperand(MCOperand::CreateReg(Reg));
1174   return MCDisassembler::Success;
1175 }
1176
1177 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1178                                                unsigned RegNo,
1179                                                uint64_t Address,
1180                                                const void *Decoder) {
1181   if (RegNo >= 4)
1182     return MCDisassembler::Fail;
1183
1184   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1185   Inst.addOperand(MCOperand::CreateReg(Reg));
1186   return MCDisassembler::Success;
1187 }
1188
1189 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1190                                                unsigned RegNo,
1191                                                uint64_t Address,
1192                                                const void *Decoder) {
1193   if (RegNo >= 4)
1194     return MCDisassembler::Fail;
1195
1196   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1197   Inst.addOperand(MCOperand::CreateReg(Reg));
1198   return MCDisassembler::Success;
1199 }
1200
1201 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1202                                                unsigned RegNo,
1203                                                uint64_t Address,
1204                                                const void *Decoder) {
1205   if (RegNo > 31)
1206     return MCDisassembler::Fail;
1207
1208   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1209   Inst.addOperand(MCOperand::CreateReg(Reg));
1210   return MCDisassembler::Success;
1211 }
1212
1213 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1214                                                unsigned RegNo,
1215                                                uint64_t Address,
1216                                                const void *Decoder) {
1217   if (RegNo > 31)
1218     return MCDisassembler::Fail;
1219
1220   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1221   Inst.addOperand(MCOperand::CreateReg(Reg));
1222   return MCDisassembler::Success;
1223 }
1224
1225 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1226                                                unsigned RegNo,
1227                                                uint64_t Address,
1228                                                const void *Decoder) {
1229   if (RegNo > 31)
1230     return MCDisassembler::Fail;
1231
1232   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1233   Inst.addOperand(MCOperand::CreateReg(Reg));
1234   return MCDisassembler::Success;
1235 }
1236
1237 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1238                                                unsigned RegNo,
1239                                                uint64_t Address,
1240                                                const void *Decoder) {
1241   if (RegNo > 31)
1242     return MCDisassembler::Fail;
1243
1244   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1245   Inst.addOperand(MCOperand::CreateReg(Reg));
1246   return MCDisassembler::Success;
1247 }
1248
1249 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1250                                                unsigned RegNo,
1251                                                uint64_t Address,
1252                                                const void *Decoder) {
1253   if (RegNo > 7)
1254     return MCDisassembler::Fail;
1255
1256   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1257   Inst.addOperand(MCOperand::CreateReg(Reg));
1258   return MCDisassembler::Success;
1259 }
1260
1261 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1262                                             unsigned RegNo,
1263                                             uint64_t Address,
1264                                             const void *Decoder) {
1265   if (RegNo > 31)
1266     return MCDisassembler::Fail;
1267
1268   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1269   Inst.addOperand(MCOperand::CreateReg(Reg));
1270   return MCDisassembler::Success;
1271 }
1272
1273 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1274                                        unsigned Offset,
1275                                        uint64_t Address,
1276                                        const void *Decoder) {
1277   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1278   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1279   return MCDisassembler::Success;
1280 }
1281
1282 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1283                                      unsigned Insn,
1284                                      uint64_t Address,
1285                                      const void *Decoder) {
1286
1287   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1288   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1289   return MCDisassembler::Success;
1290 }
1291
1292 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1293                                          unsigned Offset,
1294                                          uint64_t Address,
1295                                          const void *Decoder) {
1296   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1297
1298   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1299   return MCDisassembler::Success;
1300 }
1301
1302 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1303                                          unsigned Offset,
1304                                          uint64_t Address,
1305                                          const void *Decoder) {
1306   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1307
1308   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1309   return MCDisassembler::Success;
1310 }
1311
1312 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1313                                          unsigned Offset,
1314                                          uint64_t Address,
1315                                          const void *Decoder) {
1316   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1317   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1318   return MCDisassembler::Success;
1319 }
1320
1321 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1322                                        unsigned Insn,
1323                                        uint64_t Address,
1324                                        const void *Decoder) {
1325   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1326   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1327   return MCDisassembler::Success;
1328 }
1329
1330 static DecodeStatus DecodeSimm16(MCInst &Inst,
1331                                  unsigned Insn,
1332                                  uint64_t Address,
1333                                  const void *Decoder) {
1334   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1335   return MCDisassembler::Success;
1336 }
1337
1338 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1339                                  unsigned Insn,
1340                                  uint64_t Address,
1341                                  const void *Decoder) {
1342   // We add one to the immediate field as it was encoded as 'imm - 1'.
1343   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1344   return MCDisassembler::Success;
1345 }
1346
1347 static DecodeStatus DecodeInsSize(MCInst &Inst,
1348                                   unsigned Insn,
1349                                   uint64_t Address,
1350                                   const void *Decoder) {
1351   // First we need to grab the pos(lsb) from MCInst.
1352   int Pos = Inst.getOperand(2).getImm();
1353   int Size = (int) Insn - Pos + 1;
1354   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1355   return MCDisassembler::Success;
1356 }
1357
1358 static DecodeStatus DecodeExtSize(MCInst &Inst,
1359                                   unsigned Insn,
1360                                   uint64_t Address,
1361                                   const void *Decoder) {
1362   int Size = (int) Insn  + 1;
1363   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1364   return MCDisassembler::Success;
1365 }
1366
1367 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1368                                      uint64_t Address, const void *Decoder) {
1369   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1370   return MCDisassembler::Success;
1371 }
1372
1373 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1374                                      uint64_t Address, const void *Decoder) {
1375   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1376   return MCDisassembler::Success;
1377 }