1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the Mips Disassembler.
12 //===----------------------------------------------------------------------===//
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
28 #define DEBUG_TYPE "mips-disassembler"
30 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// MipsDisassemblerBase - a disasembler class for Mips.
35 class MipsDisassemblerBase : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
41 MCDisassembler(STI, Ctx),
42 IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
44 virtual ~MipsDisassemblerBase() {}
46 bool isN64() const { return IsN64; }
54 /// MipsDisassembler - a disasembler class for Mips32.
55 class MipsDisassembler : public MipsDisassemblerBase {
58 /// Constructor - Initializes the disassembler.
60 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
61 : MipsDisassemblerBase(STI, Ctx, bigEndian) {
62 IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
65 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
66 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
67 bool hasMips32r6() const {
68 return STI.getFeatureBits() & Mips::FeatureMips32r6;
71 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
73 bool hasCOP3() const {
74 // Only present in MIPS-I and MIPS-II
75 return !hasMips32() && !hasMips3();
78 /// getInstruction - See MCDisassembler.
79 DecodeStatus getInstruction(MCInst &instr,
81 const MemoryObject ®ion,
84 raw_ostream &cStream) const override;
88 /// Mips64Disassembler - a disasembler class for Mips64.
89 class Mips64Disassembler : public MipsDisassemblerBase {
91 /// Constructor - Initializes the disassembler.
93 Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
95 MipsDisassemblerBase(STI, Ctx, bigEndian) {}
97 /// getInstruction - See MCDisassembler.
98 DecodeStatus getInstruction(MCInst &instr,
100 const MemoryObject ®ion,
102 raw_ostream &vStream,
103 raw_ostream &cStream) const override;
106 } // end anonymous namespace
108 // Forward declare these because the autogenerated code will reference them.
109 // Definitions are further down.
110 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
113 const void *Decoder);
115 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
118 const void *Decoder);
120 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
123 const void *Decoder);
125 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
128 const void *Decoder);
130 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
133 const void *Decoder);
135 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
138 const void *Decoder);
140 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
143 const void *Decoder);
145 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
148 const void *Decoder);
150 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
153 const void *Decoder);
155 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
157 const void *Decoder);
159 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
162 const void *Decoder);
164 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
167 const void *Decoder);
169 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
172 const void *Decoder);
174 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
177 const void *Decoder);
179 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
182 const void *Decoder);
184 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
187 const void *Decoder);
189 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
192 const void *Decoder);
194 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
197 const void *Decoder);
199 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
202 const void *Decoder);
204 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
207 const void *Decoder);
209 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
212 const void *Decoder);
214 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
217 const void *Decoder);
219 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
222 const void *Decoder);
224 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
227 const void *Decoder);
229 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
232 const void *Decoder);
234 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
235 // shifted left by 1 bit.
236 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
239 const void *Decoder);
241 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
242 // shifted left by 1 bit.
243 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
246 const void *Decoder);
248 static DecodeStatus DecodeMem(MCInst &Inst,
251 const void *Decoder);
253 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
254 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
259 const void *Decoder);
261 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
264 const void *Decoder);
266 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
268 const void *Decoder);
270 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
273 const void *Decoder);
275 static DecodeStatus DecodeSimm16(MCInst &Inst,
278 const void *Decoder);
280 // Decode the immediate field of an LSA instruction which
282 static DecodeStatus DecodeLSAImm(MCInst &Inst,
285 const void *Decoder);
287 static DecodeStatus DecodeInsSize(MCInst &Inst,
290 const void *Decoder);
292 static DecodeStatus DecodeExtSize(MCInst &Inst,
295 const void *Decoder);
297 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
303 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
305 template <typename InsnType>
306 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
307 const void *Decoder);
309 template <typename InsnType>
311 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
312 const void *Decoder);
314 template <typename InsnType>
316 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
317 const void *Decoder);
319 template <typename InsnType>
321 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
322 const void *Decoder);
324 template <typename InsnType>
326 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
327 const void *Decoder);
329 template <typename InsnType>
331 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
332 const void *Decoder);
334 template <typename InsnType>
336 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
337 const void *Decoder);
340 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
344 static MCDisassembler *createMipsDisassembler(
346 const MCSubtargetInfo &STI,
348 return new MipsDisassembler(STI, Ctx, true);
351 static MCDisassembler *createMipselDisassembler(
353 const MCSubtargetInfo &STI,
355 return new MipsDisassembler(STI, Ctx, false);
358 static MCDisassembler *createMips64Disassembler(
360 const MCSubtargetInfo &STI,
362 return new Mips64Disassembler(STI, Ctx, true);
365 static MCDisassembler *createMips64elDisassembler(
367 const MCSubtargetInfo &STI,
369 return new Mips64Disassembler(STI, Ctx, false);
372 extern "C" void LLVMInitializeMipsDisassembler() {
373 // Register the disassembler.
374 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
375 createMipsDisassembler);
376 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
377 createMipselDisassembler);
378 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
379 createMips64Disassembler);
380 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
381 createMips64elDisassembler);
384 #include "MipsGenDisassemblerTables.inc"
386 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
387 const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
388 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
389 return *(RegInfo->getRegClass(RC).begin() + RegNo);
392 template <typename InsnType>
393 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
394 const void *Decoder) {
395 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
396 // The size of the n field depends on the element size
397 // The register class also depends on this.
398 InsnType tmp = fieldFromInstruction(insn, 17, 5);
400 DecodeFN RegDecoder = nullptr;
401 if ((tmp & 0x18) == 0x00) { // INSVE_B
403 RegDecoder = DecodeMSA128BRegisterClass;
404 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
406 RegDecoder = DecodeMSA128HRegisterClass;
407 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
409 RegDecoder = DecodeMSA128WRegisterClass;
410 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
412 RegDecoder = DecodeMSA128DRegisterClass;
414 llvm_unreachable("Invalid encoding");
416 assert(NSize != 0 && RegDecoder != nullptr);
419 tmp = fieldFromInstruction(insn, 6, 5);
420 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
421 return MCDisassembler::Fail;
423 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
424 return MCDisassembler::Fail;
426 tmp = fieldFromInstruction(insn, 16, NSize);
427 MI.addOperand(MCOperand::CreateImm(tmp));
429 tmp = fieldFromInstruction(insn, 11, 5);
430 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
431 return MCDisassembler::Fail;
433 MI.addOperand(MCOperand::CreateImm(0));
435 return MCDisassembler::Success;
438 template <typename InsnType>
439 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
441 const void *Decoder) {
442 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
443 // (otherwise we would have matched the ADDI instruction from the earlier
447 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
449 // BEQZALC if rs == 0 && rt != 0
450 // BEQC if rs < rt && rs != 0
452 InsnType Rs = fieldFromInstruction(insn, 21, 5);
453 InsnType Rt = fieldFromInstruction(insn, 16, 5);
454 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
458 MI.setOpcode(Mips::BOVC);
460 } else if (Rs != 0 && Rs < Rt) {
461 MI.setOpcode(Mips::BEQC);
464 MI.setOpcode(Mips::BEQZALC);
467 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
470 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
472 MI.addOperand(MCOperand::CreateImm(Imm));
474 return MCDisassembler::Success;
477 template <typename InsnType>
478 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
480 const void *Decoder) {
481 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
482 // (otherwise we would have matched the ADDI instruction from the earlier
486 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
488 // BNEZALC if rs == 0 && rt != 0
489 // BNEC if rs < rt && rs != 0
491 InsnType Rs = fieldFromInstruction(insn, 21, 5);
492 InsnType Rt = fieldFromInstruction(insn, 16, 5);
493 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
497 MI.setOpcode(Mips::BNVC);
499 } else if (Rs != 0 && Rs < Rt) {
500 MI.setOpcode(Mips::BNEC);
503 MI.setOpcode(Mips::BNEZALC);
506 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
509 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
511 MI.addOperand(MCOperand::CreateImm(Imm));
513 return MCDisassembler::Success;
516 template <typename InsnType>
517 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
519 const void *Decoder) {
520 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
521 // (otherwise we would have matched the BLEZL instruction from the earlier
525 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
526 // Invalid if rs == 0
527 // BLEZC if rs == 0 && rt != 0
528 // BGEZC if rs == rt && rt != 0
529 // BGEC if rs != rt && rs != 0 && rt != 0
531 InsnType Rs = fieldFromInstruction(insn, 21, 5);
532 InsnType Rt = fieldFromInstruction(insn, 16, 5);
533 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
537 return MCDisassembler::Fail;
539 MI.setOpcode(Mips::BLEZC);
541 MI.setOpcode(Mips::BGEZC);
544 MI.setOpcode(Mips::BGEC);
548 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
551 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
554 MI.addOperand(MCOperand::CreateImm(Imm));
556 return MCDisassembler::Success;
559 template <typename InsnType>
560 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
562 const void *Decoder) {
563 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
564 // (otherwise we would have matched the BGTZL instruction from the earlier
568 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
569 // Invalid if rs == 0
570 // BGTZC if rs == 0 && rt != 0
571 // BLTZC if rs == rt && rt != 0
572 // BLTC if rs != rt && rs != 0 && rt != 0
576 InsnType Rs = fieldFromInstruction(insn, 21, 5);
577 InsnType Rt = fieldFromInstruction(insn, 16, 5);
578 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
581 return MCDisassembler::Fail;
583 MI.setOpcode(Mips::BGTZC);
585 MI.setOpcode(Mips::BLTZC);
587 MI.setOpcode(Mips::BLTC);
592 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
595 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
598 MI.addOperand(MCOperand::CreateImm(Imm));
600 return MCDisassembler::Success;
603 template <typename InsnType>
604 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
606 const void *Decoder) {
607 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
608 // (otherwise we would have matched the BGTZ instruction from the earlier
612 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
614 // BGTZALC if rs == 0 && rt != 0
615 // BLTZALC if rs != 0 && rs == rt
616 // BLTUC if rs != 0 && rs != rt
618 InsnType Rs = fieldFromInstruction(insn, 21, 5);
619 InsnType Rt = fieldFromInstruction(insn, 16, 5);
620 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
625 MI.setOpcode(Mips::BGTZ);
627 } else if (Rs == 0) {
628 MI.setOpcode(Mips::BGTZALC);
630 } else if (Rs == Rt) {
631 MI.setOpcode(Mips::BLTZALC);
634 MI.setOpcode(Mips::BLTUC);
640 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
644 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
647 MI.addOperand(MCOperand::CreateImm(Imm));
649 return MCDisassembler::Success;
652 template <typename InsnType>
653 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
655 const void *Decoder) {
656 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
657 // (otherwise we would have matched the BLEZL instruction from the earlier
661 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
662 // Invalid if rs == 0
663 // BLEZALC if rs == 0 && rt != 0
664 // BGEZALC if rs == rt && rt != 0
665 // BGEUC if rs != rt && rs != 0 && rt != 0
667 InsnType Rs = fieldFromInstruction(insn, 21, 5);
668 InsnType Rt = fieldFromInstruction(insn, 16, 5);
669 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
673 return MCDisassembler::Fail;
675 MI.setOpcode(Mips::BLEZALC);
677 MI.setOpcode(Mips::BGEZALC);
680 MI.setOpcode(Mips::BGEUC);
684 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
686 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
689 MI.addOperand(MCOperand::CreateImm(Imm));
691 return MCDisassembler::Success;
694 /// readInstruction - read four bytes from the MemoryObject
695 /// and return 32 bit word sorted according to the given endianess
696 static DecodeStatus readInstruction32(const MemoryObject ®ion,
704 // We want to read exactly 4 Bytes of data.
705 if (region.readBytes(address, 4, Bytes) == -1) {
707 return MCDisassembler::Fail;
711 // Encoded as a big-endian 32-bit word in the stream.
712 insn = (Bytes[3] << 0) |
718 // Encoded as a small-endian 32-bit word in the stream.
719 // Little-endian byte ordering:
720 // mips32r2: 4 | 3 | 2 | 1
721 // microMIPS: 2 | 1 | 4 | 3
723 insn = (Bytes[2] << 0) |
728 insn = (Bytes[0] << 0) |
735 return MCDisassembler::Success;
739 MipsDisassembler::getInstruction(MCInst &instr,
741 const MemoryObject &Region,
743 raw_ostream &vStream,
744 raw_ostream &cStream) const {
747 DecodeStatus Result = readInstruction32(Region, Address, Size,
748 Insn, isBigEndian, IsMicroMips);
749 if (Result == MCDisassembler::Fail)
750 return MCDisassembler::Fail;
753 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
754 // Calling the auto-generated decoder function.
755 Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
757 if (Result != MCDisassembler::Fail) {
761 return MCDisassembler::Fail;
765 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
767 decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
774 if (hasMips32r6() && isGP64()) {
775 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
776 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
778 if (Result != MCDisassembler::Fail) {
785 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
786 Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
788 if (Result != MCDisassembler::Fail) {
794 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
795 // Calling the auto-generated decoder function.
796 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
798 if (Result != MCDisassembler::Fail) {
803 return MCDisassembler::Fail;
807 Mips64Disassembler::getInstruction(MCInst &instr,
809 const MemoryObject &Region,
811 raw_ostream &vStream,
812 raw_ostream &cStream) const {
815 DecodeStatus Result = readInstruction32(Region, Address, Size,
816 Insn, isBigEndian, false);
817 if (Result == MCDisassembler::Fail)
818 return MCDisassembler::Fail;
820 // Calling the auto-generated decoder function.
821 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
823 if (Result != MCDisassembler::Fail) {
827 // If we fail to decode in Mips64 decoder space we can try in Mips32
828 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
830 if (Result != MCDisassembler::Fail) {
835 return MCDisassembler::Fail;
838 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
841 const void *Decoder) {
843 return MCDisassembler::Fail;
847 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
850 const void *Decoder) {
853 return MCDisassembler::Fail;
855 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
856 Inst.addOperand(MCOperand::CreateReg(Reg));
857 return MCDisassembler::Success;
860 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
863 const void *Decoder) {
865 return MCDisassembler::Fail;
866 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
867 Inst.addOperand(MCOperand::CreateReg(Reg));
868 return MCDisassembler::Success;
871 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
874 const void *Decoder) {
875 if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
876 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
878 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
881 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
884 const void *Decoder) {
885 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
888 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
891 const void *Decoder) {
893 return MCDisassembler::Fail;
895 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
896 Inst.addOperand(MCOperand::CreateReg(Reg));
897 return MCDisassembler::Success;
900 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
903 const void *Decoder) {
905 return MCDisassembler::Fail;
907 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
908 Inst.addOperand(MCOperand::CreateReg(Reg));
909 return MCDisassembler::Success;
912 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
915 const void *Decoder) {
917 return MCDisassembler::Fail;
918 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
919 Inst.addOperand(MCOperand::CreateReg(Reg));
920 return MCDisassembler::Success;
923 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
926 const void *Decoder) {
928 return MCDisassembler::Fail;
929 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
930 Inst.addOperand(MCOperand::CreateReg(Reg));
931 return MCDisassembler::Success;
934 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
936 const void *Decoder) {
938 return MCDisassembler::Fail;
940 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
941 Inst.addOperand(MCOperand::CreateReg(Reg));
942 return MCDisassembler::Success;
945 static DecodeStatus DecodeMem(MCInst &Inst,
948 const void *Decoder) {
949 int Offset = SignExtend32<16>(Insn & 0xffff);
950 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
951 unsigned Base = fieldFromInstruction(Insn, 21, 5);
953 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
954 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
956 if(Inst.getOpcode() == Mips::SC){
957 Inst.addOperand(MCOperand::CreateReg(Reg));
960 Inst.addOperand(MCOperand::CreateReg(Reg));
961 Inst.addOperand(MCOperand::CreateReg(Base));
962 Inst.addOperand(MCOperand::CreateImm(Offset));
964 return MCDisassembler::Success;
967 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
968 uint64_t Address, const void *Decoder) {
969 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
970 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
971 unsigned Base = fieldFromInstruction(Insn, 11, 5);
973 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
974 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
976 Inst.addOperand(MCOperand::CreateReg(Reg));
977 Inst.addOperand(MCOperand::CreateReg(Base));
979 // The immediate field of an LD/ST instruction is scaled which means it must
980 // be multiplied (when decoding) by the size (in bytes) of the instructions'
986 switch(Inst.getOpcode())
989 assert (0 && "Unexpected instruction");
990 return MCDisassembler::Fail;
994 Inst.addOperand(MCOperand::CreateImm(Offset));
998 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1002 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1006 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1010 return MCDisassembler::Success;
1013 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1016 const void *Decoder) {
1017 int Offset = SignExtend32<12>(Insn & 0x0fff);
1018 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1019 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1021 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1022 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1024 if (Inst.getOpcode() == Mips::SC_MM)
1025 Inst.addOperand(MCOperand::CreateReg(Reg));
1027 Inst.addOperand(MCOperand::CreateReg(Reg));
1028 Inst.addOperand(MCOperand::CreateReg(Base));
1029 Inst.addOperand(MCOperand::CreateImm(Offset));
1031 return MCDisassembler::Success;
1034 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1037 const void *Decoder) {
1038 int Offset = SignExtend32<16>(Insn & 0xffff);
1039 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1040 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1042 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1043 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1045 Inst.addOperand(MCOperand::CreateReg(Reg));
1046 Inst.addOperand(MCOperand::CreateReg(Base));
1047 Inst.addOperand(MCOperand::CreateImm(Offset));
1049 return MCDisassembler::Success;
1052 static DecodeStatus DecodeFMem(MCInst &Inst,
1055 const void *Decoder) {
1056 int Offset = SignExtend32<16>(Insn & 0xffff);
1057 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1058 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1060 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1061 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1063 Inst.addOperand(MCOperand::CreateReg(Reg));
1064 Inst.addOperand(MCOperand::CreateReg(Base));
1065 Inst.addOperand(MCOperand::CreateImm(Offset));
1067 return MCDisassembler::Success;
1070 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1073 const void *Decoder) {
1074 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1075 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1076 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1078 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1079 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1081 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1082 Inst.addOperand(MCOperand::CreateReg(Rt));
1085 Inst.addOperand(MCOperand::CreateReg(Rt));
1086 Inst.addOperand(MCOperand::CreateReg(Base));
1087 Inst.addOperand(MCOperand::CreateImm(Offset));
1089 return MCDisassembler::Success;
1092 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1095 const void *Decoder) {
1096 // Currently only hardware register 29 is supported.
1098 return MCDisassembler::Fail;
1099 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1100 return MCDisassembler::Success;
1103 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1106 const void *Decoder) {
1107 if (RegNo > 30 || RegNo %2)
1108 return MCDisassembler::Fail;
1111 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1112 Inst.addOperand(MCOperand::CreateReg(Reg));
1113 return MCDisassembler::Success;
1116 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1119 const void *Decoder) {
1121 return MCDisassembler::Fail;
1123 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1124 Inst.addOperand(MCOperand::CreateReg(Reg));
1125 return MCDisassembler::Success;
1128 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1131 const void *Decoder) {
1133 return MCDisassembler::Fail;
1135 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1136 Inst.addOperand(MCOperand::CreateReg(Reg));
1137 return MCDisassembler::Success;
1140 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1143 const void *Decoder) {
1145 return MCDisassembler::Fail;
1147 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1148 Inst.addOperand(MCOperand::CreateReg(Reg));
1149 return MCDisassembler::Success;
1152 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1155 const void *Decoder) {
1157 return MCDisassembler::Fail;
1159 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1160 Inst.addOperand(MCOperand::CreateReg(Reg));
1161 return MCDisassembler::Success;
1164 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1167 const void *Decoder) {
1169 return MCDisassembler::Fail;
1171 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1172 Inst.addOperand(MCOperand::CreateReg(Reg));
1173 return MCDisassembler::Success;
1176 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1179 const void *Decoder) {
1181 return MCDisassembler::Fail;
1183 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1184 Inst.addOperand(MCOperand::CreateReg(Reg));
1185 return MCDisassembler::Success;
1188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1191 const void *Decoder) {
1193 return MCDisassembler::Fail;
1195 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1196 Inst.addOperand(MCOperand::CreateReg(Reg));
1197 return MCDisassembler::Success;
1200 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1203 const void *Decoder) {
1205 return MCDisassembler::Fail;
1207 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1208 Inst.addOperand(MCOperand::CreateReg(Reg));
1209 return MCDisassembler::Success;
1212 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1215 const void *Decoder) {
1217 return MCDisassembler::Fail;
1219 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1220 Inst.addOperand(MCOperand::CreateReg(Reg));
1221 return MCDisassembler::Success;
1224 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1227 const void *Decoder) {
1228 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1229 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1230 return MCDisassembler::Success;
1233 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1236 const void *Decoder) {
1238 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1239 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1240 return MCDisassembler::Success;
1243 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1246 const void *Decoder) {
1247 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1249 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1250 return MCDisassembler::Success;
1253 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1256 const void *Decoder) {
1257 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1259 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1260 return MCDisassembler::Success;
1263 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1266 const void *Decoder) {
1267 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1268 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1269 return MCDisassembler::Success;
1272 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1275 const void *Decoder) {
1276 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1277 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1278 return MCDisassembler::Success;
1281 static DecodeStatus DecodeSimm16(MCInst &Inst,
1284 const void *Decoder) {
1285 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1286 return MCDisassembler::Success;
1289 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1292 const void *Decoder) {
1293 // We add one to the immediate field as it was encoded as 'imm - 1'.
1294 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1295 return MCDisassembler::Success;
1298 static DecodeStatus DecodeInsSize(MCInst &Inst,
1301 const void *Decoder) {
1302 // First we need to grab the pos(lsb) from MCInst.
1303 int Pos = Inst.getOperand(2).getImm();
1304 int Size = (int) Insn - Pos + 1;
1305 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1306 return MCDisassembler::Success;
1309 static DecodeStatus DecodeExtSize(MCInst &Inst,
1312 const void *Decoder) {
1313 int Size = (int) Insn + 1;
1314 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1315 return MCDisassembler::Success;
1318 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1319 uint64_t Address, const void *Decoder) {
1320 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1321 return MCDisassembler::Success;
1324 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1325 uint64_t Address, const void *Decoder) {
1326 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1327 return MCDisassembler::Success;