lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MathExtras.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 typedef MCDisassembler::DecodeStatus DecodeStatus;
  28
  29 namespace {
  30
  31 /// MipsDisassemblerBase - a disasembler class for Mips.
  32 class MipsDisassemblerBase : public MCDisassembler {
  33 public:
  34   /// Constructor     - Initializes the disassembler.
  35   ///
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  37                        bool bigEndian) :
  38     MCDisassembler(STI), RegInfo(Info),
  39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  40
  41   virtual ~MipsDisassemblerBase() {}
  42
  43   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   OwningPtr<const MCRegisterInfo> RegInfo;
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Info, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Info, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 189                                        unsigned Offset,
 190                                        uint64_t Address,
 191                                        const void *Decoder);
 192
 193 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 194                                      unsigned Insn,
 195                                      uint64_t Address,
 196                                      const void *Decoder);
 197
 198 static DecodeStatus DecodeMem(MCInst &Inst,
 199                               unsigned Insn,
 200                               uint64_t Address,
 201                               const void *Decoder);
 202
 203 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 209                                      unsigned Insn,
 210                                      uint64_t Address,
 211                                      const void *Decoder);
 212
 213 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 214                                uint64_t Address,
 215                                const void *Decoder);
 216
 217 static DecodeStatus DecodeSimm16(MCInst &Inst,
 218                                  unsigned Insn,
 219                                  uint64_t Address,
 220                                  const void *Decoder);
 221
 222 static DecodeStatus DecodeInsSize(MCInst &Inst,
 223                                   unsigned Insn,
 224                                   uint64_t Address,
 225                                   const void *Decoder);
 226
 227 static DecodeStatus DecodeExtSize(MCInst &Inst,
 228                                   unsigned Insn,
 229                                   uint64_t Address,
 230                                   const void *Decoder);
 231
 232 namespace llvm {
 233 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 234               TheMips64elTarget;
 235 }
 236
 237 static MCDisassembler *createMipsDisassembler(
 238                        const Target &T,
 239                        const MCSubtargetInfo &STI) {
 240   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 241 }
 242
 243 static MCDisassembler *createMipselDisassembler(
 244                        const Target &T,
 245                        const MCSubtargetInfo &STI) {
 246   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 247 }
 248
 249 static MCDisassembler *createMips64Disassembler(
 250                        const Target &T,
 251                        const MCSubtargetInfo &STI) {
 252   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 253 }
 254
 255 static MCDisassembler *createMips64elDisassembler(
 256                        const Target &T,
 257                        const MCSubtargetInfo &STI) {
 258   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 259 }
 260
 261 extern "C" void LLVMInitializeMipsDisassembler() {
 262   // Register the disassembler.
 263   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 264                                          createMipsDisassembler);
 265   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 266                                          createMipselDisassembler);
 267   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 268                                          createMips64Disassembler);
 269   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 270                                          createMips64elDisassembler);
 271 }
 272
 273
 274 #include "MipsGenDisassemblerTables.inc"
 275
 276   /// readInstruction - read four bytes from the MemoryObject
 277   /// and return 32 bit word sorted according to the given endianess
 278 static DecodeStatus readInstruction32(const MemoryObject &region,
 279                                       uint64_t address,
 280                                       uint64_t &size,
 281                                       uint32_t &insn,
 282                                       bool isBigEndian,
 283                                       bool IsMicroMips) {
 284   uint8_t Bytes[4];
 285
 286   // We want to read exactly 4 Bytes of data.
 287   if (region.readBytes(address, 4, Bytes) == -1) {
 288     size = 0;
 289     return MCDisassembler::Fail;
 290   }
 291
 292   if (isBigEndian) {
 293     // Encoded as a big-endian 32-bit word in the stream.
 294     insn = (Bytes[3] <<  0) |
 295            (Bytes[2] <<  8) |
 296            (Bytes[1] << 16) |
 297            (Bytes[0] << 24);
 298   }
 299   else {
 300     // Encoded as a small-endian 32-bit word in the stream.
 301     // Little-endian byte ordering:
 302     //   mips32r2:   4 | 3 | 2 | 1
 303     //   microMIPS:  2 | 1 | 4 | 3
 304     if (IsMicroMips) {
 305       insn = (Bytes[2] <<  0) |
 306              (Bytes[3] <<  8) |
 307              (Bytes[0] << 16) |
 308              (Bytes[1] << 24);
 309     } else {
 310       insn = (Bytes[0] <<  0) |
 311              (Bytes[1] <<  8) |
 312              (Bytes[2] << 16) |
 313              (Bytes[3] << 24);
 314     }
 315   }
 316
 317   return MCDisassembler::Success;
 318 }
 319
 320 DecodeStatus
 321 MipsDisassembler::getInstruction(MCInst &instr,
 322                                  uint64_t &Size,
 323                                  const MemoryObject &Region,
 324                                  uint64_t Address,
 325                                  raw_ostream &vStream,
 326                                  raw_ostream &cStream) const {
 327   uint32_t Insn;
 328
 329   DecodeStatus Result = readInstruction32(Region, Address, Size,
 330                                           Insn, isBigEndian, IsMicroMips);
 331   if (Result == MCDisassembler::Fail)
 332     return MCDisassembler::Fail;
 333
 334   if (IsMicroMips) {
 335     // Calling the auto-generated decoder function.
 336     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 337                                this, STI);
 338     if (Result != MCDisassembler::Fail) {
 339       Size = 4;
 340       return Result;
 341     }
 342     return MCDisassembler::Fail;
 343   }
 344
 345   // Calling the auto-generated decoder function.
 346   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 347                              this, STI);
 348   if (Result != MCDisassembler::Fail) {
 349     Size = 4;
 350     return Result;
 351   }
 352
 353   return MCDisassembler::Fail;
 354 }
 355
 356 DecodeStatus
 357 Mips64Disassembler::getInstruction(MCInst &instr,
 358                                    uint64_t &Size,
 359                                    const MemoryObject &Region,
 360                                    uint64_t Address,
 361                                    raw_ostream &vStream,
 362                                    raw_ostream &cStream) const {
 363   uint32_t Insn;
 364
 365   DecodeStatus Result = readInstruction32(Region, Address, Size,
 366                                           Insn, isBigEndian, false);
 367   if (Result == MCDisassembler::Fail)
 368     return MCDisassembler::Fail;
 369
 370   // Calling the auto-generated decoder function.
 371   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 372                              this, STI);
 373   if (Result != MCDisassembler::Fail) {
 374     Size = 4;
 375     return Result;
 376   }
 377   // If we fail to decode in Mips64 decoder space we can try in Mips32
 378   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 379                              this, STI);
 380   if (Result != MCDisassembler::Fail) {
 381     Size = 4;
 382     return Result;
 383   }
 384
 385   return MCDisassembler::Fail;
 386 }
 387
 388 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 389   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 390   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 391 }
 392
 393 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 394                                                  unsigned RegNo,
 395                                                  uint64_t Address,
 396                                                  const void *Decoder) {
 397
 398   return MCDisassembler::Fail;
 399
 400 }
 401
 402 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 403                                              unsigned RegNo,
 404                                              uint64_t Address,
 405                                              const void *Decoder) {
 406
 407   if (RegNo > 31)
 408     return MCDisassembler::Fail;
 409
 410   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 411   Inst.addOperand(MCOperand::CreateReg(Reg));
 412   return MCDisassembler::Success;
 413 }
 414
 415 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 416                                              unsigned RegNo,
 417                                              uint64_t Address,
 418                                              const void *Decoder) {
 419   if (RegNo > 31)
 420     return MCDisassembler::Fail;
 421   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 422   Inst.addOperand(MCOperand::CreateReg(Reg));
 423   return MCDisassembler::Success;
 424 }
 425
 426 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 427                                            unsigned RegNo,
 428                                            uint64_t Address,
 429                                            const void *Decoder) {
 430   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 431     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 432
 433   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 434 }
 435
 436 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 437                                             unsigned RegNo,
 438                                             uint64_t Address,
 439                                             const void *Decoder) {
 440   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 441 }
 442
 443 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 444                                              unsigned RegNo,
 445                                              uint64_t Address,
 446                                              const void *Decoder) {
 447   if (RegNo > 31)
 448     return MCDisassembler::Fail;
 449
 450   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 451   Inst.addOperand(MCOperand::CreateReg(Reg));
 452   return MCDisassembler::Success;
 453 }
 454
 455 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 456                                              unsigned RegNo,
 457                                              uint64_t Address,
 458                                              const void *Decoder) {
 459   if (RegNo > 31)
 460     return MCDisassembler::Fail;
 461
 462   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 463   Inst.addOperand(MCOperand::CreateReg(Reg));
 464   return MCDisassembler::Success;
 465 }
 466
 467 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 468                                               unsigned RegNo,
 469                                               uint64_t Address,
 470                                               const void *Decoder) {
 471   if (RegNo > 31)
 472     return MCDisassembler::Fail;
 473
 474   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 475   Inst.addOperand(MCOperand::CreateReg(Reg));
 476   return MCDisassembler::Success;
 477 }
 478
 479 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 480                                            unsigned RegNo,
 481                                            uint64_t Address,
 482                                            const void *Decoder) {
 483   if (RegNo > 31)
 484     return MCDisassembler::Fail;
 485   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 486   Inst.addOperand(MCOperand::CreateReg(Reg));
 487   return MCDisassembler::Success;
 488 }
 489
 490 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 491                                            unsigned RegNo,
 492                                            uint64_t Address,
 493                                            const void *Decoder) {
 494   if (RegNo > 7)
 495     return MCDisassembler::Fail;
 496   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 497   Inst.addOperand(MCOperand::CreateReg(Reg));
 498   return MCDisassembler::Success;
 499 }
 500
 501 static DecodeStatus DecodeMem(MCInst &Inst,
 502                               unsigned Insn,
 503                               uint64_t Address,
 504                               const void *Decoder) {
 505   int Offset = SignExtend32<16>(Insn & 0xffff);
 506   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 507   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 508
 509   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 510   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 511
 512   if(Inst.getOpcode() == Mips::SC){
 513     Inst.addOperand(MCOperand::CreateReg(Reg));
 514   }
 515
 516   Inst.addOperand(MCOperand::CreateReg(Reg));
 517   Inst.addOperand(MCOperand::CreateReg(Base));
 518   Inst.addOperand(MCOperand::CreateImm(Offset));
 519
 520   return MCDisassembler::Success;
 521 }
 522
 523 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 524                                      unsigned Insn,
 525                                      uint64_t Address,
 526                                      const void *Decoder) {
 527   int Offset = SignExtend32<12>(Insn & 0x0fff);
 528   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 529   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 530
 531   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 532   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 533
 534   Inst.addOperand(MCOperand::CreateReg(Reg));
 535   Inst.addOperand(MCOperand::CreateReg(Base));
 536   Inst.addOperand(MCOperand::CreateImm(Offset));
 537
 538   return MCDisassembler::Success;
 539 }
 540
 541 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 542                                      unsigned Insn,
 543                                      uint64_t Address,
 544                                      const void *Decoder) {
 545   int Offset = SignExtend32<16>(Insn & 0xffff);
 546   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 547   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 548
 549   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 550   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 551
 552   Inst.addOperand(MCOperand::CreateReg(Reg));
 553   Inst.addOperand(MCOperand::CreateReg(Base));
 554   Inst.addOperand(MCOperand::CreateImm(Offset));
 555
 556   return MCDisassembler::Success;
 557 }
 558
 559 static DecodeStatus DecodeFMem(MCInst &Inst,
 560                                unsigned Insn,
 561                                uint64_t Address,
 562                                const void *Decoder) {
 563   int Offset = SignExtend32<16>(Insn & 0xffff);
 564   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 565   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 566
 567   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 568   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 569
 570   Inst.addOperand(MCOperand::CreateReg(Reg));
 571   Inst.addOperand(MCOperand::CreateReg(Base));
 572   Inst.addOperand(MCOperand::CreateImm(Offset));
 573
 574   return MCDisassembler::Success;
 575 }
 576
 577
 578 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 579                                               unsigned RegNo,
 580                                               uint64_t Address,
 581                                               const void *Decoder) {
 582   // Currently only hardware register 29 is supported.
 583   if (RegNo != 29)
 584     return  MCDisassembler::Fail;
 585   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 586   return MCDisassembler::Success;
 587 }
 588
 589 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 590                                               unsigned RegNo,
 591                                               uint64_t Address,
 592                                               const void *Decoder) {
 593   if (RegNo > 30 || RegNo %2)
 594     return MCDisassembler::Fail;
 595
 596   ;
 597   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 598   Inst.addOperand(MCOperand::CreateReg(Reg));
 599   return MCDisassembler::Success;
 600 }
 601
 602 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 603                                                 unsigned RegNo,
 604                                                 uint64_t Address,
 605                                                 const void *Decoder) {
 606   if (RegNo >= 4)
 607     return MCDisassembler::Fail;
 608
 609   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 610   Inst.addOperand(MCOperand::CreateReg(Reg));
 611   return MCDisassembler::Success;
 612 }
 613
 614 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 615                                                unsigned RegNo,
 616                                                uint64_t Address,
 617                                                const void *Decoder) {
 618   if (RegNo >= 4)
 619     return MCDisassembler::Fail;
 620
 621   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 622   Inst.addOperand(MCOperand::CreateReg(Reg));
 623   return MCDisassembler::Success;
 624 }
 625
 626 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 627                                                unsigned RegNo,
 628                                                uint64_t Address,
 629                                                const void *Decoder) {
 630   if (RegNo >= 4)
 631     return MCDisassembler::Fail;
 632
 633   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 634   Inst.addOperand(MCOperand::CreateReg(Reg));
 635   return MCDisassembler::Success;
 636 }
 637
 638 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 639                                                unsigned RegNo,
 640                                                uint64_t Address,
 641                                                const void *Decoder) {
 642   if (RegNo > 31)
 643     return MCDisassembler::Fail;
 644
 645   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 646   Inst.addOperand(MCOperand::CreateReg(Reg));
 647   return MCDisassembler::Success;
 648 }
 649
 650 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 651                                                unsigned RegNo,
 652                                                uint64_t Address,
 653                                                const void *Decoder) {
 654   if (RegNo > 31)
 655     return MCDisassembler::Fail;
 656
 657   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 658   Inst.addOperand(MCOperand::CreateReg(Reg));
 659   return MCDisassembler::Success;
 660 }
 661
 662 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 663                                                unsigned RegNo,
 664                                                uint64_t Address,
 665                                                const void *Decoder) {
 666   if (RegNo > 31)
 667     return MCDisassembler::Fail;
 668
 669   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 670   Inst.addOperand(MCOperand::CreateReg(Reg));
 671   return MCDisassembler::Success;
 672 }
 673
 674 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 675                                        unsigned Offset,
 676                                        uint64_t Address,
 677                                        const void *Decoder) {
 678   unsigned BranchOffset = Offset & 0xffff;
 679   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 680   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 681   return MCDisassembler::Success;
 682 }
 683
 684 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 685                                      unsigned Insn,
 686                                      uint64_t Address,
 687                                      const void *Decoder) {
 688
 689   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 690   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 691   return MCDisassembler::Success;
 692 }
 693
 694
 695 static DecodeStatus DecodeSimm16(MCInst &Inst,
 696                                  unsigned Insn,
 697                                  uint64_t Address,
 698                                  const void *Decoder) {
 699   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 700   return MCDisassembler::Success;
 701 }
 702
 703 static DecodeStatus DecodeInsSize(MCInst &Inst,
 704                                   unsigned Insn,
 705                                   uint64_t Address,
 706                                   const void *Decoder) {
 707   // First we need to grab the pos(lsb) from MCInst.
 708   int Pos = Inst.getOperand(2).getImm();
 709   int Size = (int) Insn - Pos + 1;
 710   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 711   return MCDisassembler::Success;
 712 }
 713
 714 static DecodeStatus DecodeExtSize(MCInst &Inst,
 715                                   unsigned Insn,
 716                                   uint64_t Address,
 717                                   const void *Decoder) {
 718   int Size = (int) Insn  + 1;
 719   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 720   return MCDisassembler::Success;
 721 }