lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Ctx, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 209 // shifted left by 1 bit.
 210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 211                                          unsigned Offset,
 212                                          uint64_t Address,
 213                                          const void *Decoder);
 214
 215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 216 // shifted left by 1 bit.
 217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 218                                        unsigned Insn,
 219                                        uint64_t Address,
 220                                        const void *Decoder);
 221
 222 static DecodeStatus DecodeMem(MCInst &Inst,
 223                               unsigned Insn,
 224                               uint64_t Address,
 225                               const void *Decoder);
 226
 227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 228                                     uint64_t Address, const void *Decoder);
 229
 230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 231                                      unsigned Insn,
 232                                      uint64_t Address,
 233                                      const void *Decoder);
 234
 235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 236                                      unsigned Insn,
 237                                      uint64_t Address,
 238                                      const void *Decoder);
 239
 240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 241                                uint64_t Address,
 242                                const void *Decoder);
 243
 244 static DecodeStatus DecodeSimm16(MCInst &Inst,
 245                                  unsigned Insn,
 246                                  uint64_t Address,
 247                                  const void *Decoder);
 248
 249 // Decode the immediate field of an LSA instruction which
 250 // is off by one.
 251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 252                                  unsigned Insn,
 253                                  uint64_t Address,
 254                                  const void *Decoder);
 255
 256 static DecodeStatus DecodeInsSize(MCInst &Inst,
 257                                   unsigned Insn,
 258                                   uint64_t Address,
 259                                   const void *Decoder);
 260
 261 static DecodeStatus DecodeExtSize(MCInst &Inst,
 262                                   unsigned Insn,
 263                                   uint64_t Address,
 264                                   const void *Decoder);
 265
 266 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 267 /// handle.
 268 template <typename InsnType>
 269 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 270                                    const void *Decoder);
 271 namespace llvm {
 272 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 273               TheMips64elTarget;
 274 }
 275
 276 static MCDisassembler *createMipsDisassembler(
 277                        const Target &T,
 278                        const MCSubtargetInfo &STI,
 279                        MCContext &Ctx) {
 280   return new MipsDisassembler(STI, Ctx, true);
 281 }
 282
 283 static MCDisassembler *createMipselDisassembler(
 284                        const Target &T,
 285                        const MCSubtargetInfo &STI,
 286                        MCContext &Ctx) {
 287   return new MipsDisassembler(STI, Ctx, false);
 288 }
 289
 290 static MCDisassembler *createMips64Disassembler(
 291                        const Target &T,
 292                        const MCSubtargetInfo &STI,
 293                        MCContext &Ctx) {
 294   return new Mips64Disassembler(STI, Ctx, true);
 295 }
 296
 297 static MCDisassembler *createMips64elDisassembler(
 298                        const Target &T,
 299                        const MCSubtargetInfo &STI,
 300                        MCContext &Ctx) {
 301   return new Mips64Disassembler(STI, Ctx, false);
 302 }
 303
 304 extern "C" void LLVMInitializeMipsDisassembler() {
 305   // Register the disassembler.
 306   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 307                                          createMipsDisassembler);
 308   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 309                                          createMipselDisassembler);
 310   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 311                                          createMips64Disassembler);
 312   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 313                                          createMips64elDisassembler);
 314 }
 315
 316 #include "MipsGenDisassemblerTables.inc"
 317
 318 template <typename InsnType>
 319 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 320                                    const void *Decoder) {
 321   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 322   // The size of the n field depends on the element size
 323   // The register class also depends on this.
 324   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 325   unsigned NSize = 0;
 326   DecodeFN RegDecoder = nullptr;
 327   if ((tmp & 0x18) == 0x00) { // INSVE_B
 328     NSize = 4;
 329     RegDecoder = DecodeMSA128BRegisterClass;
 330   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 331     NSize = 3;
 332     RegDecoder = DecodeMSA128HRegisterClass;
 333   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 334     NSize = 2;
 335     RegDecoder = DecodeMSA128WRegisterClass;
 336   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 337     NSize = 1;
 338     RegDecoder = DecodeMSA128DRegisterClass;
 339   } else
 340     llvm_unreachable("Invalid encoding");
 341
 342   assert(NSize != 0 && RegDecoder != nullptr);
 343
 344   // $wd
 345   tmp = fieldFromInstruction(insn, 6, 5);
 346   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 347     return MCDisassembler::Fail;
 348   // $wd_in
 349   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 350     return MCDisassembler::Fail;
 351   // $n
 352   tmp = fieldFromInstruction(insn, 16, NSize);
 353   MI.addOperand(MCOperand::CreateImm(tmp));
 354   // $ws
 355   tmp = fieldFromInstruction(insn, 11, 5);
 356   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 357     return MCDisassembler::Fail;
 358   // $n2
 359   MI.addOperand(MCOperand::CreateImm(0));
 360
 361   return MCDisassembler::Success;
 362 }
 363
 364   /// readInstruction - read four bytes from the MemoryObject
 365   /// and return 32 bit word sorted according to the given endianess
 366 static DecodeStatus readInstruction32(const MemoryObject &region,
 367                                       uint64_t address,
 368                                       uint64_t &size,
 369                                       uint32_t &insn,
 370                                       bool isBigEndian,
 371                                       bool IsMicroMips) {
 372   uint8_t Bytes[4];
 373
 374   // We want to read exactly 4 Bytes of data.
 375   if (region.readBytes(address, 4, Bytes) == -1) {
 376     size = 0;
 377     return MCDisassembler::Fail;
 378   }
 379
 380   if (isBigEndian) {
 381     // Encoded as a big-endian 32-bit word in the stream.
 382     insn = (Bytes[3] <<  0) |
 383            (Bytes[2] <<  8) |
 384            (Bytes[1] << 16) |
 385            (Bytes[0] << 24);
 386   }
 387   else {
 388     // Encoded as a small-endian 32-bit word in the stream.
 389     // Little-endian byte ordering:
 390     //   mips32r2:   4 | 3 | 2 | 1
 391     //   microMIPS:  2 | 1 | 4 | 3
 392     if (IsMicroMips) {
 393       insn = (Bytes[2] <<  0) |
 394              (Bytes[3] <<  8) |
 395              (Bytes[0] << 16) |
 396              (Bytes[1] << 24);
 397     } else {
 398       insn = (Bytes[0] <<  0) |
 399              (Bytes[1] <<  8) |
 400              (Bytes[2] << 16) |
 401              (Bytes[3] << 24);
 402     }
 403   }
 404
 405   return MCDisassembler::Success;
 406 }
 407
 408 DecodeStatus
 409 MipsDisassembler::getInstruction(MCInst &instr,
 410                                  uint64_t &Size,
 411                                  const MemoryObject &Region,
 412                                  uint64_t Address,
 413                                  raw_ostream &vStream,
 414                                  raw_ostream &cStream) const {
 415   uint32_t Insn;
 416
 417   DecodeStatus Result = readInstruction32(Region, Address, Size,
 418                                           Insn, isBigEndian, IsMicroMips);
 419   if (Result == MCDisassembler::Fail)
 420     return MCDisassembler::Fail;
 421
 422   if (IsMicroMips) {
 423     // Calling the auto-generated decoder function.
 424     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 425                                this, STI);
 426     if (Result != MCDisassembler::Fail) {
 427       Size = 4;
 428       return Result;
 429     }
 430     return MCDisassembler::Fail;
 431   }
 432
 433   // Calling the auto-generated decoder function.
 434   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 435                              this, STI);
 436   if (Result != MCDisassembler::Fail) {
 437     Size = 4;
 438     return Result;
 439   }
 440
 441   return MCDisassembler::Fail;
 442 }
 443
 444 DecodeStatus
 445 Mips64Disassembler::getInstruction(MCInst &instr,
 446                                    uint64_t &Size,
 447                                    const MemoryObject &Region,
 448                                    uint64_t Address,
 449                                    raw_ostream &vStream,
 450                                    raw_ostream &cStream) const {
 451   uint32_t Insn;
 452
 453   DecodeStatus Result = readInstruction32(Region, Address, Size,
 454                                           Insn, isBigEndian, false);
 455   if (Result == MCDisassembler::Fail)
 456     return MCDisassembler::Fail;
 457
 458   // Calling the auto-generated decoder function.
 459   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 460                              this, STI);
 461   if (Result != MCDisassembler::Fail) {
 462     Size = 4;
 463     return Result;
 464   }
 465   // If we fail to decode in Mips64 decoder space we can try in Mips32
 466   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 467                              this, STI);
 468   if (Result != MCDisassembler::Fail) {
 469     Size = 4;
 470     return Result;
 471   }
 472
 473   return MCDisassembler::Fail;
 474 }
 475
 476 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 477   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 478   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 479   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 480 }
 481
 482 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 483                                                  unsigned RegNo,
 484                                                  uint64_t Address,
 485                                                  const void *Decoder) {
 486
 487   return MCDisassembler::Fail;
 488
 489 }
 490
 491 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 492                                              unsigned RegNo,
 493                                              uint64_t Address,
 494                                              const void *Decoder) {
 495
 496   if (RegNo > 31)
 497     return MCDisassembler::Fail;
 498
 499   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 500   Inst.addOperand(MCOperand::CreateReg(Reg));
 501   return MCDisassembler::Success;
 502 }
 503
 504 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 505                                              unsigned RegNo,
 506                                              uint64_t Address,
 507                                              const void *Decoder) {
 508   if (RegNo > 31)
 509     return MCDisassembler::Fail;
 510   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 511   Inst.addOperand(MCOperand::CreateReg(Reg));
 512   return MCDisassembler::Success;
 513 }
 514
 515 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 516                                            unsigned RegNo,
 517                                            uint64_t Address,
 518                                            const void *Decoder) {
 519   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 520     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 521
 522   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 523 }
 524
 525 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 526                                             unsigned RegNo,
 527                                             uint64_t Address,
 528                                             const void *Decoder) {
 529   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 530 }
 531
 532 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 533                                              unsigned RegNo,
 534                                              uint64_t Address,
 535                                              const void *Decoder) {
 536   if (RegNo > 31)
 537     return MCDisassembler::Fail;
 538
 539   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 540   Inst.addOperand(MCOperand::CreateReg(Reg));
 541   return MCDisassembler::Success;
 542 }
 543
 544 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 545                                              unsigned RegNo,
 546                                              uint64_t Address,
 547                                              const void *Decoder) {
 548   if (RegNo > 31)
 549     return MCDisassembler::Fail;
 550
 551   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 552   Inst.addOperand(MCOperand::CreateReg(Reg));
 553   return MCDisassembler::Success;
 554 }
 555
 556 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 557                                               unsigned RegNo,
 558                                               uint64_t Address,
 559                                               const void *Decoder) {
 560   if (RegNo > 31)
 561     return MCDisassembler::Fail;
 562
 563   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 564   Inst.addOperand(MCOperand::CreateReg(Reg));
 565   return MCDisassembler::Success;
 566 }
 567
 568 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 569                                            unsigned RegNo,
 570                                            uint64_t Address,
 571                                            const void *Decoder) {
 572   if (RegNo > 31)
 573     return MCDisassembler::Fail;
 574   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 575   Inst.addOperand(MCOperand::CreateReg(Reg));
 576   return MCDisassembler::Success;
 577 }
 578
 579 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 580                                            unsigned RegNo,
 581                                            uint64_t Address,
 582                                            const void *Decoder) {
 583   if (RegNo > 7)
 584     return MCDisassembler::Fail;
 585   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 586   Inst.addOperand(MCOperand::CreateReg(Reg));
 587   return MCDisassembler::Success;
 588 }
 589
 590 static DecodeStatus DecodeMem(MCInst &Inst,
 591                               unsigned Insn,
 592                               uint64_t Address,
 593                               const void *Decoder) {
 594   int Offset = SignExtend32<16>(Insn & 0xffff);
 595   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 596   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 597
 598   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 599   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 600
 601   if(Inst.getOpcode() == Mips::SC){
 602     Inst.addOperand(MCOperand::CreateReg(Reg));
 603   }
 604
 605   Inst.addOperand(MCOperand::CreateReg(Reg));
 606   Inst.addOperand(MCOperand::CreateReg(Base));
 607   Inst.addOperand(MCOperand::CreateImm(Offset));
 608
 609   return MCDisassembler::Success;
 610 }
 611
 612 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 613                                     uint64_t Address, const void *Decoder) {
 614   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 615   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 616   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 617
 618   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 619   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 620
 621   Inst.addOperand(MCOperand::CreateReg(Reg));
 622   Inst.addOperand(MCOperand::CreateReg(Base));
 623
 624   // The immediate field of an LD/ST instruction is scaled which means it must
 625   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 626   // data format.
 627   // .b - 1 byte
 628   // .h - 2 bytes
 629   // .w - 4 bytes
 630   // .d - 8 bytes
 631   switch(Inst.getOpcode())
 632   {
 633   default:
 634     assert (0 && "Unexpected instruction");
 635     return MCDisassembler::Fail;
 636     break;
 637   case Mips::LD_B:
 638   case Mips::ST_B:
 639     Inst.addOperand(MCOperand::CreateImm(Offset));
 640     break;
 641   case Mips::LD_H:
 642   case Mips::ST_H:
 643     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 644     break;
 645   case Mips::LD_W:
 646   case Mips::ST_W:
 647     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 648     break;
 649   case Mips::LD_D:
 650   case Mips::ST_D:
 651     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 652     break;
 653   }
 654
 655   return MCDisassembler::Success;
 656 }
 657
 658 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 659                                      unsigned Insn,
 660                                      uint64_t Address,
 661                                      const void *Decoder) {
 662   int Offset = SignExtend32<12>(Insn & 0x0fff);
 663   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 664   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 665
 666   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 667   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 668
 669   if (Inst.getOpcode() == Mips::SC_MM)
 670     Inst.addOperand(MCOperand::CreateReg(Reg));
 671
 672   Inst.addOperand(MCOperand::CreateReg(Reg));
 673   Inst.addOperand(MCOperand::CreateReg(Base));
 674   Inst.addOperand(MCOperand::CreateImm(Offset));
 675
 676   return MCDisassembler::Success;
 677 }
 678
 679 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 680                                      unsigned Insn,
 681                                      uint64_t Address,
 682                                      const void *Decoder) {
 683   int Offset = SignExtend32<16>(Insn & 0xffff);
 684   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 685   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 686
 687   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 688   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 689
 690   Inst.addOperand(MCOperand::CreateReg(Reg));
 691   Inst.addOperand(MCOperand::CreateReg(Base));
 692   Inst.addOperand(MCOperand::CreateImm(Offset));
 693
 694   return MCDisassembler::Success;
 695 }
 696
 697 static DecodeStatus DecodeFMem(MCInst &Inst,
 698                                unsigned Insn,
 699                                uint64_t Address,
 700                                const void *Decoder) {
 701   int Offset = SignExtend32<16>(Insn & 0xffff);
 702   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 703   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 704
 705   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 706   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 707
 708   Inst.addOperand(MCOperand::CreateReg(Reg));
 709   Inst.addOperand(MCOperand::CreateReg(Base));
 710   Inst.addOperand(MCOperand::CreateImm(Offset));
 711
 712   return MCDisassembler::Success;
 713 }
 714
 715
 716 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 717                                               unsigned RegNo,
 718                                               uint64_t Address,
 719                                               const void *Decoder) {
 720   // Currently only hardware register 29 is supported.
 721   if (RegNo != 29)
 722     return  MCDisassembler::Fail;
 723   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 724   return MCDisassembler::Success;
 725 }
 726
 727 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 728                                               unsigned RegNo,
 729                                               uint64_t Address,
 730                                               const void *Decoder) {
 731   if (RegNo > 30 || RegNo %2)
 732     return MCDisassembler::Fail;
 733
 734   ;
 735   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 736   Inst.addOperand(MCOperand::CreateReg(Reg));
 737   return MCDisassembler::Success;
 738 }
 739
 740 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 741                                                 unsigned RegNo,
 742                                                 uint64_t Address,
 743                                                 const void *Decoder) {
 744   if (RegNo >= 4)
 745     return MCDisassembler::Fail;
 746
 747   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 748   Inst.addOperand(MCOperand::CreateReg(Reg));
 749   return MCDisassembler::Success;
 750 }
 751
 752 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 753                                                unsigned RegNo,
 754                                                uint64_t Address,
 755                                                const void *Decoder) {
 756   if (RegNo >= 4)
 757     return MCDisassembler::Fail;
 758
 759   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 760   Inst.addOperand(MCOperand::CreateReg(Reg));
 761   return MCDisassembler::Success;
 762 }
 763
 764 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 765                                                unsigned RegNo,
 766                                                uint64_t Address,
 767                                                const void *Decoder) {
 768   if (RegNo >= 4)
 769     return MCDisassembler::Fail;
 770
 771   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 772   Inst.addOperand(MCOperand::CreateReg(Reg));
 773   return MCDisassembler::Success;
 774 }
 775
 776 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 777                                                unsigned RegNo,
 778                                                uint64_t Address,
 779                                                const void *Decoder) {
 780   if (RegNo > 31)
 781     return MCDisassembler::Fail;
 782
 783   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 784   Inst.addOperand(MCOperand::CreateReg(Reg));
 785   return MCDisassembler::Success;
 786 }
 787
 788 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 789                                                unsigned RegNo,
 790                                                uint64_t Address,
 791                                                const void *Decoder) {
 792   if (RegNo > 31)
 793     return MCDisassembler::Fail;
 794
 795   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 796   Inst.addOperand(MCOperand::CreateReg(Reg));
 797   return MCDisassembler::Success;
 798 }
 799
 800 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 801                                                unsigned RegNo,
 802                                                uint64_t Address,
 803                                                const void *Decoder) {
 804   if (RegNo > 31)
 805     return MCDisassembler::Fail;
 806
 807   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 808   Inst.addOperand(MCOperand::CreateReg(Reg));
 809   return MCDisassembler::Success;
 810 }
 811
 812 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 813                                                unsigned RegNo,
 814                                                uint64_t Address,
 815                                                const void *Decoder) {
 816   if (RegNo > 31)
 817     return MCDisassembler::Fail;
 818
 819   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 820   Inst.addOperand(MCOperand::CreateReg(Reg));
 821   return MCDisassembler::Success;
 822 }
 823
 824 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 825                                                unsigned RegNo,
 826                                                uint64_t Address,
 827                                                const void *Decoder) {
 828   if (RegNo > 7)
 829     return MCDisassembler::Fail;
 830
 831   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 832   Inst.addOperand(MCOperand::CreateReg(Reg));
 833   return MCDisassembler::Success;
 834 }
 835
 836 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 837                                        unsigned Offset,
 838                                        uint64_t Address,
 839                                        const void *Decoder) {
 840   unsigned BranchOffset = Offset & 0xffff;
 841   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 842   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 843   return MCDisassembler::Success;
 844 }
 845
 846 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 847                                      unsigned Insn,
 848                                      uint64_t Address,
 849                                      const void *Decoder) {
 850
 851   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 852   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 853   return MCDisassembler::Success;
 854 }
 855
 856 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 857                                          unsigned Offset,
 858                                          uint64_t Address,
 859                                          const void *Decoder) {
 860   unsigned BranchOffset = Offset & 0xffff;
 861   BranchOffset = SignExtend32<18>(BranchOffset << 1);
 862   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 863   return MCDisassembler::Success;
 864 }
 865
 866 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 867                                        unsigned Insn,
 868                                        uint64_t Address,
 869                                        const void *Decoder) {
 870   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 871   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 872   return MCDisassembler::Success;
 873 }
 874
 875 static DecodeStatus DecodeSimm16(MCInst &Inst,
 876                                  unsigned Insn,
 877                                  uint64_t Address,
 878                                  const void *Decoder) {
 879   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 880   return MCDisassembler::Success;
 881 }
 882
 883 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 884                                  unsigned Insn,
 885                                  uint64_t Address,
 886                                  const void *Decoder) {
 887   // We add one to the immediate field as it was encoded as 'imm - 1'.
 888   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
 889   return MCDisassembler::Success;
 890 }
 891
 892 static DecodeStatus DecodeInsSize(MCInst &Inst,
 893                                   unsigned Insn,
 894                                   uint64_t Address,
 895                                   const void *Decoder) {
 896   // First we need to grab the pos(lsb) from MCInst.
 897   int Pos = Inst.getOperand(2).getImm();
 898   int Size = (int) Insn - Pos + 1;
 899   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 900   return MCDisassembler::Success;
 901 }
 902
 903 static DecodeStatus DecodeExtSize(MCInst &Inst,
 904                                   unsigned Insn,
 905                                   uint64_t Address,
 906                                   const void *Decoder) {
 907   int Size = (int) Insn  + 1;
 908   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 909   return MCDisassembler::Success;
 910 }