lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Ctx, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   bool isMips32r6() const {
  67     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  68   }
  69
  70   /// getInstruction - See MCDisassembler.
  71   DecodeStatus getInstruction(MCInst &instr,
  72                               uint64_t &size,
  73                               const MemoryObject &region,
  74                               uint64_t address,
  75                               raw_ostream &vStream,
  76                               raw_ostream &cStream) const override;
  77 };
  78
  79
  80 /// Mips64Disassembler - a disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   /// Constructor     - Initializes the disassembler.
  84   ///
  85   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  86                      bool bigEndian) :
  87     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  88
  89   /// getInstruction - See MCDisassembler.
  90   DecodeStatus getInstruction(MCInst &instr,
  91                               uint64_t &size,
  92                               const MemoryObject &region,
  93                               uint64_t address,
  94                               raw_ostream &vStream,
  95                               raw_ostream &cStream) const override;
  96 };
  97
  98 } // end anonymous namespace
  99
 100 // Forward declare these because the autogenerated code will reference them.
 101 // Definitions are further down.
 102 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 103                                              unsigned RegNo,
 104                                              uint64_t Address,
 105                                              const void *Decoder);
 106
 107 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 108                                                  unsigned RegNo,
 109                                                  uint64_t Address,
 110                                                  const void *Decoder);
 111
 112 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 118                                            unsigned Insn,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 123                                             unsigned RegNo,
 124                                             uint64_t Address,
 125                                             const void *Decoder);
 126
 127 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 128                                              unsigned RegNo,
 129                                              uint64_t Address,
 130                                              const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 138                                               unsigned RegNo,
 139                                               uint64_t Address,
 140                                               const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 153                                               unsigned Insn,
 154                                               uint64_t Address,
 155                                               const void *Decoder);
 156
 157 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 158                                               unsigned RegNo,
 159                                               uint64_t Address,
 160                                               const void *Decoder);
 161
 162 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 163                                                 unsigned RegNo,
 164                                                 uint64_t Address,
 165                                                 const void *Decoder);
 166
 167 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 168                                                unsigned RegNo,
 169                                                uint64_t Address,
 170                                                const void *Decoder);
 171
 172 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 173                                                unsigned RegNo,
 174                                                uint64_t Address,
 175                                                const void *Decoder);
 176
 177 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 178                                                unsigned RegNo,
 179                                                uint64_t Address,
 180                                                const void *Decoder);
 181
 182 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 183                                                unsigned RegNo,
 184                                                uint64_t Address,
 185                                                const void *Decoder);
 186
 187 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 188                                                unsigned RegNo,
 189                                                uint64_t Address,
 190                                                const void *Decoder);
 191
 192 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 193                                                unsigned RegNo,
 194                                                uint64_t Address,
 195                                                const void *Decoder);
 196
 197 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 198                                                unsigned RegNo,
 199                                                uint64_t Address,
 200                                                const void *Decoder);
 201
 202 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 203                                             unsigned RegNo,
 204                                             uint64_t Address,
 205                                             const void *Decoder);
 206
 207 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 208                                        unsigned Offset,
 209                                        uint64_t Address,
 210                                        const void *Decoder);
 211
 212 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 213                                      unsigned Insn,
 214                                      uint64_t Address,
 215                                      const void *Decoder);
 216
 217 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 218                                          unsigned Offset,
 219                                          uint64_t Address,
 220                                          const void *Decoder);
 221
 222 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 223                                          unsigned Offset,
 224                                          uint64_t Address,
 225                                          const void *Decoder);
 226
 227 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 228 // shifted left by 1 bit.
 229 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 235 // shifted left by 1 bit.
 236 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 237                                        unsigned Insn,
 238                                        uint64_t Address,
 239                                        const void *Decoder);
 240
 241 static DecodeStatus DecodeMem(MCInst &Inst,
 242                               unsigned Insn,
 243                               uint64_t Address,
 244                               const void *Decoder);
 245
 246 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 247                                     uint64_t Address, const void *Decoder);
 248
 249 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 250                                      unsigned Insn,
 251                                      uint64_t Address,
 252                                      const void *Decoder);
 253
 254 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 255                                      unsigned Insn,
 256                                      uint64_t Address,
 257                                      const void *Decoder);
 258
 259 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 260                                uint64_t Address,
 261                                const void *Decoder);
 262
 263 static DecodeStatus DecodeSimm16(MCInst &Inst,
 264                                  unsigned Insn,
 265                                  uint64_t Address,
 266                                  const void *Decoder);
 267
 268 // Decode the immediate field of an LSA instruction which
 269 // is off by one.
 270 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 271                                  unsigned Insn,
 272                                  uint64_t Address,
 273                                  const void *Decoder);
 274
 275 static DecodeStatus DecodeInsSize(MCInst &Inst,
 276                                   unsigned Insn,
 277                                   uint64_t Address,
 278                                   const void *Decoder);
 279
 280 static DecodeStatus DecodeExtSize(MCInst &Inst,
 281                                   unsigned Insn,
 282                                   uint64_t Address,
 283                                   const void *Decoder);
 284
 285 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 286                                      uint64_t Address, const void *Decoder);
 287
 288 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 289                                      uint64_t Address, const void *Decoder);
 290
 291 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 292 /// handle.
 293 template <typename InsnType>
 294 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 295                                    const void *Decoder);
 296
 297 template <typename InsnType>
 298 static DecodeStatus
 299 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 300                       const void *Decoder);
 301
 302 template <typename InsnType>
 303 static DecodeStatus
 304 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 305                        const void *Decoder);
 306
 307 template <typename InsnType>
 308 static DecodeStatus
 309 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 310                        const void *Decoder);
 311
 312 template <typename InsnType>
 313 static DecodeStatus
 314 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 315                        const void *Decoder);
 316
 317 template <typename InsnType>
 318 static DecodeStatus
 319 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 320                       const void *Decoder);
 321
 322 template <typename InsnType>
 323 static DecodeStatus
 324 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 325                        const void *Decoder);
 326
 327 namespace llvm {
 328 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 329               TheMips64elTarget;
 330 }
 331
 332 static MCDisassembler *createMipsDisassembler(
 333                        const Target &T,
 334                        const MCSubtargetInfo &STI,
 335                        MCContext &Ctx) {
 336   return new MipsDisassembler(STI, Ctx, true);
 337 }
 338
 339 static MCDisassembler *createMipselDisassembler(
 340                        const Target &T,
 341                        const MCSubtargetInfo &STI,
 342                        MCContext &Ctx) {
 343   return new MipsDisassembler(STI, Ctx, false);
 344 }
 345
 346 static MCDisassembler *createMips64Disassembler(
 347                        const Target &T,
 348                        const MCSubtargetInfo &STI,
 349                        MCContext &Ctx) {
 350   return new Mips64Disassembler(STI, Ctx, true);
 351 }
 352
 353 static MCDisassembler *createMips64elDisassembler(
 354                        const Target &T,
 355                        const MCSubtargetInfo &STI,
 356                        MCContext &Ctx) {
 357   return new Mips64Disassembler(STI, Ctx, false);
 358 }
 359
 360 extern "C" void LLVMInitializeMipsDisassembler() {
 361   // Register the disassembler.
 362   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 363                                          createMipsDisassembler);
 364   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 365                                          createMipselDisassembler);
 366   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 367                                          createMips64Disassembler);
 368   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 369                                          createMips64elDisassembler);
 370 }
 371
 372 #include "MipsGenDisassemblerTables.inc"
 373
 374 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 375   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 376   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 377   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 378 }
 379
 380 template <typename InsnType>
 381 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 382                                    const void *Decoder) {
 383   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 384   // The size of the n field depends on the element size
 385   // The register class also depends on this.
 386   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 387   unsigned NSize = 0;
 388   DecodeFN RegDecoder = nullptr;
 389   if ((tmp & 0x18) == 0x00) { // INSVE_B
 390     NSize = 4;
 391     RegDecoder = DecodeMSA128BRegisterClass;
 392   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 393     NSize = 3;
 394     RegDecoder = DecodeMSA128HRegisterClass;
 395   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 396     NSize = 2;
 397     RegDecoder = DecodeMSA128WRegisterClass;
 398   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 399     NSize = 1;
 400     RegDecoder = DecodeMSA128DRegisterClass;
 401   } else
 402     llvm_unreachable("Invalid encoding");
 403
 404   assert(NSize != 0 && RegDecoder != nullptr);
 405
 406   // $wd
 407   tmp = fieldFromInstruction(insn, 6, 5);
 408   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 409     return MCDisassembler::Fail;
 410   // $wd_in
 411   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 412     return MCDisassembler::Fail;
 413   // $n
 414   tmp = fieldFromInstruction(insn, 16, NSize);
 415   MI.addOperand(MCOperand::CreateImm(tmp));
 416   // $ws
 417   tmp = fieldFromInstruction(insn, 11, 5);
 418   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 419     return MCDisassembler::Fail;
 420   // $n2
 421   MI.addOperand(MCOperand::CreateImm(0));
 422
 423   return MCDisassembler::Success;
 424 }
 425
 426 template <typename InsnType>
 427 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 428                                           uint64_t Address,
 429                                           const void *Decoder) {
 430   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 431   // (otherwise we would have matched the ADDI instruction from the earlier
 432   // ISA's instead).
 433   //
 434   // We have:
 435   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 436   //      BOVC if rs >= rt
 437   //      BEQZALC if rs == 0 && rt != 0
 438   //      BEQC if rs < rt && rs != 0
 439
 440   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 441   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 442   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 443   bool HasRs = false;
 444
 445   if (Rs >= Rt) {
 446     MI.setOpcode(Mips::BOVC);
 447     HasRs = true;
 448   } else if (Rs != 0 && Rs < Rt) {
 449     MI.setOpcode(Mips::BEQC);
 450     HasRs = true;
 451   } else
 452     MI.setOpcode(Mips::BEQZALC);
 453
 454   if (HasRs)
 455     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 456                                        Rs)));
 457
 458   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 459                                      Rt)));
 460   MI.addOperand(MCOperand::CreateImm(Imm));
 461
 462   return MCDisassembler::Success;
 463 }
 464
 465 template <typename InsnType>
 466 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 467                                            uint64_t Address,
 468                                            const void *Decoder) {
 469   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 470   // (otherwise we would have matched the ADDI instruction from the earlier
 471   // ISA's instead).
 472   //
 473   // We have:
 474   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 475   //      BNVC if rs >= rt
 476   //      BNEZALC if rs == 0 && rt != 0
 477   //      BNEC if rs < rt && rs != 0
 478
 479   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 480   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 481   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 482   bool HasRs = false;
 483
 484   if (Rs >= Rt) {
 485     MI.setOpcode(Mips::BNVC);
 486     HasRs = true;
 487   } else if (Rs != 0 && Rs < Rt) {
 488     MI.setOpcode(Mips::BNEC);
 489     HasRs = true;
 490   } else
 491     MI.setOpcode(Mips::BNEZALC);
 492
 493   if (HasRs)
 494     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 495                                        Rs)));
 496
 497   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 498                                      Rt)));
 499   MI.addOperand(MCOperand::CreateImm(Imm));
 500
 501   return MCDisassembler::Success;
 502 }
 503
 504 template <typename InsnType>
 505 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 506                                            uint64_t Address,
 507                                            const void *Decoder) {
 508   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 509   // (otherwise we would have matched the BLEZL instruction from the earlier
 510   // ISA's instead).
 511   //
 512   // We have:
 513   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 514   //      Invalid if rs == 0
 515   //      BLEZC   if rs == 0  && rt != 0
 516   //      BGEZC   if rs == rt && rt != 0
 517   //      BGEC    if rs != rt && rs != 0  && rt != 0
 518
 519   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 520   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 521   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 522   bool HasRs = false;
 523
 524   if (Rt == 0)
 525     return MCDisassembler::Fail;
 526   else if (Rs == 0)
 527     MI.setOpcode(Mips::BLEZC);
 528   else if (Rs == Rt)
 529     MI.setOpcode(Mips::BGEZC);
 530   else {
 531     HasRs = true;
 532     MI.setOpcode(Mips::BGEC);
 533   }
 534
 535   if (HasRs)
 536     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 537                                        Rs)));
 538
 539   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 540                                      Rt)));
 541
 542   MI.addOperand(MCOperand::CreateImm(Imm));
 543
 544   return MCDisassembler::Success;
 545 }
 546
 547 template <typename InsnType>
 548 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 549                                            uint64_t Address,
 550                                            const void *Decoder) {
 551   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 552   // (otherwise we would have matched the BGTZL instruction from the earlier
 553   // ISA's instead).
 554   //
 555   // We have:
 556   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 557   //      Invalid if rs == 0
 558   //      BGTZC   if rs == 0  && rt != 0
 559   //      BLTZC   if rs == rt && rt != 0
 560   //      BLTC    if rs != rt && rs != 0  && rt != 0
 561
 562   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 563   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 564   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 565
 566   if (Rt == 0)
 567     return MCDisassembler::Fail;
 568   else if (Rs == 0)
 569     MI.setOpcode(Mips::BGTZC);
 570   else if (Rs == Rt)
 571     MI.setOpcode(Mips::BLTZC);
 572   else
 573     return MCDisassembler::Fail; // FIXME: BLTC is not implemented yet.
 574
 575   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 576                                      Rt)));
 577
 578   MI.addOperand(MCOperand::CreateImm(Imm));
 579
 580   return MCDisassembler::Success;
 581 }
 582
 583 template <typename InsnType>
 584 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 585                                           uint64_t Address,
 586                                           const void *Decoder) {
 587   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 588   // (otherwise we would have matched the BGTZ instruction from the earlier
 589   // ISA's instead).
 590   //
 591   // We have:
 592   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 593   //      BGTZ    if rt == 0
 594   //      BGTZALC if rs == 0 && rt != 0
 595   //      BLTZALC if rs != 0 && rs == rt
 596   //      BLTUC   if rs != 0 && rs != rt
 597
 598   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 599   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 600   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 601   bool HasRs = false;
 602   bool HasRt = false;
 603
 604   if (Rt == 0) {
 605     MI.setOpcode(Mips::BGTZ);
 606     HasRs = true;
 607   } else if (Rs == 0) {
 608     MI.setOpcode(Mips::BGTZALC);
 609     HasRt = true;
 610   } else if (Rs == Rt) {
 611     MI.setOpcode(Mips::BLTZALC);
 612     HasRs = true;
 613   } else
 614     return MCDisassembler::Fail; // BLTUC not implemented yet
 615
 616   if (HasRs)
 617     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 618                                        Rs)));
 619
 620   if (HasRt)
 621     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 622                                        Rt)));
 623
 624   MI.addOperand(MCOperand::CreateImm(Imm));
 625
 626   return MCDisassembler::Success;
 627 }
 628
 629 template <typename InsnType>
 630 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 631                                            uint64_t Address,
 632                                            const void *Decoder) {
 633   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 634   // (otherwise we would have matched the BLEZL instruction from the earlier
 635   // ISA's instead).
 636   //
 637   // We have:
 638   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 639   //      Invalid   if rs == 0
 640   //      BLEZALC   if rs == 0  && rt != 0
 641   //      BGEZALC   if rs == rt && rt != 0
 642   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 643
 644   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 645   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 646   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2;
 647   bool HasRs = false;
 648
 649   if (Rt == 0)
 650     return MCDisassembler::Fail;
 651   else if (Rs == 0)
 652     MI.setOpcode(Mips::BLEZALC);
 653   else if (Rs == Rt)
 654     MI.setOpcode(Mips::BGEZALC);
 655   else {
 656     HasRs = true;
 657     MI.setOpcode(Mips::BGEUC);
 658   }
 659
 660   if (HasRs)
 661     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 662                                        Rs)));
 663   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 664                                      Rt)));
 665
 666   MI.addOperand(MCOperand::CreateImm(Imm));
 667
 668   return MCDisassembler::Success;
 669 }
 670
 671   /// readInstruction - read four bytes from the MemoryObject
 672   /// and return 32 bit word sorted according to the given endianess
 673 static DecodeStatus readInstruction32(const MemoryObject &region,
 674                                       uint64_t address,
 675                                       uint64_t &size,
 676                                       uint32_t &insn,
 677                                       bool isBigEndian,
 678                                       bool IsMicroMips) {
 679   uint8_t Bytes[4];
 680
 681   // We want to read exactly 4 Bytes of data.
 682   if (region.readBytes(address, 4, Bytes) == -1) {
 683     size = 0;
 684     return MCDisassembler::Fail;
 685   }
 686
 687   if (isBigEndian) {
 688     // Encoded as a big-endian 32-bit word in the stream.
 689     insn = (Bytes[3] <<  0) |
 690            (Bytes[2] <<  8) |
 691            (Bytes[1] << 16) |
 692            (Bytes[0] << 24);
 693   }
 694   else {
 695     // Encoded as a small-endian 32-bit word in the stream.
 696     // Little-endian byte ordering:
 697     //   mips32r2:   4 | 3 | 2 | 1
 698     //   microMIPS:  2 | 1 | 4 | 3
 699     if (IsMicroMips) {
 700       insn = (Bytes[2] <<  0) |
 701              (Bytes[3] <<  8) |
 702              (Bytes[0] << 16) |
 703              (Bytes[1] << 24);
 704     } else {
 705       insn = (Bytes[0] <<  0) |
 706              (Bytes[1] <<  8) |
 707              (Bytes[2] << 16) |
 708              (Bytes[3] << 24);
 709     }
 710   }
 711
 712   return MCDisassembler::Success;
 713 }
 714
 715 DecodeStatus
 716 MipsDisassembler::getInstruction(MCInst &instr,
 717                                  uint64_t &Size,
 718                                  const MemoryObject &Region,
 719                                  uint64_t Address,
 720                                  raw_ostream &vStream,
 721                                  raw_ostream &cStream) const {
 722   uint32_t Insn;
 723
 724   DecodeStatus Result = readInstruction32(Region, Address, Size,
 725                                           Insn, isBigEndian, IsMicroMips);
 726   if (Result == MCDisassembler::Fail)
 727     return MCDisassembler::Fail;
 728
 729   if (IsMicroMips) {
 730     // Calling the auto-generated decoder function.
 731     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 732                                this, STI);
 733     if (Result != MCDisassembler::Fail) {
 734       Size = 4;
 735       return Result;
 736     }
 737     return MCDisassembler::Fail;
 738   }
 739
 740   if (isMips32r6()) {
 741     Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 742                                Address, this, STI);
 743     if (Result != MCDisassembler::Fail) {
 744       Size = 4;
 745       return Result;
 746     }
 747   }
 748
 749   // Calling the auto-generated decoder function.
 750   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 751                              this, STI);
 752   if (Result != MCDisassembler::Fail) {
 753     Size = 4;
 754     return Result;
 755   }
 756
 757   return MCDisassembler::Fail;
 758 }
 759
 760 DecodeStatus
 761 Mips64Disassembler::getInstruction(MCInst &instr,
 762                                    uint64_t &Size,
 763                                    const MemoryObject &Region,
 764                                    uint64_t Address,
 765                                    raw_ostream &vStream,
 766                                    raw_ostream &cStream) const {
 767   uint32_t Insn;
 768
 769   DecodeStatus Result = readInstruction32(Region, Address, Size,
 770                                           Insn, isBigEndian, false);
 771   if (Result == MCDisassembler::Fail)
 772     return MCDisassembler::Fail;
 773
 774   // Calling the auto-generated decoder function.
 775   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 776                              this, STI);
 777   if (Result != MCDisassembler::Fail) {
 778     Size = 4;
 779     return Result;
 780   }
 781   // If we fail to decode in Mips64 decoder space we can try in Mips32
 782   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 783                              this, STI);
 784   if (Result != MCDisassembler::Fail) {
 785     Size = 4;
 786     return Result;
 787   }
 788
 789   return MCDisassembler::Fail;
 790 }
 791
 792 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 793                                                  unsigned RegNo,
 794                                                  uint64_t Address,
 795                                                  const void *Decoder) {
 796
 797   return MCDisassembler::Fail;
 798
 799 }
 800
 801 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 802                                              unsigned RegNo,
 803                                              uint64_t Address,
 804                                              const void *Decoder) {
 805
 806   if (RegNo > 31)
 807     return MCDisassembler::Fail;
 808
 809   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 810   Inst.addOperand(MCOperand::CreateReg(Reg));
 811   return MCDisassembler::Success;
 812 }
 813
 814 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 815                                              unsigned RegNo,
 816                                              uint64_t Address,
 817                                              const void *Decoder) {
 818   if (RegNo > 31)
 819     return MCDisassembler::Fail;
 820   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 821   Inst.addOperand(MCOperand::CreateReg(Reg));
 822   return MCDisassembler::Success;
 823 }
 824
 825 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 826                                            unsigned RegNo,
 827                                            uint64_t Address,
 828                                            const void *Decoder) {
 829   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 830     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 831
 832   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 833 }
 834
 835 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 836                                             unsigned RegNo,
 837                                             uint64_t Address,
 838                                             const void *Decoder) {
 839   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 840 }
 841
 842 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 843                                              unsigned RegNo,
 844                                              uint64_t Address,
 845                                              const void *Decoder) {
 846   if (RegNo > 31)
 847     return MCDisassembler::Fail;
 848
 849   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 850   Inst.addOperand(MCOperand::CreateReg(Reg));
 851   return MCDisassembler::Success;
 852 }
 853
 854 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 855                                              unsigned RegNo,
 856                                              uint64_t Address,
 857                                              const void *Decoder) {
 858   if (RegNo > 31)
 859     return MCDisassembler::Fail;
 860
 861   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 862   Inst.addOperand(MCOperand::CreateReg(Reg));
 863   return MCDisassembler::Success;
 864 }
 865
 866 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 867                                               unsigned RegNo,
 868                                               uint64_t Address,
 869                                               const void *Decoder) {
 870   if (RegNo > 31)
 871     return MCDisassembler::Fail;
 872
 873   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 874   Inst.addOperand(MCOperand::CreateReg(Reg));
 875   return MCDisassembler::Success;
 876 }
 877
 878 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 879                                            unsigned RegNo,
 880                                            uint64_t Address,
 881                                            const void *Decoder) {
 882   if (RegNo > 31)
 883     return MCDisassembler::Fail;
 884   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 885   Inst.addOperand(MCOperand::CreateReg(Reg));
 886   return MCDisassembler::Success;
 887 }
 888
 889 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 890                                            unsigned RegNo,
 891                                            uint64_t Address,
 892                                            const void *Decoder) {
 893   if (RegNo > 7)
 894     return MCDisassembler::Fail;
 895   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 896   Inst.addOperand(MCOperand::CreateReg(Reg));
 897   return MCDisassembler::Success;
 898 }
 899
 900 static DecodeStatus DecodeMem(MCInst &Inst,
 901                               unsigned Insn,
 902                               uint64_t Address,
 903                               const void *Decoder) {
 904   int Offset = SignExtend32<16>(Insn & 0xffff);
 905   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 906   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 907
 908   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 909   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 910
 911   if(Inst.getOpcode() == Mips::SC){
 912     Inst.addOperand(MCOperand::CreateReg(Reg));
 913   }
 914
 915   Inst.addOperand(MCOperand::CreateReg(Reg));
 916   Inst.addOperand(MCOperand::CreateReg(Base));
 917   Inst.addOperand(MCOperand::CreateImm(Offset));
 918
 919   return MCDisassembler::Success;
 920 }
 921
 922 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 923                                     uint64_t Address, const void *Decoder) {
 924   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 925   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 926   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 927
 928   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 929   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 930
 931   Inst.addOperand(MCOperand::CreateReg(Reg));
 932   Inst.addOperand(MCOperand::CreateReg(Base));
 933
 934   // The immediate field of an LD/ST instruction is scaled which means it must
 935   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 936   // data format.
 937   // .b - 1 byte
 938   // .h - 2 bytes
 939   // .w - 4 bytes
 940   // .d - 8 bytes
 941   switch(Inst.getOpcode())
 942   {
 943   default:
 944     assert (0 && "Unexpected instruction");
 945     return MCDisassembler::Fail;
 946     break;
 947   case Mips::LD_B:
 948   case Mips::ST_B:
 949     Inst.addOperand(MCOperand::CreateImm(Offset));
 950     break;
 951   case Mips::LD_H:
 952   case Mips::ST_H:
 953     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 954     break;
 955   case Mips::LD_W:
 956   case Mips::ST_W:
 957     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 958     break;
 959   case Mips::LD_D:
 960   case Mips::ST_D:
 961     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 962     break;
 963   }
 964
 965   return MCDisassembler::Success;
 966 }
 967
 968 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 969                                      unsigned Insn,
 970                                      uint64_t Address,
 971                                      const void *Decoder) {
 972   int Offset = SignExtend32<12>(Insn & 0x0fff);
 973   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 974   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 975
 976   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 977   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 978
 979   if (Inst.getOpcode() == Mips::SC_MM)
 980     Inst.addOperand(MCOperand::CreateReg(Reg));
 981
 982   Inst.addOperand(MCOperand::CreateReg(Reg));
 983   Inst.addOperand(MCOperand::CreateReg(Base));
 984   Inst.addOperand(MCOperand::CreateImm(Offset));
 985
 986   return MCDisassembler::Success;
 987 }
 988
 989 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 990                                      unsigned Insn,
 991                                      uint64_t Address,
 992                                      const void *Decoder) {
 993   int Offset = SignExtend32<16>(Insn & 0xffff);
 994   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 995   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 996
 997   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 998   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 999
1000   Inst.addOperand(MCOperand::CreateReg(Reg));
1001   Inst.addOperand(MCOperand::CreateReg(Base));
1002   Inst.addOperand(MCOperand::CreateImm(Offset));
1003
1004   return MCDisassembler::Success;
1005 }
1006
1007 static DecodeStatus DecodeFMem(MCInst &Inst,
1008                                unsigned Insn,
1009                                uint64_t Address,
1010                                const void *Decoder) {
1011   int Offset = SignExtend32<16>(Insn & 0xffff);
1012   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1013   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1014
1015   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1016   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1017
1018   Inst.addOperand(MCOperand::CreateReg(Reg));
1019   Inst.addOperand(MCOperand::CreateReg(Base));
1020   Inst.addOperand(MCOperand::CreateImm(Offset));
1021
1022   return MCDisassembler::Success;
1023 }
1024
1025
1026 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1027                                               unsigned RegNo,
1028                                               uint64_t Address,
1029                                               const void *Decoder) {
1030   // Currently only hardware register 29 is supported.
1031   if (RegNo != 29)
1032     return  MCDisassembler::Fail;
1033   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1034   return MCDisassembler::Success;
1035 }
1036
1037 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1038                                               unsigned RegNo,
1039                                               uint64_t Address,
1040                                               const void *Decoder) {
1041   if (RegNo > 30 || RegNo %2)
1042     return MCDisassembler::Fail;
1043
1044   ;
1045   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1046   Inst.addOperand(MCOperand::CreateReg(Reg));
1047   return MCDisassembler::Success;
1048 }
1049
1050 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1051                                                 unsigned RegNo,
1052                                                 uint64_t Address,
1053                                                 const void *Decoder) {
1054   if (RegNo >= 4)
1055     return MCDisassembler::Fail;
1056
1057   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1058   Inst.addOperand(MCOperand::CreateReg(Reg));
1059   return MCDisassembler::Success;
1060 }
1061
1062 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1063                                                unsigned RegNo,
1064                                                uint64_t Address,
1065                                                const void *Decoder) {
1066   if (RegNo >= 4)
1067     return MCDisassembler::Fail;
1068
1069   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1070   Inst.addOperand(MCOperand::CreateReg(Reg));
1071   return MCDisassembler::Success;
1072 }
1073
1074 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1075                                                unsigned RegNo,
1076                                                uint64_t Address,
1077                                                const void *Decoder) {
1078   if (RegNo >= 4)
1079     return MCDisassembler::Fail;
1080
1081   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1082   Inst.addOperand(MCOperand::CreateReg(Reg));
1083   return MCDisassembler::Success;
1084 }
1085
1086 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1087                                                unsigned RegNo,
1088                                                uint64_t Address,
1089                                                const void *Decoder) {
1090   if (RegNo > 31)
1091     return MCDisassembler::Fail;
1092
1093   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1094   Inst.addOperand(MCOperand::CreateReg(Reg));
1095   return MCDisassembler::Success;
1096 }
1097
1098 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1099                                                unsigned RegNo,
1100                                                uint64_t Address,
1101                                                const void *Decoder) {
1102   if (RegNo > 31)
1103     return MCDisassembler::Fail;
1104
1105   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1106   Inst.addOperand(MCOperand::CreateReg(Reg));
1107   return MCDisassembler::Success;
1108 }
1109
1110 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1111                                                unsigned RegNo,
1112                                                uint64_t Address,
1113                                                const void *Decoder) {
1114   if (RegNo > 31)
1115     return MCDisassembler::Fail;
1116
1117   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1118   Inst.addOperand(MCOperand::CreateReg(Reg));
1119   return MCDisassembler::Success;
1120 }
1121
1122 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1123                                                unsigned RegNo,
1124                                                uint64_t Address,
1125                                                const void *Decoder) {
1126   if (RegNo > 31)
1127     return MCDisassembler::Fail;
1128
1129   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1130   Inst.addOperand(MCOperand::CreateReg(Reg));
1131   return MCDisassembler::Success;
1132 }
1133
1134 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1135                                                unsigned RegNo,
1136                                                uint64_t Address,
1137                                                const void *Decoder) {
1138   if (RegNo > 7)
1139     return MCDisassembler::Fail;
1140
1141   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1142   Inst.addOperand(MCOperand::CreateReg(Reg));
1143   return MCDisassembler::Success;
1144 }
1145
1146 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1147                                             unsigned RegNo,
1148                                             uint64_t Address,
1149                                             const void *Decoder) {
1150   if (RegNo > 31)
1151     return MCDisassembler::Fail;
1152
1153   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1154   Inst.addOperand(MCOperand::CreateReg(Reg));
1155   return MCDisassembler::Success;
1156 }
1157
1158 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1159                                        unsigned Offset,
1160                                        uint64_t Address,
1161                                        const void *Decoder) {
1162   int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4;
1163   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1164   return MCDisassembler::Success;
1165 }
1166
1167 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1168                                      unsigned Insn,
1169                                      uint64_t Address,
1170                                      const void *Decoder) {
1171
1172   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1173   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1174   return MCDisassembler::Success;
1175 }
1176
1177 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1178                                          unsigned Offset,
1179                                          uint64_t Address,
1180                                          const void *Decoder) {
1181   int32_t BranchOffset = SignExtend32<21>(Offset) << 2;
1182
1183   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1184   return MCDisassembler::Success;
1185 }
1186
1187 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1188                                          unsigned Offset,
1189                                          uint64_t Address,
1190                                          const void *Decoder) {
1191   int32_t BranchOffset = SignExtend32<26>(Offset) << 2;
1192
1193   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1194   return MCDisassembler::Success;
1195 }
1196
1197 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1198                                          unsigned Offset,
1199                                          uint64_t Address,
1200                                          const void *Decoder) {
1201   int32_t BranchOffset = SignExtend32<16>(Offset) << 1;
1202   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1203   return MCDisassembler::Success;
1204 }
1205
1206 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1207                                        unsigned Insn,
1208                                        uint64_t Address,
1209                                        const void *Decoder) {
1210   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1211   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1212   return MCDisassembler::Success;
1213 }
1214
1215 static DecodeStatus DecodeSimm16(MCInst &Inst,
1216                                  unsigned Insn,
1217                                  uint64_t Address,
1218                                  const void *Decoder) {
1219   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1220   return MCDisassembler::Success;
1221 }
1222
1223 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1224                                  unsigned Insn,
1225                                  uint64_t Address,
1226                                  const void *Decoder) {
1227   // We add one to the immediate field as it was encoded as 'imm - 1'.
1228   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1229   return MCDisassembler::Success;
1230 }
1231
1232 static DecodeStatus DecodeInsSize(MCInst &Inst,
1233                                   unsigned Insn,
1234                                   uint64_t Address,
1235                                   const void *Decoder) {
1236   // First we need to grab the pos(lsb) from MCInst.
1237   int Pos = Inst.getOperand(2).getImm();
1238   int Size = (int) Insn - Pos + 1;
1239   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1240   return MCDisassembler::Success;
1241 }
1242
1243 static DecodeStatus DecodeExtSize(MCInst &Inst,
1244                                   unsigned Insn,
1245                                   uint64_t Address,
1246                                   const void *Decoder) {
1247   int Size = (int) Insn  + 1;
1248   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1249   return MCDisassembler::Success;
1250 }
1251
1252 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1253                                      uint64_t Address, const void *Decoder) {
1254   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
1255   return MCDisassembler::Success;
1256 }
1257
1258 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1259                                      uint64_t Address, const void *Decoder) {
1260   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3));
1261   return MCDisassembler::Success;
1262 }