lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// MipsDisassemblerBase - a disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   /// Constructor     - Initializes the disassembler.
  38   ///
  39   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  40                        bool bigEndian) :
  41     MCDisassembler(STI, Ctx),
  42     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  43
  44   virtual ~MipsDisassemblerBase() {}
  45
  46   bool isN64() const { return IsN64; }
  47
  48 private:
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Ctx, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   DecodeStatus getInstruction(MCInst &instr,
  68                               uint64_t &size,
  69                               const MemoryObject &region,
  70                               uint64_t address,
  71                               raw_ostream &vStream,
  72                               raw_ostream &cStream) const override;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   DecodeStatus getInstruction(MCInst &instr,
  87                               uint64_t &size,
  88                               const MemoryObject &region,
  89                               uint64_t address,
  90                               raw_ostream &vStream,
  91                               raw_ostream &cStream) const override;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 209 // shifted left by 1 bit.
 210 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 211                                          unsigned Offset,
 212                                          uint64_t Address,
 213                                          const void *Decoder);
 214
 215 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 216 // shifted left by 1 bit.
 217 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 218                                        unsigned Insn,
 219                                        uint64_t Address,
 220                                        const void *Decoder);
 221
 222 static DecodeStatus DecodeMem(MCInst &Inst,
 223                               unsigned Insn,
 224                               uint64_t Address,
 225                               const void *Decoder);
 226
 227 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 228                                     uint64_t Address, const void *Decoder);
 229
 230 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 231                                      unsigned Insn,
 232                                      uint64_t Address,
 233                                      const void *Decoder);
 234
 235 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 236                                      unsigned Insn,
 237                                      uint64_t Address,
 238                                      const void *Decoder);
 239
 240 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 241                                uint64_t Address,
 242                                const void *Decoder);
 243
 244 static DecodeStatus DecodeSimm16(MCInst &Inst,
 245                                  unsigned Insn,
 246                                  uint64_t Address,
 247                                  const void *Decoder);
 248
 249 // Decode the immediate field of an LSA instruction which
 250 // is off by one.
 251 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 252                                  unsigned Insn,
 253                                  uint64_t Address,
 254                                  const void *Decoder);
 255
 256 static DecodeStatus DecodeInsSize(MCInst &Inst,
 257                                   unsigned Insn,
 258                                   uint64_t Address,
 259                                   const void *Decoder);
 260
 261 static DecodeStatus DecodeExtSize(MCInst &Inst,
 262                                   unsigned Insn,
 263                                   uint64_t Address,
 264                                   const void *Decoder);
 265
 266 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 267                                      uint64_t Address, const void *Decoder);
 268
 269 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 270 /// handle.
 271 template <typename InsnType>
 272 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 273                                    const void *Decoder);
 274 namespace llvm {
 275 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 276               TheMips64elTarget;
 277 }
 278
 279 static MCDisassembler *createMipsDisassembler(
 280                        const Target &T,
 281                        const MCSubtargetInfo &STI,
 282                        MCContext &Ctx) {
 283   return new MipsDisassembler(STI, Ctx, true);
 284 }
 285
 286 static MCDisassembler *createMipselDisassembler(
 287                        const Target &T,
 288                        const MCSubtargetInfo &STI,
 289                        MCContext &Ctx) {
 290   return new MipsDisassembler(STI, Ctx, false);
 291 }
 292
 293 static MCDisassembler *createMips64Disassembler(
 294                        const Target &T,
 295                        const MCSubtargetInfo &STI,
 296                        MCContext &Ctx) {
 297   return new Mips64Disassembler(STI, Ctx, true);
 298 }
 299
 300 static MCDisassembler *createMips64elDisassembler(
 301                        const Target &T,
 302                        const MCSubtargetInfo &STI,
 303                        MCContext &Ctx) {
 304   return new Mips64Disassembler(STI, Ctx, false);
 305 }
 306
 307 extern "C" void LLVMInitializeMipsDisassembler() {
 308   // Register the disassembler.
 309   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 310                                          createMipsDisassembler);
 311   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 312                                          createMipselDisassembler);
 313   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 314                                          createMips64Disassembler);
 315   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 316                                          createMips64elDisassembler);
 317 }
 318
 319 #include "MipsGenDisassemblerTables.inc"
 320
 321 template <typename InsnType>
 322 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 323                                    const void *Decoder) {
 324   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 325   // The size of the n field depends on the element size
 326   // The register class also depends on this.
 327   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 328   unsigned NSize = 0;
 329   DecodeFN RegDecoder = nullptr;
 330   if ((tmp & 0x18) == 0x00) { // INSVE_B
 331     NSize = 4;
 332     RegDecoder = DecodeMSA128BRegisterClass;
 333   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 334     NSize = 3;
 335     RegDecoder = DecodeMSA128HRegisterClass;
 336   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 337     NSize = 2;
 338     RegDecoder = DecodeMSA128WRegisterClass;
 339   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 340     NSize = 1;
 341     RegDecoder = DecodeMSA128DRegisterClass;
 342   } else
 343     llvm_unreachable("Invalid encoding");
 344
 345   assert(NSize != 0 && RegDecoder != nullptr);
 346
 347   // $wd
 348   tmp = fieldFromInstruction(insn, 6, 5);
 349   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 350     return MCDisassembler::Fail;
 351   // $wd_in
 352   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 353     return MCDisassembler::Fail;
 354   // $n
 355   tmp = fieldFromInstruction(insn, 16, NSize);
 356   MI.addOperand(MCOperand::CreateImm(tmp));
 357   // $ws
 358   tmp = fieldFromInstruction(insn, 11, 5);
 359   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 360     return MCDisassembler::Fail;
 361   // $n2
 362   MI.addOperand(MCOperand::CreateImm(0));
 363
 364   return MCDisassembler::Success;
 365 }
 366
 367   /// readInstruction - read four bytes from the MemoryObject
 368   /// and return 32 bit word sorted according to the given endianess
 369 static DecodeStatus readInstruction32(const MemoryObject &region,
 370                                       uint64_t address,
 371                                       uint64_t &size,
 372                                       uint32_t &insn,
 373                                       bool isBigEndian,
 374                                       bool IsMicroMips) {
 375   uint8_t Bytes[4];
 376
 377   // We want to read exactly 4 Bytes of data.
 378   if (region.readBytes(address, 4, Bytes) == -1) {
 379     size = 0;
 380     return MCDisassembler::Fail;
 381   }
 382
 383   if (isBigEndian) {
 384     // Encoded as a big-endian 32-bit word in the stream.
 385     insn = (Bytes[3] <<  0) |
 386            (Bytes[2] <<  8) |
 387            (Bytes[1] << 16) |
 388            (Bytes[0] << 24);
 389   }
 390   else {
 391     // Encoded as a small-endian 32-bit word in the stream.
 392     // Little-endian byte ordering:
 393     //   mips32r2:   4 | 3 | 2 | 1
 394     //   microMIPS:  2 | 1 | 4 | 3
 395     if (IsMicroMips) {
 396       insn = (Bytes[2] <<  0) |
 397              (Bytes[3] <<  8) |
 398              (Bytes[0] << 16) |
 399              (Bytes[1] << 24);
 400     } else {
 401       insn = (Bytes[0] <<  0) |
 402              (Bytes[1] <<  8) |
 403              (Bytes[2] << 16) |
 404              (Bytes[3] << 24);
 405     }
 406   }
 407
 408   return MCDisassembler::Success;
 409 }
 410
 411 DecodeStatus
 412 MipsDisassembler::getInstruction(MCInst &instr,
 413                                  uint64_t &Size,
 414                                  const MemoryObject &Region,
 415                                  uint64_t Address,
 416                                  raw_ostream &vStream,
 417                                  raw_ostream &cStream) const {
 418   uint32_t Insn;
 419
 420   DecodeStatus Result = readInstruction32(Region, Address, Size,
 421                                           Insn, isBigEndian, IsMicroMips);
 422   if (Result == MCDisassembler::Fail)
 423     return MCDisassembler::Fail;
 424
 425   if (IsMicroMips) {
 426     // Calling the auto-generated decoder function.
 427     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 428                                this, STI);
 429     if (Result != MCDisassembler::Fail) {
 430       Size = 4;
 431       return Result;
 432     }
 433     return MCDisassembler::Fail;
 434   }
 435
 436   // Calling the auto-generated decoder function.
 437   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 438                              this, STI);
 439   if (Result != MCDisassembler::Fail) {
 440     Size = 4;
 441     return Result;
 442   }
 443
 444   return MCDisassembler::Fail;
 445 }
 446
 447 DecodeStatus
 448 Mips64Disassembler::getInstruction(MCInst &instr,
 449                                    uint64_t &Size,
 450                                    const MemoryObject &Region,
 451                                    uint64_t Address,
 452                                    raw_ostream &vStream,
 453                                    raw_ostream &cStream) const {
 454   uint32_t Insn;
 455
 456   DecodeStatus Result = readInstruction32(Region, Address, Size,
 457                                           Insn, isBigEndian, false);
 458   if (Result == MCDisassembler::Fail)
 459     return MCDisassembler::Fail;
 460
 461   // Calling the auto-generated decoder function.
 462   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 463                              this, STI);
 464   if (Result != MCDisassembler::Fail) {
 465     Size = 4;
 466     return Result;
 467   }
 468   // If we fail to decode in Mips64 decoder space we can try in Mips32
 469   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 470                              this, STI);
 471   if (Result != MCDisassembler::Fail) {
 472     Size = 4;
 473     return Result;
 474   }
 475
 476   return MCDisassembler::Fail;
 477 }
 478
 479 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 480   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 481   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 482   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 483 }
 484
 485 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 486                                                  unsigned RegNo,
 487                                                  uint64_t Address,
 488                                                  const void *Decoder) {
 489
 490   return MCDisassembler::Fail;
 491
 492 }
 493
 494 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 495                                              unsigned RegNo,
 496                                              uint64_t Address,
 497                                              const void *Decoder) {
 498
 499   if (RegNo > 31)
 500     return MCDisassembler::Fail;
 501
 502   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 503   Inst.addOperand(MCOperand::CreateReg(Reg));
 504   return MCDisassembler::Success;
 505 }
 506
 507 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 508                                              unsigned RegNo,
 509                                              uint64_t Address,
 510                                              const void *Decoder) {
 511   if (RegNo > 31)
 512     return MCDisassembler::Fail;
 513   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 514   Inst.addOperand(MCOperand::CreateReg(Reg));
 515   return MCDisassembler::Success;
 516 }
 517
 518 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 519                                            unsigned RegNo,
 520                                            uint64_t Address,
 521                                            const void *Decoder) {
 522   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 523     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 524
 525   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 526 }
 527
 528 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 529                                             unsigned RegNo,
 530                                             uint64_t Address,
 531                                             const void *Decoder) {
 532   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 533 }
 534
 535 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 536                                              unsigned RegNo,
 537                                              uint64_t Address,
 538                                              const void *Decoder) {
 539   if (RegNo > 31)
 540     return MCDisassembler::Fail;
 541
 542   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 543   Inst.addOperand(MCOperand::CreateReg(Reg));
 544   return MCDisassembler::Success;
 545 }
 546
 547 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 548                                              unsigned RegNo,
 549                                              uint64_t Address,
 550                                              const void *Decoder) {
 551   if (RegNo > 31)
 552     return MCDisassembler::Fail;
 553
 554   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 555   Inst.addOperand(MCOperand::CreateReg(Reg));
 556   return MCDisassembler::Success;
 557 }
 558
 559 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 560                                               unsigned RegNo,
 561                                               uint64_t Address,
 562                                               const void *Decoder) {
 563   if (RegNo > 31)
 564     return MCDisassembler::Fail;
 565
 566   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 567   Inst.addOperand(MCOperand::CreateReg(Reg));
 568   return MCDisassembler::Success;
 569 }
 570
 571 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 572                                            unsigned RegNo,
 573                                            uint64_t Address,
 574                                            const void *Decoder) {
 575   if (RegNo > 31)
 576     return MCDisassembler::Fail;
 577   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 578   Inst.addOperand(MCOperand::CreateReg(Reg));
 579   return MCDisassembler::Success;
 580 }
 581
 582 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 583                                            unsigned RegNo,
 584                                            uint64_t Address,
 585                                            const void *Decoder) {
 586   if (RegNo > 7)
 587     return MCDisassembler::Fail;
 588   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 589   Inst.addOperand(MCOperand::CreateReg(Reg));
 590   return MCDisassembler::Success;
 591 }
 592
 593 static DecodeStatus DecodeMem(MCInst &Inst,
 594                               unsigned Insn,
 595                               uint64_t Address,
 596                               const void *Decoder) {
 597   int Offset = SignExtend32<16>(Insn & 0xffff);
 598   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 599   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 600
 601   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 602   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 603
 604   if(Inst.getOpcode() == Mips::SC){
 605     Inst.addOperand(MCOperand::CreateReg(Reg));
 606   }
 607
 608   Inst.addOperand(MCOperand::CreateReg(Reg));
 609   Inst.addOperand(MCOperand::CreateReg(Base));
 610   Inst.addOperand(MCOperand::CreateImm(Offset));
 611
 612   return MCDisassembler::Success;
 613 }
 614
 615 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 616                                     uint64_t Address, const void *Decoder) {
 617   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 618   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 619   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 620
 621   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 622   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 623
 624   Inst.addOperand(MCOperand::CreateReg(Reg));
 625   Inst.addOperand(MCOperand::CreateReg(Base));
 626
 627   // The immediate field of an LD/ST instruction is scaled which means it must
 628   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 629   // data format.
 630   // .b - 1 byte
 631   // .h - 2 bytes
 632   // .w - 4 bytes
 633   // .d - 8 bytes
 634   switch(Inst.getOpcode())
 635   {
 636   default:
 637     assert (0 && "Unexpected instruction");
 638     return MCDisassembler::Fail;
 639     break;
 640   case Mips::LD_B:
 641   case Mips::ST_B:
 642     Inst.addOperand(MCOperand::CreateImm(Offset));
 643     break;
 644   case Mips::LD_H:
 645   case Mips::ST_H:
 646     Inst.addOperand(MCOperand::CreateImm(Offset << 1));
 647     break;
 648   case Mips::LD_W:
 649   case Mips::ST_W:
 650     Inst.addOperand(MCOperand::CreateImm(Offset << 2));
 651     break;
 652   case Mips::LD_D:
 653   case Mips::ST_D:
 654     Inst.addOperand(MCOperand::CreateImm(Offset << 3));
 655     break;
 656   }
 657
 658   return MCDisassembler::Success;
 659 }
 660
 661 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 662                                      unsigned Insn,
 663                                      uint64_t Address,
 664                                      const void *Decoder) {
 665   int Offset = SignExtend32<12>(Insn & 0x0fff);
 666   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 667   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 668
 669   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 670   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 671
 672   if (Inst.getOpcode() == Mips::SC_MM)
 673     Inst.addOperand(MCOperand::CreateReg(Reg));
 674
 675   Inst.addOperand(MCOperand::CreateReg(Reg));
 676   Inst.addOperand(MCOperand::CreateReg(Base));
 677   Inst.addOperand(MCOperand::CreateImm(Offset));
 678
 679   return MCDisassembler::Success;
 680 }
 681
 682 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 683                                      unsigned Insn,
 684                                      uint64_t Address,
 685                                      const void *Decoder) {
 686   int Offset = SignExtend32<16>(Insn & 0xffff);
 687   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 688   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 689
 690   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 691   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 692
 693   Inst.addOperand(MCOperand::CreateReg(Reg));
 694   Inst.addOperand(MCOperand::CreateReg(Base));
 695   Inst.addOperand(MCOperand::CreateImm(Offset));
 696
 697   return MCDisassembler::Success;
 698 }
 699
 700 static DecodeStatus DecodeFMem(MCInst &Inst,
 701                                unsigned Insn,
 702                                uint64_t Address,
 703                                const void *Decoder) {
 704   int Offset = SignExtend32<16>(Insn & 0xffff);
 705   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 706   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 707
 708   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 709   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 710
 711   Inst.addOperand(MCOperand::CreateReg(Reg));
 712   Inst.addOperand(MCOperand::CreateReg(Base));
 713   Inst.addOperand(MCOperand::CreateImm(Offset));
 714
 715   return MCDisassembler::Success;
 716 }
 717
 718
 719 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 720                                               unsigned RegNo,
 721                                               uint64_t Address,
 722                                               const void *Decoder) {
 723   // Currently only hardware register 29 is supported.
 724   if (RegNo != 29)
 725     return  MCDisassembler::Fail;
 726   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 727   return MCDisassembler::Success;
 728 }
 729
 730 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 731                                               unsigned RegNo,
 732                                               uint64_t Address,
 733                                               const void *Decoder) {
 734   if (RegNo > 30 || RegNo %2)
 735     return MCDisassembler::Fail;
 736
 737   ;
 738   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 739   Inst.addOperand(MCOperand::CreateReg(Reg));
 740   return MCDisassembler::Success;
 741 }
 742
 743 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 744                                                 unsigned RegNo,
 745                                                 uint64_t Address,
 746                                                 const void *Decoder) {
 747   if (RegNo >= 4)
 748     return MCDisassembler::Fail;
 749
 750   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 751   Inst.addOperand(MCOperand::CreateReg(Reg));
 752   return MCDisassembler::Success;
 753 }
 754
 755 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 756                                                unsigned RegNo,
 757                                                uint64_t Address,
 758                                                const void *Decoder) {
 759   if (RegNo >= 4)
 760     return MCDisassembler::Fail;
 761
 762   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 763   Inst.addOperand(MCOperand::CreateReg(Reg));
 764   return MCDisassembler::Success;
 765 }
 766
 767 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 768                                                unsigned RegNo,
 769                                                uint64_t Address,
 770                                                const void *Decoder) {
 771   if (RegNo >= 4)
 772     return MCDisassembler::Fail;
 773
 774   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 775   Inst.addOperand(MCOperand::CreateReg(Reg));
 776   return MCDisassembler::Success;
 777 }
 778
 779 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 780                                                unsigned RegNo,
 781                                                uint64_t Address,
 782                                                const void *Decoder) {
 783   if (RegNo > 31)
 784     return MCDisassembler::Fail;
 785
 786   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 787   Inst.addOperand(MCOperand::CreateReg(Reg));
 788   return MCDisassembler::Success;
 789 }
 790
 791 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 792                                                unsigned RegNo,
 793                                                uint64_t Address,
 794                                                const void *Decoder) {
 795   if (RegNo > 31)
 796     return MCDisassembler::Fail;
 797
 798   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 799   Inst.addOperand(MCOperand::CreateReg(Reg));
 800   return MCDisassembler::Success;
 801 }
 802
 803 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 804                                                unsigned RegNo,
 805                                                uint64_t Address,
 806                                                const void *Decoder) {
 807   if (RegNo > 31)
 808     return MCDisassembler::Fail;
 809
 810   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 811   Inst.addOperand(MCOperand::CreateReg(Reg));
 812   return MCDisassembler::Success;
 813 }
 814
 815 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 816                                                unsigned RegNo,
 817                                                uint64_t Address,
 818                                                const void *Decoder) {
 819   if (RegNo > 31)
 820     return MCDisassembler::Fail;
 821
 822   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 823   Inst.addOperand(MCOperand::CreateReg(Reg));
 824   return MCDisassembler::Success;
 825 }
 826
 827 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 828                                                unsigned RegNo,
 829                                                uint64_t Address,
 830                                                const void *Decoder) {
 831   if (RegNo > 7)
 832     return MCDisassembler::Fail;
 833
 834   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 835   Inst.addOperand(MCOperand::CreateReg(Reg));
 836   return MCDisassembler::Success;
 837 }
 838
 839 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 840                                        unsigned Offset,
 841                                        uint64_t Address,
 842                                        const void *Decoder) {
 843   unsigned BranchOffset = Offset & 0xffff;
 844   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 845   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 846   return MCDisassembler::Success;
 847 }
 848
 849 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 850                                      unsigned Insn,
 851                                      uint64_t Address,
 852                                      const void *Decoder) {
 853
 854   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 855   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 856   return MCDisassembler::Success;
 857 }
 858
 859 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 860                                          unsigned Offset,
 861                                          uint64_t Address,
 862                                          const void *Decoder) {
 863   unsigned BranchOffset = Offset & 0xffff;
 864   BranchOffset = SignExtend32<18>(BranchOffset << 1);
 865   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 866   return MCDisassembler::Success;
 867 }
 868
 869 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 870                                        unsigned Insn,
 871                                        uint64_t Address,
 872                                        const void *Decoder) {
 873   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
 874   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 875   return MCDisassembler::Success;
 876 }
 877
 878 static DecodeStatus DecodeSimm16(MCInst &Inst,
 879                                  unsigned Insn,
 880                                  uint64_t Address,
 881                                  const void *Decoder) {
 882   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 883   return MCDisassembler::Success;
 884 }
 885
 886 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 887                                  unsigned Insn,
 888                                  uint64_t Address,
 889                                  const void *Decoder) {
 890   // We add one to the immediate field as it was encoded as 'imm - 1'.
 891   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
 892   return MCDisassembler::Success;
 893 }
 894
 895 static DecodeStatus DecodeInsSize(MCInst &Inst,
 896                                   unsigned Insn,
 897                                   uint64_t Address,
 898                                   const void *Decoder) {
 899   // First we need to grab the pos(lsb) from MCInst.
 900   int Pos = Inst.getOperand(2).getImm();
 901   int Size = (int) Insn - Pos + 1;
 902   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 903   return MCDisassembler::Success;
 904 }
 905
 906 static DecodeStatus DecodeExtSize(MCInst &Inst,
 907                                   unsigned Insn,
 908                                   uint64_t Address,
 909                                   const void *Decoder) {
 910   int Size = (int) Insn  + 1;
 911   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 912   return MCDisassembler::Success;
 913 }
 914
 915 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 916                                      uint64_t Address, const void *Decoder) {
 917   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2));
 918   return MCDisassembler::Success;
 919 }