lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MathExtras.h"
  22 #include "llvm/Support/MemoryObject.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 typedef MCDisassembler::DecodeStatus DecodeStatus;
  28
  29 namespace {
  30
  31 /// MipsDisassemblerBase - a disasembler class for Mips.
  32 class MipsDisassemblerBase : public MCDisassembler {
  33 public:
  34   /// Constructor     - Initializes the disassembler.
  35   ///
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  37                        bool bigEndian) :
  38     MCDisassembler(STI), RegInfo(Info),
  39     IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
  40
  41   virtual ~MipsDisassemblerBase() {}
  42
  43   const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   OwningPtr<const MCRegisterInfo> RegInfo;
  49   bool IsN64;
  50 protected:
  51   bool isBigEndian;
  52 };
  53
  54 /// MipsDisassembler - a disasembler class for Mips32.
  55 class MipsDisassembler : public MipsDisassemblerBase {
  56   bool IsMicroMips;
  57 public:
  58   /// Constructor     - Initializes the disassembler.
  59   ///
  60   MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  61                    bool bigEndian) :
  62     MipsDisassemblerBase(STI, Info, bigEndian) {
  63       IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  64     }
  65
  66   /// getInstruction - See MCDisassembler.
  67   virtual DecodeStatus getInstruction(MCInst &instr,
  68                                       uint64_t &size,
  69                                       const MemoryObject &region,
  70                                       uint64_t address,
  71                                       raw_ostream &vStream,
  72                                       raw_ostream &cStream) const;
  73 };
  74
  75
  76 /// Mips64Disassembler - a disasembler class for Mips64.
  77 class Mips64Disassembler : public MipsDisassemblerBase {
  78 public:
  79   /// Constructor     - Initializes the disassembler.
  80   ///
  81   Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
  82                      bool bigEndian) :
  83     MipsDisassemblerBase(STI, Info, bigEndian) {}
  84
  85   /// getInstruction - See MCDisassembler.
  86   virtual DecodeStatus getInstruction(MCInst &instr,
  87                                       uint64_t &size,
  88                                       const MemoryObject &region,
  89                                       uint64_t address,
  90                                       raw_ostream &vStream,
  91                                       raw_ostream &cStream) const;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 109                                              unsigned RegNo,
 110                                              uint64_t Address,
 111                                              const void *Decoder);
 112
 113 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 114                                            unsigned Insn,
 115                                            uint64_t Address,
 116                                            const void *Decoder);
 117
 118 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 119                                             unsigned RegNo,
 120                                             uint64_t Address,
 121                                             const void *Decoder);
 122
 123 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 124                                              unsigned RegNo,
 125                                              uint64_t Address,
 126                                              const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 134                                               unsigned RegNo,
 135                                               uint64_t Address,
 136                                               const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 149                                               unsigned Insn,
 150                                               uint64_t Address,
 151                                               const void *Decoder);
 152
 153 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 154                                               unsigned RegNo,
 155                                               uint64_t Address,
 156                                               const void *Decoder);
 157
 158 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 159                                                 unsigned RegNo,
 160                                                 uint64_t Address,
 161                                                 const void *Decoder);
 162
 163 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 164                                                unsigned RegNo,
 165                                                uint64_t Address,
 166                                                const void *Decoder);
 167
 168 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 169                                                unsigned RegNo,
 170                                                uint64_t Address,
 171                                                const void *Decoder);
 172
 173 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 174                                                unsigned RegNo,
 175                                                uint64_t Address,
 176                                                const void *Decoder);
 177
 178 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 179                                                unsigned RegNo,
 180                                                uint64_t Address,
 181                                                const void *Decoder);
 182
 183 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 184                                                unsigned RegNo,
 185                                                uint64_t Address,
 186                                                const void *Decoder);
 187
 188 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 189                                                unsigned RegNo,
 190                                                uint64_t Address,
 191                                                const void *Decoder);
 192
 193 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 194                                                unsigned RegNo,
 195                                                uint64_t Address,
 196                                                const void *Decoder);
 197
 198 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 199                                        unsigned Offset,
 200                                        uint64_t Address,
 201                                        const void *Decoder);
 202
 203 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 204                                      unsigned Insn,
 205                                      uint64_t Address,
 206                                      const void *Decoder);
 207
 208 static DecodeStatus DecodeMem(MCInst &Inst,
 209                               unsigned Insn,
 210                               uint64_t Address,
 211                               const void *Decoder);
 212
 213 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 214                                      unsigned Insn,
 215                                      uint64_t Address,
 216                                      const void *Decoder);
 217
 218 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 219                                      unsigned Insn,
 220                                      uint64_t Address,
 221                                      const void *Decoder);
 222
 223 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 224                                uint64_t Address,
 225                                const void *Decoder);
 226
 227 static DecodeStatus DecodeSimm16(MCInst &Inst,
 228                                  unsigned Insn,
 229                                  uint64_t Address,
 230                                  const void *Decoder);
 231
 232 static DecodeStatus DecodeInsSize(MCInst &Inst,
 233                                   unsigned Insn,
 234                                   uint64_t Address,
 235                                   const void *Decoder);
 236
 237 static DecodeStatus DecodeExtSize(MCInst &Inst,
 238                                   unsigned Insn,
 239                                   uint64_t Address,
 240                                   const void *Decoder);
 241
 242 namespace llvm {
 243 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 244               TheMips64elTarget;
 245 }
 246
 247 static MCDisassembler *createMipsDisassembler(
 248                        const Target &T,
 249                        const MCSubtargetInfo &STI) {
 250   return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
 251 }
 252
 253 static MCDisassembler *createMipselDisassembler(
 254                        const Target &T,
 255                        const MCSubtargetInfo &STI) {
 256   return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
 257 }
 258
 259 static MCDisassembler *createMips64Disassembler(
 260                        const Target &T,
 261                        const MCSubtargetInfo &STI) {
 262   return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
 263 }
 264
 265 static MCDisassembler *createMips64elDisassembler(
 266                        const Target &T,
 267                        const MCSubtargetInfo &STI) {
 268   return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
 269 }
 270
 271 extern "C" void LLVMInitializeMipsDisassembler() {
 272   // Register the disassembler.
 273   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 274                                          createMipsDisassembler);
 275   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 276                                          createMipselDisassembler);
 277   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 278                                          createMips64Disassembler);
 279   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 280                                          createMips64elDisassembler);
 281 }
 282
 283
 284 #include "MipsGenDisassemblerTables.inc"
 285
 286   /// readInstruction - read four bytes from the MemoryObject
 287   /// and return 32 bit word sorted according to the given endianess
 288 static DecodeStatus readInstruction32(const MemoryObject &region,
 289                                       uint64_t address,
 290                                       uint64_t &size,
 291                                       uint32_t &insn,
 292                                       bool isBigEndian,
 293                                       bool IsMicroMips) {
 294   uint8_t Bytes[4];
 295
 296   // We want to read exactly 4 Bytes of data.
 297   if (region.readBytes(address, 4, Bytes) == -1) {
 298     size = 0;
 299     return MCDisassembler::Fail;
 300   }
 301
 302   if (isBigEndian) {
 303     // Encoded as a big-endian 32-bit word in the stream.
 304     insn = (Bytes[3] <<  0) |
 305            (Bytes[2] <<  8) |
 306            (Bytes[1] << 16) |
 307            (Bytes[0] << 24);
 308   }
 309   else {
 310     // Encoded as a small-endian 32-bit word in the stream.
 311     // Little-endian byte ordering:
 312     //   mips32r2:   4 | 3 | 2 | 1
 313     //   microMIPS:  2 | 1 | 4 | 3
 314     if (IsMicroMips) {
 315       insn = (Bytes[2] <<  0) |
 316              (Bytes[3] <<  8) |
 317              (Bytes[0] << 16) |
 318              (Bytes[1] << 24);
 319     } else {
 320       insn = (Bytes[0] <<  0) |
 321              (Bytes[1] <<  8) |
 322              (Bytes[2] << 16) |
 323              (Bytes[3] << 24);
 324     }
 325   }
 326
 327   return MCDisassembler::Success;
 328 }
 329
 330 DecodeStatus
 331 MipsDisassembler::getInstruction(MCInst &instr,
 332                                  uint64_t &Size,
 333                                  const MemoryObject &Region,
 334                                  uint64_t Address,
 335                                  raw_ostream &vStream,
 336                                  raw_ostream &cStream) const {
 337   uint32_t Insn;
 338
 339   DecodeStatus Result = readInstruction32(Region, Address, Size,
 340                                           Insn, isBigEndian, IsMicroMips);
 341   if (Result == MCDisassembler::Fail)
 342     return MCDisassembler::Fail;
 343
 344   if (IsMicroMips) {
 345     // Calling the auto-generated decoder function.
 346     Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
 347                                this, STI);
 348     if (Result != MCDisassembler::Fail) {
 349       Size = 4;
 350       return Result;
 351     }
 352     return MCDisassembler::Fail;
 353   }
 354
 355   // Calling the auto-generated decoder function.
 356   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 357                              this, STI);
 358   if (Result != MCDisassembler::Fail) {
 359     Size = 4;
 360     return Result;
 361   }
 362
 363   return MCDisassembler::Fail;
 364 }
 365
 366 DecodeStatus
 367 Mips64Disassembler::getInstruction(MCInst &instr,
 368                                    uint64_t &Size,
 369                                    const MemoryObject &Region,
 370                                    uint64_t Address,
 371                                    raw_ostream &vStream,
 372                                    raw_ostream &cStream) const {
 373   uint32_t Insn;
 374
 375   DecodeStatus Result = readInstruction32(Region, Address, Size,
 376                                           Insn, isBigEndian, false);
 377   if (Result == MCDisassembler::Fail)
 378     return MCDisassembler::Fail;
 379
 380   // Calling the auto-generated decoder function.
 381   Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
 382                              this, STI);
 383   if (Result != MCDisassembler::Fail) {
 384     Size = 4;
 385     return Result;
 386   }
 387   // If we fail to decode in Mips64 decoder space we can try in Mips32
 388   Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
 389                              this, STI);
 390   if (Result != MCDisassembler::Fail) {
 391     Size = 4;
 392     return Result;
 393   }
 394
 395   return MCDisassembler::Fail;
 396 }
 397
 398 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 399   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 400   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 401 }
 402
 403 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 404                                                  unsigned RegNo,
 405                                                  uint64_t Address,
 406                                                  const void *Decoder) {
 407
 408   return MCDisassembler::Fail;
 409
 410 }
 411
 412 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 413                                              unsigned RegNo,
 414                                              uint64_t Address,
 415                                              const void *Decoder) {
 416
 417   if (RegNo > 31)
 418     return MCDisassembler::Fail;
 419
 420   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 421   Inst.addOperand(MCOperand::CreateReg(Reg));
 422   return MCDisassembler::Success;
 423 }
 424
 425 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 426                                              unsigned RegNo,
 427                                              uint64_t Address,
 428                                              const void *Decoder) {
 429   if (RegNo > 31)
 430     return MCDisassembler::Fail;
 431   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 432   Inst.addOperand(MCOperand::CreateReg(Reg));
 433   return MCDisassembler::Success;
 434 }
 435
 436 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 437                                            unsigned RegNo,
 438                                            uint64_t Address,
 439                                            const void *Decoder) {
 440   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 441     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 442
 443   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 444 }
 445
 446 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 447                                             unsigned RegNo,
 448                                             uint64_t Address,
 449                                             const void *Decoder) {
 450   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 451 }
 452
 453 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 454                                              unsigned RegNo,
 455                                              uint64_t Address,
 456                                              const void *Decoder) {
 457   if (RegNo > 31)
 458     return MCDisassembler::Fail;
 459
 460   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 461   Inst.addOperand(MCOperand::CreateReg(Reg));
 462   return MCDisassembler::Success;
 463 }
 464
 465 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 466                                              unsigned RegNo,
 467                                              uint64_t Address,
 468                                              const void *Decoder) {
 469   if (RegNo > 31)
 470     return MCDisassembler::Fail;
 471
 472   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 473   Inst.addOperand(MCOperand::CreateReg(Reg));
 474   return MCDisassembler::Success;
 475 }
 476
 477 static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
 478                                               unsigned RegNo,
 479                                               uint64_t Address,
 480                                               const void *Decoder) {
 481   if (RegNo > 31)
 482     return MCDisassembler::Fail;
 483
 484   unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
 485   Inst.addOperand(MCOperand::CreateReg(Reg));
 486   return MCDisassembler::Success;
 487 }
 488
 489 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 490                                            unsigned RegNo,
 491                                            uint64_t Address,
 492                                            const void *Decoder) {
 493   if (RegNo > 31)
 494     return MCDisassembler::Fail;
 495   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 496   Inst.addOperand(MCOperand::CreateReg(Reg));
 497   return MCDisassembler::Success;
 498 }
 499
 500 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 501                                            unsigned RegNo,
 502                                            uint64_t Address,
 503                                            const void *Decoder) {
 504   if (RegNo > 7)
 505     return MCDisassembler::Fail;
 506   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 507   Inst.addOperand(MCOperand::CreateReg(Reg));
 508   return MCDisassembler::Success;
 509 }
 510
 511 static DecodeStatus DecodeMem(MCInst &Inst,
 512                               unsigned Insn,
 513                               uint64_t Address,
 514                               const void *Decoder) {
 515   int Offset = SignExtend32<16>(Insn & 0xffff);
 516   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 517   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 518
 519   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 520   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 521
 522   if(Inst.getOpcode() == Mips::SC){
 523     Inst.addOperand(MCOperand::CreateReg(Reg));
 524   }
 525
 526   Inst.addOperand(MCOperand::CreateReg(Reg));
 527   Inst.addOperand(MCOperand::CreateReg(Base));
 528   Inst.addOperand(MCOperand::CreateImm(Offset));
 529
 530   return MCDisassembler::Success;
 531 }
 532
 533 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 534                                      unsigned Insn,
 535                                      uint64_t Address,
 536                                      const void *Decoder) {
 537   int Offset = SignExtend32<12>(Insn & 0x0fff);
 538   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 539   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 540
 541   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 542   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 543
 544   Inst.addOperand(MCOperand::CreateReg(Reg));
 545   Inst.addOperand(MCOperand::CreateReg(Base));
 546   Inst.addOperand(MCOperand::CreateImm(Offset));
 547
 548   return MCDisassembler::Success;
 549 }
 550
 551 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 552                                      unsigned Insn,
 553                                      uint64_t Address,
 554                                      const void *Decoder) {
 555   int Offset = SignExtend32<16>(Insn & 0xffff);
 556   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
 557   unsigned Base = fieldFromInstruction(Insn, 16, 5);
 558
 559   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 560   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 561
 562   Inst.addOperand(MCOperand::CreateReg(Reg));
 563   Inst.addOperand(MCOperand::CreateReg(Base));
 564   Inst.addOperand(MCOperand::CreateImm(Offset));
 565
 566   return MCDisassembler::Success;
 567 }
 568
 569 static DecodeStatus DecodeFMem(MCInst &Inst,
 570                                unsigned Insn,
 571                                uint64_t Address,
 572                                const void *Decoder) {
 573   int Offset = SignExtend32<16>(Insn & 0xffff);
 574   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 575   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 576
 577   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
 578   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 579
 580   Inst.addOperand(MCOperand::CreateReg(Reg));
 581   Inst.addOperand(MCOperand::CreateReg(Base));
 582   Inst.addOperand(MCOperand::CreateImm(Offset));
 583
 584   return MCDisassembler::Success;
 585 }
 586
 587
 588 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 589                                               unsigned RegNo,
 590                                               uint64_t Address,
 591                                               const void *Decoder) {
 592   // Currently only hardware register 29 is supported.
 593   if (RegNo != 29)
 594     return  MCDisassembler::Fail;
 595   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
 596   return MCDisassembler::Success;
 597 }
 598
 599 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 600                                               unsigned RegNo,
 601                                               uint64_t Address,
 602                                               const void *Decoder) {
 603   if (RegNo > 30 || RegNo %2)
 604     return MCDisassembler::Fail;
 605
 606   ;
 607   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
 608   Inst.addOperand(MCOperand::CreateReg(Reg));
 609   return MCDisassembler::Success;
 610 }
 611
 612 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 613                                                 unsigned RegNo,
 614                                                 uint64_t Address,
 615                                                 const void *Decoder) {
 616   if (RegNo >= 4)
 617     return MCDisassembler::Fail;
 618
 619   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
 620   Inst.addOperand(MCOperand::CreateReg(Reg));
 621   return MCDisassembler::Success;
 622 }
 623
 624 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 625                                                unsigned RegNo,
 626                                                uint64_t Address,
 627                                                const void *Decoder) {
 628   if (RegNo >= 4)
 629     return MCDisassembler::Fail;
 630
 631   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
 632   Inst.addOperand(MCOperand::CreateReg(Reg));
 633   return MCDisassembler::Success;
 634 }
 635
 636 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 637                                                unsigned RegNo,
 638                                                uint64_t Address,
 639                                                const void *Decoder) {
 640   if (RegNo >= 4)
 641     return MCDisassembler::Fail;
 642
 643   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
 644   Inst.addOperand(MCOperand::CreateReg(Reg));
 645   return MCDisassembler::Success;
 646 }
 647
 648 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 649                                                unsigned RegNo,
 650                                                uint64_t Address,
 651                                                const void *Decoder) {
 652   if (RegNo > 31)
 653     return MCDisassembler::Fail;
 654
 655   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
 656   Inst.addOperand(MCOperand::CreateReg(Reg));
 657   return MCDisassembler::Success;
 658 }
 659
 660 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 661                                                unsigned RegNo,
 662                                                uint64_t Address,
 663                                                const void *Decoder) {
 664   if (RegNo > 31)
 665     return MCDisassembler::Fail;
 666
 667   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
 668   Inst.addOperand(MCOperand::CreateReg(Reg));
 669   return MCDisassembler::Success;
 670 }
 671
 672 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 673                                                unsigned RegNo,
 674                                                uint64_t Address,
 675                                                const void *Decoder) {
 676   if (RegNo > 31)
 677     return MCDisassembler::Fail;
 678
 679   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
 680   Inst.addOperand(MCOperand::CreateReg(Reg));
 681   return MCDisassembler::Success;
 682 }
 683
 684 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 685                                                unsigned RegNo,
 686                                                uint64_t Address,
 687                                                const void *Decoder) {
 688   if (RegNo > 31)
 689     return MCDisassembler::Fail;
 690
 691   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
 692   Inst.addOperand(MCOperand::CreateReg(Reg));
 693   return MCDisassembler::Success;
 694 }
 695
 696 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 697                                                unsigned RegNo,
 698                                                uint64_t Address,
 699                                                const void *Decoder) {
 700   if (RegNo > 7)
 701     return MCDisassembler::Fail;
 702
 703   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
 704   Inst.addOperand(MCOperand::CreateReg(Reg));
 705   return MCDisassembler::Success;
 706 }
 707
 708 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 709                                        unsigned Offset,
 710                                        uint64_t Address,
 711                                        const void *Decoder) {
 712   unsigned BranchOffset = Offset & 0xffff;
 713   BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
 714   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
 715   return MCDisassembler::Success;
 716 }
 717
 718 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 719                                      unsigned Insn,
 720                                      uint64_t Address,
 721                                      const void *Decoder) {
 722
 723   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
 724   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
 725   return MCDisassembler::Success;
 726 }
 727
 728
 729 static DecodeStatus DecodeSimm16(MCInst &Inst,
 730                                  unsigned Insn,
 731                                  uint64_t Address,
 732                                  const void *Decoder) {
 733   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
 734   return MCDisassembler::Success;
 735 }
 736
 737 static DecodeStatus DecodeInsSize(MCInst &Inst,
 738                                   unsigned Insn,
 739                                   uint64_t Address,
 740                                   const void *Decoder) {
 741   // First we need to grab the pos(lsb) from MCInst.
 742   int Pos = Inst.getOperand(2).getImm();
 743   int Size = (int) Insn - Pos + 1;
 744   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 745   return MCDisassembler::Success;
 746 }
 747
 748 static DecodeStatus DecodeExtSize(MCInst &Inst,
 749                                   unsigned Insn,
 750                                   uint64_t Address,
 751                                   const void *Decoder) {
 752   int Size = (int) Insn  + 1;
 753   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
 754   return MCDisassembler::Success;
 755 }