lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/MemoryObject.h"
  24 #include "llvm/Support/TargetRegistry.h"
  25
  26 using namespace llvm;
  27
  28 #define DEBUG_TYPE "mips-disassembler"
  29
  30 typedef MCDisassembler::DecodeStatus DecodeStatus;
  31
  32 namespace {
  33
  34 /// A disasembler class for Mips.
  35 class MipsDisassemblerBase : public MCDisassembler {
  36 public:
  37   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  38                        bool IsBigEndian)
  39       : MCDisassembler(STI, Ctx),
  40         IsN64(STI.getFeatureBits() & Mips::FeatureN64),
  41         IsBigEndian(IsBigEndian) {}
  42
  43   virtual ~MipsDisassemblerBase() {}
  44
  45   bool isN64() const { return IsN64; }
  46
  47 private:
  48   bool IsN64;
  49 protected:
  50   bool IsBigEndian;
  51 };
  52
  53 /// A disasembler class for Mips32.
  54 class MipsDisassembler : public MipsDisassemblerBase {
  55   bool IsMicroMips;
  56 public:
  57   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  58       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  59     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  60   }
  61
  62   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  63   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  64   bool hasMips32r6() const {
  65     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  66   }
  67
  68   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  69
  70   bool hasCOP3() const {
  71     // Only present in MIPS-I and MIPS-II
  72     return !hasMips32() && !hasMips3();
  73   }
  74
  75   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  76                               const MemoryObject &Region, uint64_t Address,
  77                               raw_ostream &VStream,
  78                               raw_ostream &CStream) const override;
  79 };
  80
  81 /// A disasembler class for Mips64.
  82 class Mips64Disassembler : public MipsDisassemblerBase {
  83 public:
  84   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  85                      bool bigEndian) :
  86     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  87
  88   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  89                               const MemoryObject &Region, uint64_t Address,
  90                               raw_ostream &VStream,
  91                               raw_ostream &CStream) const override;
  92 };
  93
  94 } // end anonymous namespace
  95
  96 // Forward declare these because the autogenerated code will reference them.
  97 // Definitions are further down.
  98 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  99                                              unsigned RegNo,
 100                                              uint64_t Address,
 101                                              const void *Decoder);
 102
 103 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 104                                                  unsigned RegNo,
 105                                                  uint64_t Address,
 106                                                  const void *Decoder);
 107
 108 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 109                                                unsigned RegNo,
 110                                                uint64_t Address,
 111                                                const void *Decoder);
 112
 113 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 114                                              unsigned RegNo,
 115                                              uint64_t Address,
 116                                              const void *Decoder);
 117
 118 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 119                                            unsigned Insn,
 120                                            uint64_t Address,
 121                                            const void *Decoder);
 122
 123 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 124                                             unsigned RegNo,
 125                                             uint64_t Address,
 126                                             const void *Decoder);
 127
 128 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 129                                              unsigned RegNo,
 130                                              uint64_t Address,
 131                                              const void *Decoder);
 132
 133 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 134                                              unsigned RegNo,
 135                                              uint64_t Address,
 136                                              const void *Decoder);
 137
 138 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 139                                            unsigned RegNo,
 140                                            uint64_t Address,
 141                                            const void *Decoder);
 142
 143 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 144                                            unsigned RegNo,
 145                                            uint64_t Address,
 146                                            const void *Decoder);
 147
 148 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 149                                              uint64_t Address,
 150                                              const void *Decoder);
 151
 152 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 153                                               unsigned Insn,
 154                                               uint64_t Address,
 155                                               const void *Decoder);
 156
 157 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 158                                               unsigned RegNo,
 159                                               uint64_t Address,
 160                                               const void *Decoder);
 161
 162 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 163                                                 unsigned RegNo,
 164                                                 uint64_t Address,
 165                                                 const void *Decoder);
 166
 167 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 168                                                unsigned RegNo,
 169                                                uint64_t Address,
 170                                                const void *Decoder);
 171
 172 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 173                                                unsigned RegNo,
 174                                                uint64_t Address,
 175                                                const void *Decoder);
 176
 177 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 178                                                unsigned RegNo,
 179                                                uint64_t Address,
 180                                                const void *Decoder);
 181
 182 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 183                                                unsigned RegNo,
 184                                                uint64_t Address,
 185                                                const void *Decoder);
 186
 187 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 188                                                unsigned RegNo,
 189                                                uint64_t Address,
 190                                                const void *Decoder);
 191
 192 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 193                                                unsigned RegNo,
 194                                                uint64_t Address,
 195                                                const void *Decoder);
 196
 197 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 198                                                unsigned RegNo,
 199                                                uint64_t Address,
 200                                                const void *Decoder);
 201
 202 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 203                                             unsigned RegNo,
 204                                             uint64_t Address,
 205                                             const void *Decoder);
 206
 207 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 208                                        unsigned Offset,
 209                                        uint64_t Address,
 210                                        const void *Decoder);
 211
 212 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 213                                      unsigned Insn,
 214                                      uint64_t Address,
 215                                      const void *Decoder);
 216
 217 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 218                                          unsigned Offset,
 219                                          uint64_t Address,
 220                                          const void *Decoder);
 221
 222 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 223                                          unsigned Offset,
 224                                          uint64_t Address,
 225                                          const void *Decoder);
 226
 227 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 228 // shifted left by 1 bit.
 229 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 230                                          unsigned Offset,
 231                                          uint64_t Address,
 232                                          const void *Decoder);
 233
 234 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 235 // shifted left by 1 bit.
 236 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 237                                        unsigned Insn,
 238                                        uint64_t Address,
 239                                        const void *Decoder);
 240
 241 static DecodeStatus DecodeMem(MCInst &Inst,
 242                               unsigned Insn,
 243                               uint64_t Address,
 244                               const void *Decoder);
 245
 246 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 247                               unsigned Insn,
 248                               uint64_t Address,
 249                               const void *Decoder);
 250
 251 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 252                                     uint64_t Address, const void *Decoder);
 253
 254 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 255                                      unsigned Insn,
 256                                      uint64_t Address,
 257                                      const void *Decoder);
 258
 259 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 260                                      unsigned Insn,
 261                                      uint64_t Address,
 262                                      const void *Decoder);
 263
 264 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 265                                uint64_t Address,
 266                                const void *Decoder);
 267
 268 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 269                                uint64_t Address,
 270                                const void *Decoder);
 271
 272 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 273                                uint64_t Address,
 274                                const void *Decoder);
 275
 276 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 277                                        unsigned Insn,
 278                                        uint64_t Address,
 279                                        const void *Decoder);
 280
 281 static DecodeStatus DecodeSimm16(MCInst &Inst,
 282                                  unsigned Insn,
 283                                  uint64_t Address,
 284                                  const void *Decoder);
 285
 286 // Decode the immediate field of an LSA instruction which
 287 // is off by one.
 288 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 289                                  unsigned Insn,
 290                                  uint64_t Address,
 291                                  const void *Decoder);
 292
 293 static DecodeStatus DecodeInsSize(MCInst &Inst,
 294                                   unsigned Insn,
 295                                   uint64_t Address,
 296                                   const void *Decoder);
 297
 298 static DecodeStatus DecodeExtSize(MCInst &Inst,
 299                                   unsigned Insn,
 300                                   uint64_t Address,
 301                                   const void *Decoder);
 302
 303 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 304                                      uint64_t Address, const void *Decoder);
 305
 306 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 307                                      uint64_t Address, const void *Decoder);
 308
 309 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 310 /// handle.
 311 template <typename InsnType>
 312 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 313                                    const void *Decoder);
 314
 315 template <typename InsnType>
 316 static DecodeStatus
 317 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 318                       const void *Decoder);
 319
 320 template <typename InsnType>
 321 static DecodeStatus
 322 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 323                        const void *Decoder);
 324
 325 template <typename InsnType>
 326 static DecodeStatus
 327 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 328                        const void *Decoder);
 329
 330 template <typename InsnType>
 331 static DecodeStatus
 332 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 333                        const void *Decoder);
 334
 335 template <typename InsnType>
 336 static DecodeStatus
 337 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 338                       const void *Decoder);
 339
 340 template <typename InsnType>
 341 static DecodeStatus
 342 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 343                        const void *Decoder);
 344
 345 namespace llvm {
 346 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 347               TheMips64elTarget;
 348 }
 349
 350 static MCDisassembler *createMipsDisassembler(
 351                        const Target &T,
 352                        const MCSubtargetInfo &STI,
 353                        MCContext &Ctx) {
 354   return new MipsDisassembler(STI, Ctx, true);
 355 }
 356
 357 static MCDisassembler *createMipselDisassembler(
 358                        const Target &T,
 359                        const MCSubtargetInfo &STI,
 360                        MCContext &Ctx) {
 361   return new MipsDisassembler(STI, Ctx, false);
 362 }
 363
 364 static MCDisassembler *createMips64Disassembler(
 365                        const Target &T,
 366                        const MCSubtargetInfo &STI,
 367                        MCContext &Ctx) {
 368   return new Mips64Disassembler(STI, Ctx, true);
 369 }
 370
 371 static MCDisassembler *createMips64elDisassembler(
 372                        const Target &T,
 373                        const MCSubtargetInfo &STI,
 374                        MCContext &Ctx) {
 375   return new Mips64Disassembler(STI, Ctx, false);
 376 }
 377
 378 extern "C" void LLVMInitializeMipsDisassembler() {
 379   // Register the disassembler.
 380   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 381                                          createMipsDisassembler);
 382   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 383                                          createMipselDisassembler);
 384   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 385                                          createMips64Disassembler);
 386   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 387                                          createMips64elDisassembler);
 388 }
 389
 390 #include "MipsGenDisassemblerTables.inc"
 391
 392 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 393   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 394   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 395   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 396 }
 397
 398 template <typename InsnType>
 399 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 400                                    const void *Decoder) {
 401   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 402   // The size of the n field depends on the element size
 403   // The register class also depends on this.
 404   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 405   unsigned NSize = 0;
 406   DecodeFN RegDecoder = nullptr;
 407   if ((tmp & 0x18) == 0x00) { // INSVE_B
 408     NSize = 4;
 409     RegDecoder = DecodeMSA128BRegisterClass;
 410   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 411     NSize = 3;
 412     RegDecoder = DecodeMSA128HRegisterClass;
 413   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 414     NSize = 2;
 415     RegDecoder = DecodeMSA128WRegisterClass;
 416   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 417     NSize = 1;
 418     RegDecoder = DecodeMSA128DRegisterClass;
 419   } else
 420     llvm_unreachable("Invalid encoding");
 421
 422   assert(NSize != 0 && RegDecoder != nullptr);
 423
 424   // $wd
 425   tmp = fieldFromInstruction(insn, 6, 5);
 426   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 427     return MCDisassembler::Fail;
 428   // $wd_in
 429   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 430     return MCDisassembler::Fail;
 431   // $n
 432   tmp = fieldFromInstruction(insn, 16, NSize);
 433   MI.addOperand(MCOperand::CreateImm(tmp));
 434   // $ws
 435   tmp = fieldFromInstruction(insn, 11, 5);
 436   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 437     return MCDisassembler::Fail;
 438   // $n2
 439   MI.addOperand(MCOperand::CreateImm(0));
 440
 441   return MCDisassembler::Success;
 442 }
 443
 444 template <typename InsnType>
 445 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 446                                           uint64_t Address,
 447                                           const void *Decoder) {
 448   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 449   // (otherwise we would have matched the ADDI instruction from the earlier
 450   // ISA's instead).
 451   //
 452   // We have:
 453   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 454   //      BOVC if rs >= rt
 455   //      BEQZALC if rs == 0 && rt != 0
 456   //      BEQC if rs < rt && rs != 0
 457
 458   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 459   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 460   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 461   bool HasRs = false;
 462
 463   if (Rs >= Rt) {
 464     MI.setOpcode(Mips::BOVC);
 465     HasRs = true;
 466   } else if (Rs != 0 && Rs < Rt) {
 467     MI.setOpcode(Mips::BEQC);
 468     HasRs = true;
 469   } else
 470     MI.setOpcode(Mips::BEQZALC);
 471
 472   if (HasRs)
 473     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 474                                        Rs)));
 475
 476   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 477                                      Rt)));
 478   MI.addOperand(MCOperand::CreateImm(Imm));
 479
 480   return MCDisassembler::Success;
 481 }
 482
 483 template <typename InsnType>
 484 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 485                                            uint64_t Address,
 486                                            const void *Decoder) {
 487   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 488   // (otherwise we would have matched the ADDI instruction from the earlier
 489   // ISA's instead).
 490   //
 491   // We have:
 492   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 493   //      BNVC if rs >= rt
 494   //      BNEZALC if rs == 0 && rt != 0
 495   //      BNEC if rs < rt && rs != 0
 496
 497   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 498   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 499   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 500   bool HasRs = false;
 501
 502   if (Rs >= Rt) {
 503     MI.setOpcode(Mips::BNVC);
 504     HasRs = true;
 505   } else if (Rs != 0 && Rs < Rt) {
 506     MI.setOpcode(Mips::BNEC);
 507     HasRs = true;
 508   } else
 509     MI.setOpcode(Mips::BNEZALC);
 510
 511   if (HasRs)
 512     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 513                                        Rs)));
 514
 515   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 516                                      Rt)));
 517   MI.addOperand(MCOperand::CreateImm(Imm));
 518
 519   return MCDisassembler::Success;
 520 }
 521
 522 template <typename InsnType>
 523 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 524                                            uint64_t Address,
 525                                            const void *Decoder) {
 526   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 527   // (otherwise we would have matched the BLEZL instruction from the earlier
 528   // ISA's instead).
 529   //
 530   // We have:
 531   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 532   //      Invalid if rs == 0
 533   //      BLEZC   if rs == 0  && rt != 0
 534   //      BGEZC   if rs == rt && rt != 0
 535   //      BGEC    if rs != rt && rs != 0  && rt != 0
 536
 537   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 538   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 539   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 540   bool HasRs = false;
 541
 542   if (Rt == 0)
 543     return MCDisassembler::Fail;
 544   else if (Rs == 0)
 545     MI.setOpcode(Mips::BLEZC);
 546   else if (Rs == Rt)
 547     MI.setOpcode(Mips::BGEZC);
 548   else {
 549     HasRs = true;
 550     MI.setOpcode(Mips::BGEC);
 551   }
 552
 553   if (HasRs)
 554     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 555                                        Rs)));
 556
 557   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 558                                      Rt)));
 559
 560   MI.addOperand(MCOperand::CreateImm(Imm));
 561
 562   return MCDisassembler::Success;
 563 }
 564
 565 template <typename InsnType>
 566 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 567                                            uint64_t Address,
 568                                            const void *Decoder) {
 569   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 570   // (otherwise we would have matched the BGTZL instruction from the earlier
 571   // ISA's instead).
 572   //
 573   // We have:
 574   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 575   //      Invalid if rs == 0
 576   //      BGTZC   if rs == 0  && rt != 0
 577   //      BLTZC   if rs == rt && rt != 0
 578   //      BLTC    if rs != rt && rs != 0  && rt != 0
 579
 580   bool HasRs = false;
 581
 582   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 583   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 584   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 585
 586   if (Rt == 0)
 587     return MCDisassembler::Fail;
 588   else if (Rs == 0)
 589     MI.setOpcode(Mips::BGTZC);
 590   else if (Rs == Rt)
 591     MI.setOpcode(Mips::BLTZC);
 592   else {
 593     MI.setOpcode(Mips::BLTC);
 594     HasRs = true;
 595   }
 596
 597   if (HasRs)
 598     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 599                                               Rs)));
 600
 601   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 602                                      Rt)));
 603
 604   MI.addOperand(MCOperand::CreateImm(Imm));
 605
 606   return MCDisassembler::Success;
 607 }
 608
 609 template <typename InsnType>
 610 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 611                                           uint64_t Address,
 612                                           const void *Decoder) {
 613   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 614   // (otherwise we would have matched the BGTZ instruction from the earlier
 615   // ISA's instead).
 616   //
 617   // We have:
 618   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 619   //      BGTZ    if rt == 0
 620   //      BGTZALC if rs == 0 && rt != 0
 621   //      BLTZALC if rs != 0 && rs == rt
 622   //      BLTUC   if rs != 0 && rs != rt
 623
 624   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 625   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 626   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 627   bool HasRs = false;
 628   bool HasRt = false;
 629
 630   if (Rt == 0) {
 631     MI.setOpcode(Mips::BGTZ);
 632     HasRs = true;
 633   } else if (Rs == 0) {
 634     MI.setOpcode(Mips::BGTZALC);
 635     HasRt = true;
 636   } else if (Rs == Rt) {
 637     MI.setOpcode(Mips::BLTZALC);
 638     HasRs = true;
 639   } else {
 640     MI.setOpcode(Mips::BLTUC);
 641     HasRs = true;
 642     HasRt = true;
 643   }
 644
 645   if (HasRs)
 646     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 647                                        Rs)));
 648
 649   if (HasRt)
 650     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 651                                        Rt)));
 652
 653   MI.addOperand(MCOperand::CreateImm(Imm));
 654
 655   return MCDisassembler::Success;
 656 }
 657
 658 template <typename InsnType>
 659 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 660                                            uint64_t Address,
 661                                            const void *Decoder) {
 662   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 663   // (otherwise we would have matched the BLEZL instruction from the earlier
 664   // ISA's instead).
 665   //
 666   // We have:
 667   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 668   //      Invalid   if rs == 0
 669   //      BLEZALC   if rs == 0  && rt != 0
 670   //      BGEZALC   if rs == rt && rt != 0
 671   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 672
 673   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 674   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 675   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 676   bool HasRs = false;
 677
 678   if (Rt == 0)
 679     return MCDisassembler::Fail;
 680   else if (Rs == 0)
 681     MI.setOpcode(Mips::BLEZALC);
 682   else if (Rs == Rt)
 683     MI.setOpcode(Mips::BGEZALC);
 684   else {
 685     HasRs = true;
 686     MI.setOpcode(Mips::BGEUC);
 687   }
 688
 689   if (HasRs)
 690     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 691                                        Rs)));
 692   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 693                                      Rt)));
 694
 695   MI.addOperand(MCOperand::CreateImm(Imm));
 696
 697   return MCDisassembler::Success;
 698 }
 699
 700 /// Read four bytes from the MemoryObject and return 32 bit word sorted
 701 /// according to the given endianess
 702 static DecodeStatus readInstruction32(const MemoryObject &Region,
 703                                       uint64_t Address, uint64_t &Size,
 704                                       uint32_t &Insn, bool IsBigEndian,
 705                                       bool IsMicroMips) {
 706   uint8_t Bytes[4];
 707
 708   // We want to read exactly 4 Bytes of data.
 709   if (Region.readBytes(Address, 4, Bytes) == -1) {
 710     Size = 0;
 711     return MCDisassembler::Fail;
 712   }
 713
 714   if (IsBigEndian) {
 715     // Encoded as a big-endian 32-bit word in the stream.
 716     Insn =
 717         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 718   } else {
 719     // Encoded as a small-endian 32-bit word in the stream.
 720     // Little-endian byte ordering:
 721     //   mips32r2:   4 | 3 | 2 | 1
 722     //   microMIPS:  2 | 1 | 4 | 3
 723     if (IsMicroMips) {
 724       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 725              (Bytes[1] << 24);
 726     } else {
 727       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 728              (Bytes[3] << 24);
 729     }
 730   }
 731
 732   return MCDisassembler::Success;
 733 }
 734
 735 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 736                                               const MemoryObject &Region,
 737                                               uint64_t Address,
 738                                               raw_ostream &VStream,
 739                                               raw_ostream &CStream) const {
 740   uint32_t Insn;
 741
 742   DecodeStatus Result =
 743       readInstruction32(Region, Address, Size, Insn, IsBigEndian, IsMicroMips);
 744   if (Result == MCDisassembler::Fail)
 745     return MCDisassembler::Fail;
 746
 747   if (IsMicroMips) {
 748     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n");
 749     // Calling the auto-generated decoder function.
 750     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 751                                this, STI);
 752     if (Result != MCDisassembler::Fail) {
 753       Size = 4;
 754       return Result;
 755     }
 756     return MCDisassembler::Fail;
 757   }
 758
 759   if (hasCOP3()) {
 760     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 761     Result =
 762         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 763     if (Result != MCDisassembler::Fail) {
 764       Size = 4;
 765       return Result;
 766     }
 767   }
 768
 769   if (hasMips32r6() && isGP64()) {
 770     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 771     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 772                                Address, this, STI);
 773     if (Result != MCDisassembler::Fail) {
 774       Size = 4;
 775       return Result;
 776     }
 777   }
 778
 779   if (hasMips32r6()) {
 780     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 781     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 782                                Address, this, STI);
 783     if (Result != MCDisassembler::Fail) {
 784       Size = 4;
 785       return Result;
 786     }
 787   }
 788
 789   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 790   // Calling the auto-generated decoder function.
 791   Result =
 792       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 793   if (Result != MCDisassembler::Fail) {
 794     Size = 4;
 795     return Result;
 796   }
 797
 798   return MCDisassembler::Fail;
 799 }
 800
 801 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 802                                                 const MemoryObject &Region,
 803                                                 uint64_t Address,
 804                                                 raw_ostream &VStream,
 805                                                 raw_ostream &CStream) const {
 806   uint32_t Insn;
 807
 808   DecodeStatus Result =
 809       readInstruction32(Region, Address, Size, Insn, IsBigEndian, false);
 810   if (Result == MCDisassembler::Fail)
 811     return MCDisassembler::Fail;
 812
 813   // Calling the auto-generated decoder function.
 814   Result =
 815       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 816   if (Result != MCDisassembler::Fail) {
 817     Size = 4;
 818     return Result;
 819   }
 820   // If we fail to decode in Mips64 decoder space we can try in Mips32
 821   Result =
 822       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 823   if (Result != MCDisassembler::Fail) {
 824     Size = 4;
 825     return Result;
 826   }
 827
 828   return MCDisassembler::Fail;
 829 }
 830
 831 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 832                                                  unsigned RegNo,
 833                                                  uint64_t Address,
 834                                                  const void *Decoder) {
 835
 836   return MCDisassembler::Fail;
 837
 838 }
 839
 840 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 841                                              unsigned RegNo,
 842                                              uint64_t Address,
 843                                              const void *Decoder) {
 844
 845   if (RegNo > 31)
 846     return MCDisassembler::Fail;
 847
 848   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 849   Inst.addOperand(MCOperand::CreateReg(Reg));
 850   return MCDisassembler::Success;
 851 }
 852
 853 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 854                                                unsigned RegNo,
 855                                                uint64_t Address,
 856                                                const void *Decoder) {
 857   return MCDisassembler::Fail;
 858 }
 859
 860 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 861                                              unsigned RegNo,
 862                                              uint64_t Address,
 863                                              const void *Decoder) {
 864   if (RegNo > 31)
 865     return MCDisassembler::Fail;
 866   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 867   Inst.addOperand(MCOperand::CreateReg(Reg));
 868   return MCDisassembler::Success;
 869 }
 870
 871 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 872                                            unsigned RegNo,
 873                                            uint64_t Address,
 874                                            const void *Decoder) {
 875   if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
 876     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
 877
 878   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 879 }
 880
 881 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 882                                             unsigned RegNo,
 883                                             uint64_t Address,
 884                                             const void *Decoder) {
 885   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
 886 }
 887
 888 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 889                                              unsigned RegNo,
 890                                              uint64_t Address,
 891                                              const void *Decoder) {
 892   if (RegNo > 31)
 893     return MCDisassembler::Fail;
 894
 895   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
 896   Inst.addOperand(MCOperand::CreateReg(Reg));
 897   return MCDisassembler::Success;
 898 }
 899
 900 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 901                                              unsigned RegNo,
 902                                              uint64_t Address,
 903                                              const void *Decoder) {
 904   if (RegNo > 31)
 905     return MCDisassembler::Fail;
 906
 907   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
 908   Inst.addOperand(MCOperand::CreateReg(Reg));
 909   return MCDisassembler::Success;
 910 }
 911
 912 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 913                                            unsigned RegNo,
 914                                            uint64_t Address,
 915                                            const void *Decoder) {
 916   if (RegNo > 31)
 917     return MCDisassembler::Fail;
 918   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
 919   Inst.addOperand(MCOperand::CreateReg(Reg));
 920   return MCDisassembler::Success;
 921 }
 922
 923 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 924                                            unsigned RegNo,
 925                                            uint64_t Address,
 926                                            const void *Decoder) {
 927   if (RegNo > 7)
 928     return MCDisassembler::Fail;
 929   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
 930   Inst.addOperand(MCOperand::CreateReg(Reg));
 931   return MCDisassembler::Success;
 932 }
 933
 934 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 935                                              uint64_t Address,
 936                                              const void *Decoder) {
 937   if (RegNo > 31)
 938     return MCDisassembler::Fail;
 939
 940   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
 941   Inst.addOperand(MCOperand::CreateReg(Reg));
 942   return MCDisassembler::Success;
 943 }
 944
 945 static DecodeStatus DecodeMem(MCInst &Inst,
 946                               unsigned Insn,
 947                               uint64_t Address,
 948                               const void *Decoder) {
 949   int Offset = SignExtend32<16>(Insn & 0xffff);
 950   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 951   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 952
 953   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
 954   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 955
 956   if(Inst.getOpcode() == Mips::SC){
 957     Inst.addOperand(MCOperand::CreateReg(Reg));
 958   }
 959
 960   Inst.addOperand(MCOperand::CreateReg(Reg));
 961   Inst.addOperand(MCOperand::CreateReg(Base));
 962   Inst.addOperand(MCOperand::CreateImm(Offset));
 963
 964   return MCDisassembler::Success;
 965 }
 966
 967 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 968                               unsigned Insn,
 969                               uint64_t Address,
 970                               const void *Decoder) {
 971   int Offset = SignExtend32<16>(Insn & 0xffff);
 972   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
 973   unsigned Base = fieldFromInstruction(Insn, 21, 5);
 974
 975   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 976
 977   Inst.addOperand(MCOperand::CreateReg(Base));
 978   Inst.addOperand(MCOperand::CreateImm(Offset));
 979   Inst.addOperand(MCOperand::CreateImm(Hint));
 980
 981   return MCDisassembler::Success;
 982 }
 983
 984 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 985                                     uint64_t Address, const void *Decoder) {
 986   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
 987   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
 988   unsigned Base = fieldFromInstruction(Insn, 11, 5);
 989
 990   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
 991   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
 992
 993   Inst.addOperand(MCOperand::CreateReg(Reg));
 994   Inst.addOperand(MCOperand::CreateReg(Base));
 995
 996   // The immediate field of an LD/ST instruction is scaled which means it must
 997   // be multiplied (when decoding) by the size (in bytes) of the instructions'
 998   // data format.
 999   // .b - 1 byte
1000   // .h - 2 bytes
1001   // .w - 4 bytes
1002   // .d - 8 bytes
1003   switch(Inst.getOpcode())
1004   {
1005   default:
1006     assert (0 && "Unexpected instruction");
1007     return MCDisassembler::Fail;
1008     break;
1009   case Mips::LD_B:
1010   case Mips::ST_B:
1011     Inst.addOperand(MCOperand::CreateImm(Offset));
1012     break;
1013   case Mips::LD_H:
1014   case Mips::ST_H:
1015     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1016     break;
1017   case Mips::LD_W:
1018   case Mips::ST_W:
1019     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1020     break;
1021   case Mips::LD_D:
1022   case Mips::ST_D:
1023     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1024     break;
1025   }
1026
1027   return MCDisassembler::Success;
1028 }
1029
1030 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1031                                      unsigned Insn,
1032                                      uint64_t Address,
1033                                      const void *Decoder) {
1034   int Offset = SignExtend32<12>(Insn & 0x0fff);
1035   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1036   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1037
1038   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1039   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1040
1041   if (Inst.getOpcode() == Mips::SC_MM)
1042     Inst.addOperand(MCOperand::CreateReg(Reg));
1043
1044   Inst.addOperand(MCOperand::CreateReg(Reg));
1045   Inst.addOperand(MCOperand::CreateReg(Base));
1046   Inst.addOperand(MCOperand::CreateImm(Offset));
1047
1048   return MCDisassembler::Success;
1049 }
1050
1051 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1052                                      unsigned Insn,
1053                                      uint64_t Address,
1054                                      const void *Decoder) {
1055   int Offset = SignExtend32<16>(Insn & 0xffff);
1056   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1057   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1058
1059   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1060   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1061
1062   Inst.addOperand(MCOperand::CreateReg(Reg));
1063   Inst.addOperand(MCOperand::CreateReg(Base));
1064   Inst.addOperand(MCOperand::CreateImm(Offset));
1065
1066   return MCDisassembler::Success;
1067 }
1068
1069 static DecodeStatus DecodeFMem(MCInst &Inst,
1070                                unsigned Insn,
1071                                uint64_t Address,
1072                                const void *Decoder) {
1073   int Offset = SignExtend32<16>(Insn & 0xffff);
1074   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1075   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1076
1077   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1078   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1079
1080   Inst.addOperand(MCOperand::CreateReg(Reg));
1081   Inst.addOperand(MCOperand::CreateReg(Base));
1082   Inst.addOperand(MCOperand::CreateImm(Offset));
1083
1084   return MCDisassembler::Success;
1085 }
1086
1087 static DecodeStatus DecodeFMem2(MCInst &Inst,
1088                                unsigned Insn,
1089                                uint64_t Address,
1090                                const void *Decoder) {
1091   int Offset = SignExtend32<16>(Insn & 0xffff);
1092   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1093   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1094
1095   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1096   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1097
1098   Inst.addOperand(MCOperand::CreateReg(Reg));
1099   Inst.addOperand(MCOperand::CreateReg(Base));
1100   Inst.addOperand(MCOperand::CreateImm(Offset));
1101
1102   return MCDisassembler::Success;
1103 }
1104
1105 static DecodeStatus DecodeFMem3(MCInst &Inst,
1106                                unsigned Insn,
1107                                uint64_t Address,
1108                                const void *Decoder) {
1109   int Offset = SignExtend32<16>(Insn & 0xffff);
1110   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1111   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1112
1113   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1114   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1115
1116   Inst.addOperand(MCOperand::CreateReg(Reg));
1117   Inst.addOperand(MCOperand::CreateReg(Base));
1118   Inst.addOperand(MCOperand::CreateImm(Offset));
1119
1120   return MCDisassembler::Success;
1121 }
1122
1123 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1124                                        unsigned Insn,
1125                                        uint64_t Address,
1126                                        const void *Decoder) {
1127   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1128   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1129   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1130
1131   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1132   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1133
1134   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1135     Inst.addOperand(MCOperand::CreateReg(Rt));
1136   }
1137
1138   Inst.addOperand(MCOperand::CreateReg(Rt));
1139   Inst.addOperand(MCOperand::CreateReg(Base));
1140   Inst.addOperand(MCOperand::CreateImm(Offset));
1141
1142   return MCDisassembler::Success;
1143 }
1144
1145 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1146                                               unsigned RegNo,
1147                                               uint64_t Address,
1148                                               const void *Decoder) {
1149   // Currently only hardware register 29 is supported.
1150   if (RegNo != 29)
1151     return  MCDisassembler::Fail;
1152   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1153   return MCDisassembler::Success;
1154 }
1155
1156 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1157                                               unsigned RegNo,
1158                                               uint64_t Address,
1159                                               const void *Decoder) {
1160   if (RegNo > 30 || RegNo %2)
1161     return MCDisassembler::Fail;
1162
1163   ;
1164   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1165   Inst.addOperand(MCOperand::CreateReg(Reg));
1166   return MCDisassembler::Success;
1167 }
1168
1169 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1170                                                 unsigned RegNo,
1171                                                 uint64_t Address,
1172                                                 const void *Decoder) {
1173   if (RegNo >= 4)
1174     return MCDisassembler::Fail;
1175
1176   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1177   Inst.addOperand(MCOperand::CreateReg(Reg));
1178   return MCDisassembler::Success;
1179 }
1180
1181 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1182                                                unsigned RegNo,
1183                                                uint64_t Address,
1184                                                const void *Decoder) {
1185   if (RegNo >= 4)
1186     return MCDisassembler::Fail;
1187
1188   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1189   Inst.addOperand(MCOperand::CreateReg(Reg));
1190   return MCDisassembler::Success;
1191 }
1192
1193 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1194                                                unsigned RegNo,
1195                                                uint64_t Address,
1196                                                const void *Decoder) {
1197   if (RegNo >= 4)
1198     return MCDisassembler::Fail;
1199
1200   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1201   Inst.addOperand(MCOperand::CreateReg(Reg));
1202   return MCDisassembler::Success;
1203 }
1204
1205 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1206                                                unsigned RegNo,
1207                                                uint64_t Address,
1208                                                const void *Decoder) {
1209   if (RegNo > 31)
1210     return MCDisassembler::Fail;
1211
1212   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1213   Inst.addOperand(MCOperand::CreateReg(Reg));
1214   return MCDisassembler::Success;
1215 }
1216
1217 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1218                                                unsigned RegNo,
1219                                                uint64_t Address,
1220                                                const void *Decoder) {
1221   if (RegNo > 31)
1222     return MCDisassembler::Fail;
1223
1224   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1225   Inst.addOperand(MCOperand::CreateReg(Reg));
1226   return MCDisassembler::Success;
1227 }
1228
1229 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1230                                                unsigned RegNo,
1231                                                uint64_t Address,
1232                                                const void *Decoder) {
1233   if (RegNo > 31)
1234     return MCDisassembler::Fail;
1235
1236   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1237   Inst.addOperand(MCOperand::CreateReg(Reg));
1238   return MCDisassembler::Success;
1239 }
1240
1241 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1242                                                unsigned RegNo,
1243                                                uint64_t Address,
1244                                                const void *Decoder) {
1245   if (RegNo > 31)
1246     return MCDisassembler::Fail;
1247
1248   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1249   Inst.addOperand(MCOperand::CreateReg(Reg));
1250   return MCDisassembler::Success;
1251 }
1252
1253 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1254                                                unsigned RegNo,
1255                                                uint64_t Address,
1256                                                const void *Decoder) {
1257   if (RegNo > 7)
1258     return MCDisassembler::Fail;
1259
1260   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1261   Inst.addOperand(MCOperand::CreateReg(Reg));
1262   return MCDisassembler::Success;
1263 }
1264
1265 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1266                                             unsigned RegNo,
1267                                             uint64_t Address,
1268                                             const void *Decoder) {
1269   if (RegNo > 31)
1270     return MCDisassembler::Fail;
1271
1272   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1273   Inst.addOperand(MCOperand::CreateReg(Reg));
1274   return MCDisassembler::Success;
1275 }
1276
1277 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1278                                        unsigned Offset,
1279                                        uint64_t Address,
1280                                        const void *Decoder) {
1281   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1282   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1283   return MCDisassembler::Success;
1284 }
1285
1286 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1287                                      unsigned Insn,
1288                                      uint64_t Address,
1289                                      const void *Decoder) {
1290
1291   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1292   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1293   return MCDisassembler::Success;
1294 }
1295
1296 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1297                                          unsigned Offset,
1298                                          uint64_t Address,
1299                                          const void *Decoder) {
1300   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1301
1302   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1303   return MCDisassembler::Success;
1304 }
1305
1306 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1307                                          unsigned Offset,
1308                                          uint64_t Address,
1309                                          const void *Decoder) {
1310   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1311
1312   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1313   return MCDisassembler::Success;
1314 }
1315
1316 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1317                                          unsigned Offset,
1318                                          uint64_t Address,
1319                                          const void *Decoder) {
1320   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1321   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1322   return MCDisassembler::Success;
1323 }
1324
1325 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1326                                        unsigned Insn,
1327                                        uint64_t Address,
1328                                        const void *Decoder) {
1329   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1330   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1331   return MCDisassembler::Success;
1332 }
1333
1334 static DecodeStatus DecodeSimm16(MCInst &Inst,
1335                                  unsigned Insn,
1336                                  uint64_t Address,
1337                                  const void *Decoder) {
1338   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1339   return MCDisassembler::Success;
1340 }
1341
1342 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1343                                  unsigned Insn,
1344                                  uint64_t Address,
1345                                  const void *Decoder) {
1346   // We add one to the immediate field as it was encoded as 'imm - 1'.
1347   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1348   return MCDisassembler::Success;
1349 }
1350
1351 static DecodeStatus DecodeInsSize(MCInst &Inst,
1352                                   unsigned Insn,
1353                                   uint64_t Address,
1354                                   const void *Decoder) {
1355   // First we need to grab the pos(lsb) from MCInst.
1356   int Pos = Inst.getOperand(2).getImm();
1357   int Size = (int) Insn - Pos + 1;
1358   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1359   return MCDisassembler::Success;
1360 }
1361
1362 static DecodeStatus DecodeExtSize(MCInst &Inst,
1363                                   unsigned Insn,
1364                                   uint64_t Address,
1365                                   const void *Decoder) {
1366   int Size = (int) Insn  + 1;
1367   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1368   return MCDisassembler::Success;
1369 }
1370
1371 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1372                                      uint64_t Address, const void *Decoder) {
1373   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1374   return MCDisassembler::Success;
1375 }
1376
1377 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1378                                      uint64_t Address, const void *Decoder) {
1379   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1380   return MCDisassembler::Success;
1381 }