lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 /// A disasembler class for Mips.
  34 class MipsDisassemblerBase : public MCDisassembler {
  35 public:
  36   MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx,
  37                        bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsGP64Bit(STI.getFeatureBits() & Mips::FeatureGP64Bit),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   virtual ~MipsDisassemblerBase() {}
  43
  44   bool isGP64Bit() const { return IsGP64Bit; }
  45
  46 private:
  47   bool IsGP64Bit;
  48 protected:
  49   bool IsBigEndian;
  50 };
  51
  52 /// A disasembler class for Mips32.
  53 class MipsDisassembler : public MipsDisassemblerBase {
  54   bool IsMicroMips;
  55 public:
  56   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian)
  57       : MipsDisassemblerBase(STI, Ctx, bigEndian) {
  58     IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
  59   }
  60
  61   bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
  62   bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
  63   bool hasMips32r6() const {
  64     return STI.getFeatureBits() & Mips::FeatureMips32r6;
  65   }
  66
  67   bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
  68
  69   bool hasCOP3() const {
  70     // Only present in MIPS-I and MIPS-II
  71     return !hasMips32() && !hasMips3();
  72   }
  73
  74   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  75                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  76                               raw_ostream &VStream,
  77                               raw_ostream &CStream) const override;
  78 };
  79
  80 /// A disasembler class for Mips64.
  81 class Mips64Disassembler : public MipsDisassemblerBase {
  82 public:
  83   Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
  84                      bool bigEndian) :
  85     MipsDisassemblerBase(STI, Ctx, bigEndian) {}
  86
  87   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  88                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  89                               raw_ostream &VStream,
  90                               raw_ostream &CStream) const override;
  91 };
  92
  93 } // end anonymous namespace
  94
  95 // Forward declare these because the autogenerated code will reference them.
  96 // Definitions are further down.
  97 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  98                                              unsigned RegNo,
  99                                              uint64_t Address,
 100                                              const void *Decoder);
 101
 102 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 103                                                  unsigned RegNo,
 104                                                  uint64_t Address,
 105                                                  const void *Decoder);
 106
 107 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 108                                                unsigned RegNo,
 109                                                uint64_t Address,
 110                                                const void *Decoder);
 111
 112 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 113                                                    unsigned RegNo,
 114                                                    uint64_t Address,
 115                                                    const void *Decoder);
 116
 117 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 118                                              unsigned RegNo,
 119                                              uint64_t Address,
 120                                              const void *Decoder);
 121
 122 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 123                                            unsigned Insn,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 128                                             unsigned RegNo,
 129                                             uint64_t Address,
 130                                             const void *Decoder);
 131
 132 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 133                                              unsigned RegNo,
 134                                              uint64_t Address,
 135                                              const void *Decoder);
 136
 137 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 138                                              unsigned RegNo,
 139                                              uint64_t Address,
 140                                              const void *Decoder);
 141
 142 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 143                                            unsigned RegNo,
 144                                            uint64_t Address,
 145                                            const void *Decoder);
 146
 147 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 148                                            unsigned RegNo,
 149                                            uint64_t Address,
 150                                            const void *Decoder);
 151
 152 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 153                                              uint64_t Address,
 154                                              const void *Decoder);
 155
 156 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 157                                               unsigned Insn,
 158                                               uint64_t Address,
 159                                               const void *Decoder);
 160
 161 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 162                                               unsigned RegNo,
 163                                               uint64_t Address,
 164                                               const void *Decoder);
 165
 166 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 167                                                 unsigned RegNo,
 168                                                 uint64_t Address,
 169                                                 const void *Decoder);
 170
 171 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 182                                                unsigned RegNo,
 183                                                uint64_t Address,
 184                                                const void *Decoder);
 185
 186 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 187                                                unsigned RegNo,
 188                                                uint64_t Address,
 189                                                const void *Decoder);
 190
 191 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 192                                                unsigned RegNo,
 193                                                uint64_t Address,
 194                                                const void *Decoder);
 195
 196 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 197                                                unsigned RegNo,
 198                                                uint64_t Address,
 199                                                const void *Decoder);
 200
 201 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 202                                                unsigned RegNo,
 203                                                uint64_t Address,
 204                                                const void *Decoder);
 205
 206 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 207                                             unsigned RegNo,
 208                                             uint64_t Address,
 209                                             const void *Decoder);
 210
 211 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 212                                        unsigned Offset,
 213                                        uint64_t Address,
 214                                        const void *Decoder);
 215
 216 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 217                                      unsigned Insn,
 218                                      uint64_t Address,
 219                                      const void *Decoder);
 220
 221 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 222                                          unsigned Offset,
 223                                          uint64_t Address,
 224                                          const void *Decoder);
 225
 226 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 227                                          unsigned Offset,
 228                                          uint64_t Address,
 229                                          const void *Decoder);
 230
 231 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 232 // shifted left by 1 bit.
 233 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 234                                           unsigned Offset,
 235                                           uint64_t Address,
 236                                           const void *Decoder);
 237
 238 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 239 // shifted left by 1 bit.
 240 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 241                                            unsigned Offset,
 242                                            uint64_t Address,
 243                                            const void *Decoder);
 244
 245 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 246 // shifted left by 1 bit.
 247 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 248                                          unsigned Offset,
 249                                          uint64_t Address,
 250                                          const void *Decoder);
 251
 252 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 253 // shifted left by 1 bit.
 254 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 255                                        unsigned Insn,
 256                                        uint64_t Address,
 257                                        const void *Decoder);
 258
 259 static DecodeStatus DecodeMem(MCInst &Inst,
 260                               unsigned Insn,
 261                               uint64_t Address,
 262                               const void *Decoder);
 263
 264 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 265                               unsigned Insn,
 266                               uint64_t Address,
 267                               const void *Decoder);
 268
 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeSyncI(MCInst &Inst,
 275                                 unsigned Insn,
 276                                 uint64_t Address,
 277                                 const void *Decoder);
 278
 279 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 280                                     uint64_t Address, const void *Decoder);
 281
 282 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 283                                     unsigned Insn,
 284                                     uint64_t Address,
 285                                     const void *Decoder);
 286
 287 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 288                                           unsigned Insn,
 289                                           uint64_t Address,
 290                                           const void *Decoder);
 291
 292 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 293                                      unsigned Insn,
 294                                      uint64_t Address,
 295                                      const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 298                                      unsigned Insn,
 299                                      uint64_t Address,
 300                                      const void *Decoder);
 301
 302 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 303                                uint64_t Address,
 304                                const void *Decoder);
 305
 306 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 307                                uint64_t Address,
 308                                const void *Decoder);
 309
 310 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 311                                uint64_t Address,
 312                                const void *Decoder);
 313
 314 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 315                                        unsigned Insn,
 316                                        uint64_t Address,
 317                                        const void *Decoder);
 318
 319 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 320                                        unsigned Value,
 321                                        uint64_t Address,
 322                                        const void *Decoder);
 323
 324 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 325                                     unsigned Value,
 326                                     uint64_t Address,
 327                                     const void *Decoder);
 328
 329 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 330                                   unsigned Value,
 331                                   uint64_t Address,
 332                                   const void *Decoder);
 333
 334 static DecodeStatus DecodeSimm4(MCInst &Inst,
 335                                 unsigned Value,
 336                                 uint64_t Address,
 337                                 const void *Decoder);
 338
 339 static DecodeStatus DecodeSimm16(MCInst &Inst,
 340                                  unsigned Insn,
 341                                  uint64_t Address,
 342                                  const void *Decoder);
 343
 344 // Decode the immediate field of an LSA instruction which
 345 // is off by one.
 346 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 347                                  unsigned Insn,
 348                                  uint64_t Address,
 349                                  const void *Decoder);
 350
 351 static DecodeStatus DecodeInsSize(MCInst &Inst,
 352                                   unsigned Insn,
 353                                   uint64_t Address,
 354                                   const void *Decoder);
 355
 356 static DecodeStatus DecodeExtSize(MCInst &Inst,
 357                                   unsigned Insn,
 358                                   uint64_t Address,
 359                                   const void *Decoder);
 360
 361 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 362                                      uint64_t Address, const void *Decoder);
 363
 364 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 365                                      uint64_t Address, const void *Decoder);
 366
 367 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 368                                   uint64_t Address, const void *Decoder);
 369
 370 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 371                                     uint64_t Address, const void *Decoder);
 372
 373 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 374                                    uint64_t Address, const void *Decoder);
 375
 376 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 377 /// handle.
 378 template <typename InsnType>
 379 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 380                                    const void *Decoder);
 381
 382 template <typename InsnType>
 383 static DecodeStatus
 384 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 385                       const void *Decoder);
 386
 387 template <typename InsnType>
 388 static DecodeStatus
 389 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 390                        const void *Decoder);
 391
 392 template <typename InsnType>
 393 static DecodeStatus
 394 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 395                        const void *Decoder);
 396
 397 template <typename InsnType>
 398 static DecodeStatus
 399 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 400                        const void *Decoder);
 401
 402 template <typename InsnType>
 403 static DecodeStatus
 404 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 405                       const void *Decoder);
 406
 407 template <typename InsnType>
 408 static DecodeStatus
 409 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 410                        const void *Decoder);
 411
 412 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 413                                          uint64_t Address,
 414                                          const void *Decoder);
 415
 416 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 417                                            uint64_t Address,
 418                                            const void *Decoder);
 419
 420 namespace llvm {
 421 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 422               TheMips64elTarget;
 423 }
 424
 425 static MCDisassembler *createMipsDisassembler(
 426                        const Target &T,
 427                        const MCSubtargetInfo &STI,
 428                        MCContext &Ctx) {
 429   return new MipsDisassembler(STI, Ctx, true);
 430 }
 431
 432 static MCDisassembler *createMipselDisassembler(
 433                        const Target &T,
 434                        const MCSubtargetInfo &STI,
 435                        MCContext &Ctx) {
 436   return new MipsDisassembler(STI, Ctx, false);
 437 }
 438
 439 static MCDisassembler *createMips64Disassembler(
 440                        const Target &T,
 441                        const MCSubtargetInfo &STI,
 442                        MCContext &Ctx) {
 443   return new Mips64Disassembler(STI, Ctx, true);
 444 }
 445
 446 static MCDisassembler *createMips64elDisassembler(
 447                        const Target &T,
 448                        const MCSubtargetInfo &STI,
 449                        MCContext &Ctx) {
 450   return new Mips64Disassembler(STI, Ctx, false);
 451 }
 452
 453 extern "C" void LLVMInitializeMipsDisassembler() {
 454   // Register the disassembler.
 455   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 456                                          createMipsDisassembler);
 457   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 458                                          createMipselDisassembler);
 459   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 460                                          createMips64Disassembler);
 461   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 462                                          createMips64elDisassembler);
 463 }
 464
 465 #include "MipsGenDisassemblerTables.inc"
 466
 467 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 468   const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
 469   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 470   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 471 }
 472
 473 template <typename InsnType>
 474 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 475                                    const void *Decoder) {
 476   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 477   // The size of the n field depends on the element size
 478   // The register class also depends on this.
 479   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 480   unsigned NSize = 0;
 481   DecodeFN RegDecoder = nullptr;
 482   if ((tmp & 0x18) == 0x00) { // INSVE_B
 483     NSize = 4;
 484     RegDecoder = DecodeMSA128BRegisterClass;
 485   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 486     NSize = 3;
 487     RegDecoder = DecodeMSA128HRegisterClass;
 488   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 489     NSize = 2;
 490     RegDecoder = DecodeMSA128WRegisterClass;
 491   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 492     NSize = 1;
 493     RegDecoder = DecodeMSA128DRegisterClass;
 494   } else
 495     llvm_unreachable("Invalid encoding");
 496
 497   assert(NSize != 0 && RegDecoder != nullptr);
 498
 499   // $wd
 500   tmp = fieldFromInstruction(insn, 6, 5);
 501   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 502     return MCDisassembler::Fail;
 503   // $wd_in
 504   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 505     return MCDisassembler::Fail;
 506   // $n
 507   tmp = fieldFromInstruction(insn, 16, NSize);
 508   MI.addOperand(MCOperand::CreateImm(tmp));
 509   // $ws
 510   tmp = fieldFromInstruction(insn, 11, 5);
 511   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 512     return MCDisassembler::Fail;
 513   // $n2
 514   MI.addOperand(MCOperand::CreateImm(0));
 515
 516   return MCDisassembler::Success;
 517 }
 518
 519 template <typename InsnType>
 520 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 521                                           uint64_t Address,
 522                                           const void *Decoder) {
 523   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 524   // (otherwise we would have matched the ADDI instruction from the earlier
 525   // ISA's instead).
 526   //
 527   // We have:
 528   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 529   //      BOVC if rs >= rt
 530   //      BEQZALC if rs == 0 && rt != 0
 531   //      BEQC if rs < rt && rs != 0
 532
 533   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 534   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 535   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 536   bool HasRs = false;
 537
 538   if (Rs >= Rt) {
 539     MI.setOpcode(Mips::BOVC);
 540     HasRs = true;
 541   } else if (Rs != 0 && Rs < Rt) {
 542     MI.setOpcode(Mips::BEQC);
 543     HasRs = true;
 544   } else
 545     MI.setOpcode(Mips::BEQZALC);
 546
 547   if (HasRs)
 548     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 549                                        Rs)));
 550
 551   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 552                                      Rt)));
 553   MI.addOperand(MCOperand::CreateImm(Imm));
 554
 555   return MCDisassembler::Success;
 556 }
 557
 558 template <typename InsnType>
 559 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 560                                            uint64_t Address,
 561                                            const void *Decoder) {
 562   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 563   // (otherwise we would have matched the ADDI instruction from the earlier
 564   // ISA's instead).
 565   //
 566   // We have:
 567   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 568   //      BNVC if rs >= rt
 569   //      BNEZALC if rs == 0 && rt != 0
 570   //      BNEC if rs < rt && rs != 0
 571
 572   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 573   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 574   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 575   bool HasRs = false;
 576
 577   if (Rs >= Rt) {
 578     MI.setOpcode(Mips::BNVC);
 579     HasRs = true;
 580   } else if (Rs != 0 && Rs < Rt) {
 581     MI.setOpcode(Mips::BNEC);
 582     HasRs = true;
 583   } else
 584     MI.setOpcode(Mips::BNEZALC);
 585
 586   if (HasRs)
 587     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 588                                        Rs)));
 589
 590   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 591                                      Rt)));
 592   MI.addOperand(MCOperand::CreateImm(Imm));
 593
 594   return MCDisassembler::Success;
 595 }
 596
 597 template <typename InsnType>
 598 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 599                                            uint64_t Address,
 600                                            const void *Decoder) {
 601   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 602   // (otherwise we would have matched the BLEZL instruction from the earlier
 603   // ISA's instead).
 604   //
 605   // We have:
 606   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 607   //      Invalid if rs == 0
 608   //      BLEZC   if rs == 0  && rt != 0
 609   //      BGEZC   if rs == rt && rt != 0
 610   //      BGEC    if rs != rt && rs != 0  && rt != 0
 611
 612   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 613   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 614   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 615   bool HasRs = false;
 616
 617   if (Rt == 0)
 618     return MCDisassembler::Fail;
 619   else if (Rs == 0)
 620     MI.setOpcode(Mips::BLEZC);
 621   else if (Rs == Rt)
 622     MI.setOpcode(Mips::BGEZC);
 623   else {
 624     HasRs = true;
 625     MI.setOpcode(Mips::BGEC);
 626   }
 627
 628   if (HasRs)
 629     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 630                                        Rs)));
 631
 632   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 633                                      Rt)));
 634
 635   MI.addOperand(MCOperand::CreateImm(Imm));
 636
 637   return MCDisassembler::Success;
 638 }
 639
 640 template <typename InsnType>
 641 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 642                                            uint64_t Address,
 643                                            const void *Decoder) {
 644   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 645   // (otherwise we would have matched the BGTZL instruction from the earlier
 646   // ISA's instead).
 647   //
 648   // We have:
 649   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 650   //      Invalid if rs == 0
 651   //      BGTZC   if rs == 0  && rt != 0
 652   //      BLTZC   if rs == rt && rt != 0
 653   //      BLTC    if rs != rt && rs != 0  && rt != 0
 654
 655   bool HasRs = false;
 656
 657   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 658   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 659   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 660
 661   if (Rt == 0)
 662     return MCDisassembler::Fail;
 663   else if (Rs == 0)
 664     MI.setOpcode(Mips::BGTZC);
 665   else if (Rs == Rt)
 666     MI.setOpcode(Mips::BLTZC);
 667   else {
 668     MI.setOpcode(Mips::BLTC);
 669     HasRs = true;
 670   }
 671
 672   if (HasRs)
 673     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 674                                               Rs)));
 675
 676   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 677                                      Rt)));
 678
 679   MI.addOperand(MCOperand::CreateImm(Imm));
 680
 681   return MCDisassembler::Success;
 682 }
 683
 684 template <typename InsnType>
 685 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 686                                           uint64_t Address,
 687                                           const void *Decoder) {
 688   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 689   // (otherwise we would have matched the BGTZ instruction from the earlier
 690   // ISA's instead).
 691   //
 692   // We have:
 693   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 694   //      BGTZ    if rt == 0
 695   //      BGTZALC if rs == 0 && rt != 0
 696   //      BLTZALC if rs != 0 && rs == rt
 697   //      BLTUC   if rs != 0 && rs != rt
 698
 699   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 700   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 701   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 702   bool HasRs = false;
 703   bool HasRt = false;
 704
 705   if (Rt == 0) {
 706     MI.setOpcode(Mips::BGTZ);
 707     HasRs = true;
 708   } else if (Rs == 0) {
 709     MI.setOpcode(Mips::BGTZALC);
 710     HasRt = true;
 711   } else if (Rs == Rt) {
 712     MI.setOpcode(Mips::BLTZALC);
 713     HasRs = true;
 714   } else {
 715     MI.setOpcode(Mips::BLTUC);
 716     HasRs = true;
 717     HasRt = true;
 718   }
 719
 720   if (HasRs)
 721     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 722                                        Rs)));
 723
 724   if (HasRt)
 725     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 726                                        Rt)));
 727
 728   MI.addOperand(MCOperand::CreateImm(Imm));
 729
 730   return MCDisassembler::Success;
 731 }
 732
 733 template <typename InsnType>
 734 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 735                                            uint64_t Address,
 736                                            const void *Decoder) {
 737   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 738   // (otherwise we would have matched the BLEZL instruction from the earlier
 739   // ISA's instead).
 740   //
 741   // We have:
 742   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 743   //      Invalid   if rs == 0
 744   //      BLEZALC   if rs == 0  && rt != 0
 745   //      BGEZALC   if rs == rt && rt != 0
 746   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 747
 748   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 749   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 750   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 751   bool HasRs = false;
 752
 753   if (Rt == 0)
 754     return MCDisassembler::Fail;
 755   else if (Rs == 0)
 756     MI.setOpcode(Mips::BLEZALC);
 757   else if (Rs == Rt)
 758     MI.setOpcode(Mips::BGEZALC);
 759   else {
 760     HasRs = true;
 761     MI.setOpcode(Mips::BGEUC);
 762   }
 763
 764   if (HasRs)
 765     MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 766                                        Rs)));
 767   MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
 768                                      Rt)));
 769
 770   MI.addOperand(MCOperand::CreateImm(Imm));
 771
 772   return MCDisassembler::Success;
 773 }
 774
 775 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 776 /// according to the given endianess.
 777 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 778                                       uint64_t &Size, uint32_t &Insn,
 779                                       bool IsBigEndian) {
 780   // We want to read exactly 2 Bytes of data.
 781   if (Bytes.size() < 2) {
 782     Size = 0;
 783     return MCDisassembler::Fail;
 784   }
 785
 786   if (IsBigEndian) {
 787     Insn = (Bytes[0] << 8) | Bytes[1];
 788   } else {
 789     Insn = (Bytes[1] << 8) | Bytes[0];
 790   }
 791
 792   return MCDisassembler::Success;
 793 }
 794
 795 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 796 /// according to the given endianess
 797 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 798                                       uint64_t &Size, uint32_t &Insn,
 799                                       bool IsBigEndian, bool IsMicroMips) {
 800   // We want to read exactly 4 Bytes of data.
 801   if (Bytes.size() < 4) {
 802     Size = 0;
 803     return MCDisassembler::Fail;
 804   }
 805
 806   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 807   // always precede the low 16 bits in the instruction stream (that is, they
 808   // are placed at lower addresses in the instruction stream).
 809   //
 810   // microMIPS byte ordering:
 811   //   Big-endian:    0 | 1 | 2 | 3
 812   //   Little-endian: 1 | 0 | 3 | 2
 813
 814   if (IsBigEndian) {
 815     // Encoded as a big-endian 32-bit word in the stream.
 816     Insn =
 817         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 818   } else {
 819     if (IsMicroMips) {
 820       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 821              (Bytes[1] << 24);
 822     } else {
 823       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 824              (Bytes[3] << 24);
 825     }
 826   }
 827
 828   return MCDisassembler::Success;
 829 }
 830
 831 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 832                                               ArrayRef<uint8_t> Bytes,
 833                                               uint64_t Address,
 834                                               raw_ostream &VStream,
 835                                               raw_ostream &CStream) const {
 836   uint32_t Insn;
 837   DecodeStatus Result;
 838
 839   if (IsMicroMips) {
 840     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 841
 842     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 843     // Calling the auto-generated decoder function.
 844     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 845                                this, STI);
 846     if (Result != MCDisassembler::Fail) {
 847       Size = 2;
 848       return Result;
 849     }
 850
 851     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 852     if (Result == MCDisassembler::Fail)
 853       return MCDisassembler::Fail;
 854
 855     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 856     // Calling the auto-generated decoder function.
 857     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 858                                this, STI);
 859     if (Result != MCDisassembler::Fail) {
 860       Size = 4;
 861       return Result;
 862     }
 863     return MCDisassembler::Fail;
 864   }
 865
 866   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 867   if (Result == MCDisassembler::Fail)
 868     return MCDisassembler::Fail;
 869
 870   if (hasCOP3()) {
 871     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 872     Result =
 873         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 874     if (Result != MCDisassembler::Fail) {
 875       Size = 4;
 876       return Result;
 877     }
 878   }
 879
 880   if (hasMips32r6() && isGP64()) {
 881     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 882     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 883                                Address, this, STI);
 884     if (Result != MCDisassembler::Fail) {
 885       Size = 4;
 886       return Result;
 887     }
 888   }
 889
 890   if (hasMips32r6()) {
 891     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 892     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 893                                Address, this, STI);
 894     if (Result != MCDisassembler::Fail) {
 895       Size = 4;
 896       return Result;
 897     }
 898   }
 899
 900   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 901   // Calling the auto-generated decoder function.
 902   Result =
 903       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 904   if (Result != MCDisassembler::Fail) {
 905     Size = 4;
 906     return Result;
 907   }
 908
 909   return MCDisassembler::Fail;
 910 }
 911
 912 DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 913                                                 ArrayRef<uint8_t> Bytes,
 914                                                 uint64_t Address,
 915                                                 raw_ostream &VStream,
 916                                                 raw_ostream &CStream) const {
 917   uint32_t Insn;
 918
 919   DecodeStatus Result =
 920       readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 921   if (Result == MCDisassembler::Fail)
 922     return MCDisassembler::Fail;
 923
 924   // Calling the auto-generated decoder function.
 925   Result =
 926       decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI);
 927   if (Result != MCDisassembler::Fail) {
 928     Size = 4;
 929     return Result;
 930   }
 931   // If we fail to decode in Mips64 decoder space we can try in Mips32
 932   Result =
 933       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 934   if (Result != MCDisassembler::Fail) {
 935     Size = 4;
 936     return Result;
 937   }
 938
 939   return MCDisassembler::Fail;
 940 }
 941
 942 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 943                                                  unsigned RegNo,
 944                                                  uint64_t Address,
 945                                                  const void *Decoder) {
 946
 947   return MCDisassembler::Fail;
 948
 949 }
 950
 951 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 952                                              unsigned RegNo,
 953                                              uint64_t Address,
 954                                              const void *Decoder) {
 955
 956   if (RegNo > 31)
 957     return MCDisassembler::Fail;
 958
 959   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
 960   Inst.addOperand(MCOperand::CreateReg(Reg));
 961   return MCDisassembler::Success;
 962 }
 963
 964 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
 965                                                unsigned RegNo,
 966                                                uint64_t Address,
 967                                                const void *Decoder) {
 968   if (RegNo > 7)
 969     return MCDisassembler::Fail;
 970   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
 971   Inst.addOperand(MCOperand::CreateReg(Reg));
 972   return MCDisassembler::Success;
 973 }
 974
 975 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
 976                                                    unsigned RegNo,
 977                                                    uint64_t Address,
 978                                                    const void *Decoder) {
 979   if (RegNo > 7)
 980     return MCDisassembler::Fail;
 981   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
 982   Inst.addOperand(MCOperand::CreateReg(Reg));
 983   return MCDisassembler::Success;
 984 }
 985
 986 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
 987                                              unsigned RegNo,
 988                                              uint64_t Address,
 989                                              const void *Decoder) {
 990   if (RegNo > 31)
 991     return MCDisassembler::Fail;
 992   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
 993   Inst.addOperand(MCOperand::CreateReg(Reg));
 994   return MCDisassembler::Success;
 995 }
 996
 997 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
 998                                            unsigned RegNo,
 999                                            uint64_t Address,
1000                                            const void *Decoder) {
1001   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64Bit())
1002     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1003
1004   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1005 }
1006
1007 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1008                                             unsigned RegNo,
1009                                             uint64_t Address,
1010                                             const void *Decoder) {
1011   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1012 }
1013
1014 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1015                                              unsigned RegNo,
1016                                              uint64_t Address,
1017                                              const void *Decoder) {
1018   if (RegNo > 31)
1019     return MCDisassembler::Fail;
1020
1021   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1022   Inst.addOperand(MCOperand::CreateReg(Reg));
1023   return MCDisassembler::Success;
1024 }
1025
1026 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1027                                              unsigned RegNo,
1028                                              uint64_t Address,
1029                                              const void *Decoder) {
1030   if (RegNo > 31)
1031     return MCDisassembler::Fail;
1032
1033   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1034   Inst.addOperand(MCOperand::CreateReg(Reg));
1035   return MCDisassembler::Success;
1036 }
1037
1038 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1039                                            unsigned RegNo,
1040                                            uint64_t Address,
1041                                            const void *Decoder) {
1042   if (RegNo > 31)
1043     return MCDisassembler::Fail;
1044   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1045   Inst.addOperand(MCOperand::CreateReg(Reg));
1046   return MCDisassembler::Success;
1047 }
1048
1049 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1050                                            unsigned RegNo,
1051                                            uint64_t Address,
1052                                            const void *Decoder) {
1053   if (RegNo > 7)
1054     return MCDisassembler::Fail;
1055   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1056   Inst.addOperand(MCOperand::CreateReg(Reg));
1057   return MCDisassembler::Success;
1058 }
1059
1060 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1061                                              uint64_t Address,
1062                                              const void *Decoder) {
1063   if (RegNo > 31)
1064     return MCDisassembler::Fail;
1065
1066   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1067   Inst.addOperand(MCOperand::CreateReg(Reg));
1068   return MCDisassembler::Success;
1069 }
1070
1071 static DecodeStatus DecodeMem(MCInst &Inst,
1072                               unsigned Insn,
1073                               uint64_t Address,
1074                               const void *Decoder) {
1075   int Offset = SignExtend32<16>(Insn & 0xffff);
1076   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1077   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1078
1079   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1080   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1081
1082   if(Inst.getOpcode() == Mips::SC ||
1083      Inst.getOpcode() == Mips::SCD){
1084     Inst.addOperand(MCOperand::CreateReg(Reg));
1085   }
1086
1087   Inst.addOperand(MCOperand::CreateReg(Reg));
1088   Inst.addOperand(MCOperand::CreateReg(Base));
1089   Inst.addOperand(MCOperand::CreateImm(Offset));
1090
1091   return MCDisassembler::Success;
1092 }
1093
1094 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1095                               unsigned Insn,
1096                               uint64_t Address,
1097                               const void *Decoder) {
1098   int Offset = SignExtend32<16>(Insn & 0xffff);
1099   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1100   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1101
1102   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1103
1104   Inst.addOperand(MCOperand::CreateReg(Base));
1105   Inst.addOperand(MCOperand::CreateImm(Offset));
1106   Inst.addOperand(MCOperand::CreateImm(Hint));
1107
1108   return MCDisassembler::Success;
1109 }
1110
1111 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1112                                     unsigned Insn,
1113                                     uint64_t Address,
1114                                     const void *Decoder) {
1115   int Offset = SignExtend32<12>(Insn & 0xfff);
1116   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1117   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1118
1119   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1120
1121   Inst.addOperand(MCOperand::CreateReg(Base));
1122   Inst.addOperand(MCOperand::CreateImm(Offset));
1123   Inst.addOperand(MCOperand::CreateImm(Hint));
1124
1125   return MCDisassembler::Success;
1126 }
1127
1128 static DecodeStatus DecodeSyncI(MCInst &Inst,
1129                               unsigned Insn,
1130                               uint64_t Address,
1131                               const void *Decoder) {
1132   int Offset = SignExtend32<16>(Insn & 0xffff);
1133   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1134
1135   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1136
1137   Inst.addOperand(MCOperand::CreateReg(Base));
1138   Inst.addOperand(MCOperand::CreateImm(Offset));
1139
1140   return MCDisassembler::Success;
1141 }
1142
1143 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1144                                     uint64_t Address, const void *Decoder) {
1145   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1146   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1147   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1148
1149   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1150   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1151
1152   Inst.addOperand(MCOperand::CreateReg(Reg));
1153   Inst.addOperand(MCOperand::CreateReg(Base));
1154
1155   // The immediate field of an LD/ST instruction is scaled which means it must
1156   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1157   // data format.
1158   // .b - 1 byte
1159   // .h - 2 bytes
1160   // .w - 4 bytes
1161   // .d - 8 bytes
1162   switch(Inst.getOpcode())
1163   {
1164   default:
1165     assert (0 && "Unexpected instruction");
1166     return MCDisassembler::Fail;
1167     break;
1168   case Mips::LD_B:
1169   case Mips::ST_B:
1170     Inst.addOperand(MCOperand::CreateImm(Offset));
1171     break;
1172   case Mips::LD_H:
1173   case Mips::ST_H:
1174     Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1175     break;
1176   case Mips::LD_W:
1177   case Mips::ST_W:
1178     Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1179     break;
1180   case Mips::LD_D:
1181   case Mips::ST_D:
1182     Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1183     break;
1184   }
1185
1186   return MCDisassembler::Success;
1187 }
1188
1189 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1190                                     unsigned Insn,
1191                                     uint64_t Address,
1192                                     const void *Decoder) {
1193   unsigned Offset = Insn & 0xf;
1194   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1195   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1196
1197   switch (Inst.getOpcode()) {
1198     case Mips::LBU16_MM:
1199     case Mips::LHU16_MM:
1200     case Mips::LW16_MM:
1201       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1202             == MCDisassembler::Fail)
1203         return MCDisassembler::Fail;
1204       break;
1205     case Mips::SB16_MM:
1206     case Mips::SH16_MM:
1207     case Mips::SW16_MM:
1208       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1209             == MCDisassembler::Fail)
1210         return MCDisassembler::Fail;
1211       break;
1212   }
1213
1214   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1215         == MCDisassembler::Fail)
1216     return MCDisassembler::Fail;
1217
1218   switch (Inst.getOpcode()) {
1219     case Mips::LBU16_MM:
1220       if (Offset == 0xf)
1221         Inst.addOperand(MCOperand::CreateImm(-1));
1222       else
1223         Inst.addOperand(MCOperand::CreateImm(Offset));
1224       break;
1225     case Mips::SB16_MM:
1226       Inst.addOperand(MCOperand::CreateImm(Offset));
1227       break;
1228     case Mips::LHU16_MM:
1229     case Mips::SH16_MM:
1230       Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1231       break;
1232     case Mips::LW16_MM:
1233     case Mips::SW16_MM:
1234       Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1235       break;
1236   }
1237
1238   return MCDisassembler::Success;
1239 }
1240
1241 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1242                                           unsigned Insn,
1243                                           uint64_t Address,
1244                                           const void *Decoder) {
1245   unsigned Offset = Insn & 0x1F;
1246   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1247
1248   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1249
1250   Inst.addOperand(MCOperand::CreateReg(Reg));
1251   Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1252   Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1253
1254   return MCDisassembler::Success;
1255 }
1256
1257 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1258                                      unsigned Insn,
1259                                      uint64_t Address,
1260                                      const void *Decoder) {
1261   int Offset = SignExtend32<12>(Insn & 0x0fff);
1262   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1263   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1264
1265   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1266   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1267
1268   switch (Inst.getOpcode()) {
1269   case Mips::SWM32_MM:
1270   case Mips::LWM32_MM:
1271     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1272         == MCDisassembler::Fail)
1273       return MCDisassembler::Fail;
1274     Inst.addOperand(MCOperand::CreateReg(Base));
1275     Inst.addOperand(MCOperand::CreateImm(Offset));
1276     break;
1277   case Mips::SC_MM:
1278     Inst.addOperand(MCOperand::CreateReg(Reg));
1279     // fallthrough
1280   default:
1281     Inst.addOperand(MCOperand::CreateReg(Reg));
1282     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1283       Inst.addOperand(MCOperand::CreateReg(Reg+1));
1284
1285     Inst.addOperand(MCOperand::CreateReg(Base));
1286     Inst.addOperand(MCOperand::CreateImm(Offset));
1287   }
1288
1289   return MCDisassembler::Success;
1290 }
1291
1292 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1293                                      unsigned Insn,
1294                                      uint64_t Address,
1295                                      const void *Decoder) {
1296   int Offset = SignExtend32<16>(Insn & 0xffff);
1297   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1298   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1299
1300   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1301   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1302
1303   Inst.addOperand(MCOperand::CreateReg(Reg));
1304   Inst.addOperand(MCOperand::CreateReg(Base));
1305   Inst.addOperand(MCOperand::CreateImm(Offset));
1306
1307   return MCDisassembler::Success;
1308 }
1309
1310 static DecodeStatus DecodeFMem(MCInst &Inst,
1311                                unsigned Insn,
1312                                uint64_t Address,
1313                                const void *Decoder) {
1314   int Offset = SignExtend32<16>(Insn & 0xffff);
1315   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1316   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1317
1318   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1319   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1320
1321   Inst.addOperand(MCOperand::CreateReg(Reg));
1322   Inst.addOperand(MCOperand::CreateReg(Base));
1323   Inst.addOperand(MCOperand::CreateImm(Offset));
1324
1325   return MCDisassembler::Success;
1326 }
1327
1328 static DecodeStatus DecodeFMem2(MCInst &Inst,
1329                                unsigned Insn,
1330                                uint64_t Address,
1331                                const void *Decoder) {
1332   int Offset = SignExtend32<16>(Insn & 0xffff);
1333   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1334   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1335
1336   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1337   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1338
1339   Inst.addOperand(MCOperand::CreateReg(Reg));
1340   Inst.addOperand(MCOperand::CreateReg(Base));
1341   Inst.addOperand(MCOperand::CreateImm(Offset));
1342
1343   return MCDisassembler::Success;
1344 }
1345
1346 static DecodeStatus DecodeFMem3(MCInst &Inst,
1347                                unsigned Insn,
1348                                uint64_t Address,
1349                                const void *Decoder) {
1350   int Offset = SignExtend32<16>(Insn & 0xffff);
1351   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1352   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1353
1354   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1355   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1356
1357   Inst.addOperand(MCOperand::CreateReg(Reg));
1358   Inst.addOperand(MCOperand::CreateReg(Base));
1359   Inst.addOperand(MCOperand::CreateImm(Offset));
1360
1361   return MCDisassembler::Success;
1362 }
1363
1364 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1365                                        unsigned Insn,
1366                                        uint64_t Address,
1367                                        const void *Decoder) {
1368   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1369   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1370   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1371
1372   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1373   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1374
1375   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1376     Inst.addOperand(MCOperand::CreateReg(Rt));
1377   }
1378
1379   Inst.addOperand(MCOperand::CreateReg(Rt));
1380   Inst.addOperand(MCOperand::CreateReg(Base));
1381   Inst.addOperand(MCOperand::CreateImm(Offset));
1382
1383   return MCDisassembler::Success;
1384 }
1385
1386 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1387                                               unsigned RegNo,
1388                                               uint64_t Address,
1389                                               const void *Decoder) {
1390   // Currently only hardware register 29 is supported.
1391   if (RegNo != 29)
1392     return  MCDisassembler::Fail;
1393   Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1394   return MCDisassembler::Success;
1395 }
1396
1397 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1398                                               unsigned RegNo,
1399                                               uint64_t Address,
1400                                               const void *Decoder) {
1401   if (RegNo > 30 || RegNo %2)
1402     return MCDisassembler::Fail;
1403
1404   ;
1405   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1406   Inst.addOperand(MCOperand::CreateReg(Reg));
1407   return MCDisassembler::Success;
1408 }
1409
1410 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1411                                                 unsigned RegNo,
1412                                                 uint64_t Address,
1413                                                 const void *Decoder) {
1414   if (RegNo >= 4)
1415     return MCDisassembler::Fail;
1416
1417   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1418   Inst.addOperand(MCOperand::CreateReg(Reg));
1419   return MCDisassembler::Success;
1420 }
1421
1422 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1423                                                unsigned RegNo,
1424                                                uint64_t Address,
1425                                                const void *Decoder) {
1426   if (RegNo >= 4)
1427     return MCDisassembler::Fail;
1428
1429   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1430   Inst.addOperand(MCOperand::CreateReg(Reg));
1431   return MCDisassembler::Success;
1432 }
1433
1434 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1435                                                unsigned RegNo,
1436                                                uint64_t Address,
1437                                                const void *Decoder) {
1438   if (RegNo >= 4)
1439     return MCDisassembler::Fail;
1440
1441   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1442   Inst.addOperand(MCOperand::CreateReg(Reg));
1443   return MCDisassembler::Success;
1444 }
1445
1446 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1447                                                unsigned RegNo,
1448                                                uint64_t Address,
1449                                                const void *Decoder) {
1450   if (RegNo > 31)
1451     return MCDisassembler::Fail;
1452
1453   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1454   Inst.addOperand(MCOperand::CreateReg(Reg));
1455   return MCDisassembler::Success;
1456 }
1457
1458 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1459                                                unsigned RegNo,
1460                                                uint64_t Address,
1461                                                const void *Decoder) {
1462   if (RegNo > 31)
1463     return MCDisassembler::Fail;
1464
1465   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1466   Inst.addOperand(MCOperand::CreateReg(Reg));
1467   return MCDisassembler::Success;
1468 }
1469
1470 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1471                                                unsigned RegNo,
1472                                                uint64_t Address,
1473                                                const void *Decoder) {
1474   if (RegNo > 31)
1475     return MCDisassembler::Fail;
1476
1477   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1478   Inst.addOperand(MCOperand::CreateReg(Reg));
1479   return MCDisassembler::Success;
1480 }
1481
1482 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1483                                                unsigned RegNo,
1484                                                uint64_t Address,
1485                                                const void *Decoder) {
1486   if (RegNo > 31)
1487     return MCDisassembler::Fail;
1488
1489   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1490   Inst.addOperand(MCOperand::CreateReg(Reg));
1491   return MCDisassembler::Success;
1492 }
1493
1494 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1495                                                unsigned RegNo,
1496                                                uint64_t Address,
1497                                                const void *Decoder) {
1498   if (RegNo > 7)
1499     return MCDisassembler::Fail;
1500
1501   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1502   Inst.addOperand(MCOperand::CreateReg(Reg));
1503   return MCDisassembler::Success;
1504 }
1505
1506 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1507                                             unsigned RegNo,
1508                                             uint64_t Address,
1509                                             const void *Decoder) {
1510   if (RegNo > 31)
1511     return MCDisassembler::Fail;
1512
1513   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1514   Inst.addOperand(MCOperand::CreateReg(Reg));
1515   return MCDisassembler::Success;
1516 }
1517
1518 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1519                                        unsigned Offset,
1520                                        uint64_t Address,
1521                                        const void *Decoder) {
1522   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1523   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1524   return MCDisassembler::Success;
1525 }
1526
1527 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1528                                      unsigned Insn,
1529                                      uint64_t Address,
1530                                      const void *Decoder) {
1531
1532   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1533   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1534   return MCDisassembler::Success;
1535 }
1536
1537 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1538                                          unsigned Offset,
1539                                          uint64_t Address,
1540                                          const void *Decoder) {
1541   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1542
1543   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1544   return MCDisassembler::Success;
1545 }
1546
1547 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1548                                          unsigned Offset,
1549                                          uint64_t Address,
1550                                          const void *Decoder) {
1551   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1552
1553   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1554   return MCDisassembler::Success;
1555 }
1556
1557 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1558                                           unsigned Offset,
1559                                           uint64_t Address,
1560                                           const void *Decoder) {
1561   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1562   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1563   return MCDisassembler::Success;
1564 }
1565
1566 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1567                                            unsigned Offset,
1568                                            uint64_t Address,
1569                                            const void *Decoder) {
1570   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1571   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1572   return MCDisassembler::Success;
1573 }
1574
1575 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1576                                          unsigned Offset,
1577                                          uint64_t Address,
1578                                          const void *Decoder) {
1579   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1580   Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1581   return MCDisassembler::Success;
1582 }
1583
1584 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1585                                        unsigned Insn,
1586                                        uint64_t Address,
1587                                        const void *Decoder) {
1588   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1589   Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1590   return MCDisassembler::Success;
1591 }
1592
1593 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1594                                        unsigned Value,
1595                                        uint64_t Address,
1596                                        const void *Decoder) {
1597   if (Value == 0)
1598     Inst.addOperand(MCOperand::CreateImm(1));
1599   else if (Value == 0x7)
1600     Inst.addOperand(MCOperand::CreateImm(-1));
1601   else
1602     Inst.addOperand(MCOperand::CreateImm(Value << 2));
1603   return MCDisassembler::Success;
1604 }
1605
1606 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1607                                     unsigned Value,
1608                                     uint64_t Address,
1609                                     const void *Decoder) {
1610   Inst.addOperand(MCOperand::CreateImm(Value << 2));
1611   return MCDisassembler::Success;
1612 }
1613
1614 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1615                                   unsigned Value,
1616                                   uint64_t Address,
1617                                   const void *Decoder) {
1618   if (Value == 0x7F)
1619     Inst.addOperand(MCOperand::CreateImm(-1));
1620   else
1621     Inst.addOperand(MCOperand::CreateImm(Value));
1622   return MCDisassembler::Success;
1623 }
1624
1625 static DecodeStatus DecodeSimm4(MCInst &Inst,
1626                                 unsigned Value,
1627                                 uint64_t Address,
1628                                 const void *Decoder) {
1629   Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1630   return MCDisassembler::Success;
1631 }
1632
1633 static DecodeStatus DecodeSimm16(MCInst &Inst,
1634                                  unsigned Insn,
1635                                  uint64_t Address,
1636                                  const void *Decoder) {
1637   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1638   return MCDisassembler::Success;
1639 }
1640
1641 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1642                                  unsigned Insn,
1643                                  uint64_t Address,
1644                                  const void *Decoder) {
1645   // We add one to the immediate field as it was encoded as 'imm - 1'.
1646   Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1647   return MCDisassembler::Success;
1648 }
1649
1650 static DecodeStatus DecodeInsSize(MCInst &Inst,
1651                                   unsigned Insn,
1652                                   uint64_t Address,
1653                                   const void *Decoder) {
1654   // First we need to grab the pos(lsb) from MCInst.
1655   int Pos = Inst.getOperand(2).getImm();
1656   int Size = (int) Insn - Pos + 1;
1657   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1658   return MCDisassembler::Success;
1659 }
1660
1661 static DecodeStatus DecodeExtSize(MCInst &Inst,
1662                                   unsigned Insn,
1663                                   uint64_t Address,
1664                                   const void *Decoder) {
1665   int Size = (int) Insn  + 1;
1666   Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1667   return MCDisassembler::Success;
1668 }
1669
1670 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1671                                      uint64_t Address, const void *Decoder) {
1672   Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1673   return MCDisassembler::Success;
1674 }
1675
1676 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1677                                      uint64_t Address, const void *Decoder) {
1678   Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1679   return MCDisassembler::Success;
1680 }
1681
1682 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1683                                   uint64_t Address, const void *Decoder) {
1684   int32_t DecodedValue;
1685   switch (Insn) {
1686   case 0: DecodedValue = 256; break;
1687   case 1: DecodedValue = 257; break;
1688   case 510: DecodedValue = -258; break;
1689   case 511: DecodedValue = -257; break;
1690   default: DecodedValue = SignExtend32<9>(Insn); break;
1691   }
1692   Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1693   return MCDisassembler::Success;
1694 }
1695
1696 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1697                                     uint64_t Address, const void *Decoder) {
1698   // Insn must be >= 0, since it is unsigned that condition is always true.
1699   assert(Insn < 16);
1700   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1701                              255, 32768, 65535};
1702   Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1703   return MCDisassembler::Success;
1704 }
1705
1706 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1707                                     uint64_t Address, const void *Decoder) {
1708   Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1709   return MCDisassembler::Success;
1710 }
1711
1712 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1713                                          unsigned Insn,
1714                                          uint64_t Address,
1715                                          const void *Decoder) {
1716   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1717                      Mips::S6, Mips::FP};
1718   unsigned RegNum;
1719
1720   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1721   // Empty register lists are not allowed.
1722   if (RegLst == 0)
1723     return MCDisassembler::Fail;
1724
1725   RegNum = RegLst & 0xf;
1726   for (unsigned i = 0; i < RegNum; i++)
1727     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1728
1729   if (RegLst & 0x10)
1730     Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1731
1732   return MCDisassembler::Success;
1733 }
1734
1735 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1736                                            uint64_t Address,
1737                                            const void *Decoder) {
1738   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1739   unsigned RegNum;
1740
1741   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1742   // Empty register lists are not allowed.
1743   if (RegLst == 0)
1744     return MCDisassembler::Fail;
1745
1746   RegNum = RegLst & 0x3;
1747   for (unsigned i = 0; i < RegNum - 1; i++)
1748     Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1749
1750   Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1751
1752   return MCDisassembler::Success;
1753 }