lib/Target/Mips/Disassembler/MipsDisassembler.cpp

   1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file is part of the Mips Disassembler.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Mips.h"
  15 #include "MipsRegisterInfo.h"
  16 #include "MipsSubtarget.h"
  17 #include "llvm/MC/MCContext.h"
  18 #include "llvm/MC/MCDisassembler.h"
  19 #include "llvm/MC/MCFixedLenDisassembler.h"
  20 #include "llvm/MC/MCInst.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 #define DEBUG_TYPE "mips-disassembler"
  28
  29 typedef MCDisassembler::DecodeStatus DecodeStatus;
  30
  31 namespace {
  32
  33 class MipsDisassembler : public MCDisassembler {
  34   bool IsMicroMips;
  35   bool IsBigEndian;
  36 public:
  37   MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
  38       : MCDisassembler(STI, Ctx),
  39         IsMicroMips(STI.getFeatureBits()[Mips::FeatureMicroMips]),
  40         IsBigEndian(IsBigEndian) {}
  41
  42   bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
  43   bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
  44   bool hasMips32r6() const {
  45     return STI.getFeatureBits()[Mips::FeatureMips32r6];
  46   }
  47
  48   bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
  49
  50   bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
  51
  52   bool hasCOP3() const {
  53     // Only present in MIPS-I and MIPS-II
  54     return !hasMips32() && !hasMips3();
  55   }
  56
  57   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  58                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  59                               raw_ostream &VStream,
  60                               raw_ostream &CStream) const override;
  61 };
  62
  63 } // end anonymous namespace
  64
  65 // Forward declare these because the autogenerated code will reference them.
  66 // Definitions are further down.
  67 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
  68                                              unsigned RegNo,
  69                                              uint64_t Address,
  70                                              const void *Decoder);
  71
  72 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
  73                                                  unsigned RegNo,
  74                                                  uint64_t Address,
  75                                                  const void *Decoder);
  76
  77 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
  78                                                unsigned RegNo,
  79                                                uint64_t Address,
  80                                                const void *Decoder);
  81
  82 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
  83                                                    unsigned RegNo,
  84                                                    uint64_t Address,
  85                                                    const void *Decoder);
  86
  87 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
  88                                                     unsigned RegNo,
  89                                                     uint64_t Address,
  90                                                     const void *Decoder);
  91
  92 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
  93                                              unsigned RegNo,
  94                                              uint64_t Address,
  95                                              const void *Decoder);
  96
  97 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
  98                                            unsigned Insn,
  99                                            uint64_t Address,
 100                                            const void *Decoder);
 101
 102 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
 103                                             unsigned RegNo,
 104                                             uint64_t Address,
 105                                             const void *Decoder);
 106
 107 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
 108                                              unsigned RegNo,
 109                                              uint64_t Address,
 110                                              const void *Decoder);
 111
 112 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
 113                                              unsigned RegNo,
 114                                              uint64_t Address,
 115                                              const void *Decoder);
 116
 117 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
 118                                            unsigned RegNo,
 119                                            uint64_t Address,
 120                                            const void *Decoder);
 121
 122 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
 123                                            unsigned RegNo,
 124                                            uint64_t Address,
 125                                            const void *Decoder);
 126
 127 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
 128                                              uint64_t Address,
 129                                              const void *Decoder);
 130
 131 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
 132                                               unsigned Insn,
 133                                               uint64_t Address,
 134                                               const void *Decoder);
 135
 136 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
 137                                               unsigned RegNo,
 138                                               uint64_t Address,
 139                                               const void *Decoder);
 140
 141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
 142                                                 unsigned RegNo,
 143                                                 uint64_t Address,
 144                                                 const void *Decoder);
 145
 146 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
 147                                                unsigned RegNo,
 148                                                uint64_t Address,
 149                                                const void *Decoder);
 150
 151 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
 152                                                unsigned RegNo,
 153                                                uint64_t Address,
 154                                                const void *Decoder);
 155
 156 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
 157                                                unsigned RegNo,
 158                                                uint64_t Address,
 159                                                const void *Decoder);
 160
 161 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
 162                                                unsigned RegNo,
 163                                                uint64_t Address,
 164                                                const void *Decoder);
 165
 166 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
 167                                                unsigned RegNo,
 168                                                uint64_t Address,
 169                                                const void *Decoder);
 170
 171 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
 172                                                unsigned RegNo,
 173                                                uint64_t Address,
 174                                                const void *Decoder);
 175
 176 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
 177                                                unsigned RegNo,
 178                                                uint64_t Address,
 179                                                const void *Decoder);
 180
 181 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
 182                                             unsigned RegNo,
 183                                             uint64_t Address,
 184                                             const void *Decoder);
 185
 186 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
 187                                             unsigned RegNo,
 188                                             uint64_t Address,
 189                                             const void *Decoder);
 190
 191 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
 192                                        unsigned Offset,
 193                                        uint64_t Address,
 194                                        const void *Decoder);
 195
 196 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
 197                                      unsigned Insn,
 198                                      uint64_t Address,
 199                                      const void *Decoder);
 200
 201 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
 202                                          unsigned Offset,
 203                                          uint64_t Address,
 204                                          const void *Decoder);
 205
 206 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
 207                                          unsigned Offset,
 208                                          uint64_t Address,
 209                                          const void *Decoder);
 210
 211 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
 212 // shifted left by 1 bit.
 213 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
 214                                           unsigned Offset,
 215                                           uint64_t Address,
 216                                           const void *Decoder);
 217
 218 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
 219 // shifted left by 1 bit.
 220 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
 221                                            unsigned Offset,
 222                                            uint64_t Address,
 223                                            const void *Decoder);
 224
 225 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 226 // shifted left by 1 bit.
 227 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
 228                                          unsigned Offset,
 229                                          uint64_t Address,
 230                                          const void *Decoder);
 231
 232 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
 233 // shifted left by 1 bit.
 234 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
 235                                        unsigned Insn,
 236                                        uint64_t Address,
 237                                        const void *Decoder);
 238
 239 static DecodeStatus DecodeMem(MCInst &Inst,
 240                               unsigned Insn,
 241                               uint64_t Address,
 242                               const void *Decoder);
 243
 244 static DecodeStatus DecodeMemEVA(MCInst &Inst,
 245                                  unsigned Insn,
 246                                  uint64_t Address,
 247                                  const void *Decoder);
 248
 249 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
 250                                     unsigned Insn,
 251                                     uint64_t Address,
 252                                     const void *Decoder);
 253
 254 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
 255                                      unsigned Insn,
 256                                      uint64_t Address,
 257                                      const void *Decoder);
 258
 259 static DecodeStatus DecodeCacheOp(MCInst &Inst,
 260                               unsigned Insn,
 261                               uint64_t Address,
 262                               const void *Decoder);
 263
 264 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
 265                                              unsigned Insn,
 266                                              uint64_t Address,
 267                                              const void *Decoder);
 268
 269 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
 270                                     unsigned Insn,
 271                                     uint64_t Address,
 272                                     const void *Decoder);
 273
 274 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
 275                                        unsigned Insn,
 276                                        uint64_t Address,
 277                                        const void *Decoder);
 278
 279 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
 280                                     unsigned Insn,
 281                                     uint64_t Address,
 282                                     const void *Decoder);
 283
 284 static DecodeStatus DecodeSyncI(MCInst &Inst,
 285                                 unsigned Insn,
 286                                 uint64_t Address,
 287                                 const void *Decoder);
 288
 289 static DecodeStatus DecodeSynciR6(MCInst &Inst,
 290                                   unsigned Insn,
 291                                   uint64_t Address,
 292                                   const void *Decoder);
 293
 294 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
 295                                     uint64_t Address, const void *Decoder);
 296
 297 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
 298                                     unsigned Insn,
 299                                     uint64_t Address,
 300                                     const void *Decoder);
 301
 302 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
 303                                           unsigned Insn,
 304                                           uint64_t Address,
 305                                           const void *Decoder);
 306
 307 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
 308                                           unsigned Insn,
 309                                           uint64_t Address,
 310                                           const void *Decoder);
 311
 312 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
 313                                                unsigned Insn,
 314                                                uint64_t Address,
 315                                                const void *Decoder);
 316
 317 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
 318                                     unsigned Insn,
 319                                     uint64_t Address,
 320                                     const void *Decoder);
 321
 322 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
 323                                      unsigned Insn,
 324                                      uint64_t Address,
 325                                      const void *Decoder);
 326
 327 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
 328                                      unsigned Insn,
 329                                      uint64_t Address,
 330                                      const void *Decoder);
 331
 332 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
 333                                uint64_t Address,
 334                                const void *Decoder);
 335
 336 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
 337                                uint64_t Address,
 338                                const void *Decoder);
 339
 340 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
 341                                uint64_t Address,
 342                                const void *Decoder);
 343
 344 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
 345                                uint64_t Address,
 346                                const void *Decoder);
 347
 348 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
 349                                        unsigned Insn,
 350                                        uint64_t Address,
 351                                        const void *Decoder);
 352
 353 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
 354                                        unsigned Value,
 355                                        uint64_t Address,
 356                                        const void *Decoder);
 357
 358 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
 359                                     unsigned Value,
 360                                     uint64_t Address,
 361                                     const void *Decoder);
 362
 363 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
 364                                   unsigned Value,
 365                                   uint64_t Address,
 366                                   const void *Decoder);
 367
 368 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
 369                                               unsigned Value,
 370                                               uint64_t Address,
 371                                               const void *Decoder);
 372
 373 static DecodeStatus DecodeSimm4(MCInst &Inst,
 374                                 unsigned Value,
 375                                 uint64_t Address,
 376                                 const void *Decoder);
 377
 378 static DecodeStatus DecodeSimm16(MCInst &Inst,
 379                                  unsigned Insn,
 380                                  uint64_t Address,
 381                                  const void *Decoder);
 382
 383 // Decode the immediate field of an LSA instruction which
 384 // is off by one.
 385 static DecodeStatus DecodeLSAImm(MCInst &Inst,
 386                                  unsigned Insn,
 387                                  uint64_t Address,
 388                                  const void *Decoder);
 389
 390 static DecodeStatus DecodeInsSize(MCInst &Inst,
 391                                   unsigned Insn,
 392                                   uint64_t Address,
 393                                   const void *Decoder);
 394
 395 static DecodeStatus DecodeExtSize(MCInst &Inst,
 396                                   unsigned Insn,
 397                                   uint64_t Address,
 398                                   const void *Decoder);
 399
 400 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
 401                                      uint64_t Address, const void *Decoder);
 402
 403 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
 404                                      uint64_t Address, const void *Decoder);
 405
 406 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
 407                                   uint64_t Address, const void *Decoder);
 408
 409 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
 410                                     uint64_t Address, const void *Decoder);
 411
 412 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
 413                                    uint64_t Address, const void *Decoder);
 414
 415 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
 416                                      uint64_t Address, const void *Decoder);
 417
 418 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 419 /// handle.
 420 template <typename InsnType>
 421 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 422                                    const void *Decoder);
 423
 424 template <typename InsnType>
 425 static DecodeStatus
 426 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 427                       const void *Decoder);
 428
 429 template <typename InsnType>
 430 static DecodeStatus
 431 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 432                        const void *Decoder);
 433
 434 template <typename InsnType>
 435 static DecodeStatus
 436 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 437                        const void *Decoder);
 438
 439 template <typename InsnType>
 440 static DecodeStatus
 441 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 442                        const void *Decoder);
 443
 444 template <typename InsnType>
 445 static DecodeStatus
 446 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 447                       const void *Decoder);
 448
 449 template <typename InsnType>
 450 static DecodeStatus
 451 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
 452                        const void *Decoder);
 453
 454 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
 455                                          uint64_t Address,
 456                                          const void *Decoder);
 457
 458 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
 459                                            uint64_t Address,
 460                                            const void *Decoder);
 461
 462 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
 463                                        uint64_t Address,
 464                                        const void *Decoder);
 465
 466 namespace llvm {
 467 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
 468               TheMips64elTarget;
 469 }
 470
 471 static MCDisassembler *createMipsDisassembler(
 472                        const Target &T,
 473                        const MCSubtargetInfo &STI,
 474                        MCContext &Ctx) {
 475   return new MipsDisassembler(STI, Ctx, true);
 476 }
 477
 478 static MCDisassembler *createMipselDisassembler(
 479                        const Target &T,
 480                        const MCSubtargetInfo &STI,
 481                        MCContext &Ctx) {
 482   return new MipsDisassembler(STI, Ctx, false);
 483 }
 484
 485 extern "C" void LLVMInitializeMipsDisassembler() {
 486   // Register the disassembler.
 487   TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
 488                                          createMipsDisassembler);
 489   TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
 490                                          createMipselDisassembler);
 491   TargetRegistry::RegisterMCDisassembler(TheMips64Target,
 492                                          createMipsDisassembler);
 493   TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
 494                                          createMipselDisassembler);
 495 }
 496
 497 #include "MipsGenDisassemblerTables.inc"
 498
 499 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
 500   const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
 501   const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
 502   return *(RegInfo->getRegClass(RC).begin() + RegNo);
 503 }
 504
 505 template <typename InsnType>
 506 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
 507                                    const void *Decoder) {
 508   typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
 509   // The size of the n field depends on the element size
 510   // The register class also depends on this.
 511   InsnType tmp = fieldFromInstruction(insn, 17, 5);
 512   unsigned NSize = 0;
 513   DecodeFN RegDecoder = nullptr;
 514   if ((tmp & 0x18) == 0x00) { // INSVE_B
 515     NSize = 4;
 516     RegDecoder = DecodeMSA128BRegisterClass;
 517   } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
 518     NSize = 3;
 519     RegDecoder = DecodeMSA128HRegisterClass;
 520   } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
 521     NSize = 2;
 522     RegDecoder = DecodeMSA128WRegisterClass;
 523   } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
 524     NSize = 1;
 525     RegDecoder = DecodeMSA128DRegisterClass;
 526   } else
 527     llvm_unreachable("Invalid encoding");
 528
 529   assert(NSize != 0 && RegDecoder != nullptr);
 530
 531   // $wd
 532   tmp = fieldFromInstruction(insn, 6, 5);
 533   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 534     return MCDisassembler::Fail;
 535   // $wd_in
 536   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 537     return MCDisassembler::Fail;
 538   // $n
 539   tmp = fieldFromInstruction(insn, 16, NSize);
 540   MI.addOperand(MCOperand::createImm(tmp));
 541   // $ws
 542   tmp = fieldFromInstruction(insn, 11, 5);
 543   if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
 544     return MCDisassembler::Fail;
 545   // $n2
 546   MI.addOperand(MCOperand::createImm(0));
 547
 548   return MCDisassembler::Success;
 549 }
 550
 551 template <typename InsnType>
 552 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
 553                                           uint64_t Address,
 554                                           const void *Decoder) {
 555   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 556   // (otherwise we would have matched the ADDI instruction from the earlier
 557   // ISA's instead).
 558   //
 559   // We have:
 560   //    0b001000 sssss ttttt iiiiiiiiiiiiiiii
 561   //      BOVC if rs >= rt
 562   //      BEQZALC if rs == 0 && rt != 0
 563   //      BEQC if rs < rt && rs != 0
 564
 565   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 566   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 567   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 568   bool HasRs = false;
 569
 570   if (Rs >= Rt) {
 571     MI.setOpcode(Mips::BOVC);
 572     HasRs = true;
 573   } else if (Rs != 0 && Rs < Rt) {
 574     MI.setOpcode(Mips::BEQC);
 575     HasRs = true;
 576   } else
 577     MI.setOpcode(Mips::BEQZALC);
 578
 579   if (HasRs)
 580     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 581                                        Rs)));
 582
 583   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 584                                      Rt)));
 585   MI.addOperand(MCOperand::createImm(Imm));
 586
 587   return MCDisassembler::Success;
 588 }
 589
 590 template <typename InsnType>
 591 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
 592                                            uint64_t Address,
 593                                            const void *Decoder) {
 594   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 595   // (otherwise we would have matched the ADDI instruction from the earlier
 596   // ISA's instead).
 597   //
 598   // We have:
 599   //    0b011000 sssss ttttt iiiiiiiiiiiiiiii
 600   //      BNVC if rs >= rt
 601   //      BNEZALC if rs == 0 && rt != 0
 602   //      BNEC if rs < rt && rs != 0
 603
 604   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 605   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 606   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 607   bool HasRs = false;
 608
 609   if (Rs >= Rt) {
 610     MI.setOpcode(Mips::BNVC);
 611     HasRs = true;
 612   } else if (Rs != 0 && Rs < Rt) {
 613     MI.setOpcode(Mips::BNEC);
 614     HasRs = true;
 615   } else
 616     MI.setOpcode(Mips::BNEZALC);
 617
 618   if (HasRs)
 619     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 620                                        Rs)));
 621
 622   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 623                                      Rt)));
 624   MI.addOperand(MCOperand::createImm(Imm));
 625
 626   return MCDisassembler::Success;
 627 }
 628
 629 template <typename InsnType>
 630 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
 631                                            uint64_t Address,
 632                                            const void *Decoder) {
 633   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 634   // (otherwise we would have matched the BLEZL instruction from the earlier
 635   // ISA's instead).
 636   //
 637   // We have:
 638   //    0b010110 sssss ttttt iiiiiiiiiiiiiiii
 639   //      Invalid if rs == 0
 640   //      BLEZC   if rs == 0  && rt != 0
 641   //      BGEZC   if rs == rt && rt != 0
 642   //      BGEC    if rs != rt && rs != 0  && rt != 0
 643
 644   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 645   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 646   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 647   bool HasRs = false;
 648
 649   if (Rt == 0)
 650     return MCDisassembler::Fail;
 651   else if (Rs == 0)
 652     MI.setOpcode(Mips::BLEZC);
 653   else if (Rs == Rt)
 654     MI.setOpcode(Mips::BGEZC);
 655   else {
 656     HasRs = true;
 657     MI.setOpcode(Mips::BGEC);
 658   }
 659
 660   if (HasRs)
 661     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 662                                        Rs)));
 663
 664   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 665                                      Rt)));
 666
 667   MI.addOperand(MCOperand::createImm(Imm));
 668
 669   return MCDisassembler::Success;
 670 }
 671
 672 template <typename InsnType>
 673 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
 674                                            uint64_t Address,
 675                                            const void *Decoder) {
 676   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 677   // (otherwise we would have matched the BGTZL instruction from the earlier
 678   // ISA's instead).
 679   //
 680   // We have:
 681   //    0b010111 sssss ttttt iiiiiiiiiiiiiiii
 682   //      Invalid if rs == 0
 683   //      BGTZC   if rs == 0  && rt != 0
 684   //      BLTZC   if rs == rt && rt != 0
 685   //      BLTC    if rs != rt && rs != 0  && rt != 0
 686
 687   bool HasRs = false;
 688
 689   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 690   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 691   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 692
 693   if (Rt == 0)
 694     return MCDisassembler::Fail;
 695   else if (Rs == 0)
 696     MI.setOpcode(Mips::BGTZC);
 697   else if (Rs == Rt)
 698     MI.setOpcode(Mips::BLTZC);
 699   else {
 700     MI.setOpcode(Mips::BLTC);
 701     HasRs = true;
 702   }
 703
 704   if (HasRs)
 705     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 706                                               Rs)));
 707
 708   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 709                                      Rt)));
 710
 711   MI.addOperand(MCOperand::createImm(Imm));
 712
 713   return MCDisassembler::Success;
 714 }
 715
 716 template <typename InsnType>
 717 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
 718                                           uint64_t Address,
 719                                           const void *Decoder) {
 720   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 721   // (otherwise we would have matched the BGTZ instruction from the earlier
 722   // ISA's instead).
 723   //
 724   // We have:
 725   //    0b000111 sssss ttttt iiiiiiiiiiiiiiii
 726   //      BGTZ    if rt == 0
 727   //      BGTZALC if rs == 0 && rt != 0
 728   //      BLTZALC if rs != 0 && rs == rt
 729   //      BLTUC   if rs != 0 && rs != rt
 730
 731   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 732   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 733   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 734   bool HasRs = false;
 735   bool HasRt = false;
 736
 737   if (Rt == 0) {
 738     MI.setOpcode(Mips::BGTZ);
 739     HasRs = true;
 740   } else if (Rs == 0) {
 741     MI.setOpcode(Mips::BGTZALC);
 742     HasRt = true;
 743   } else if (Rs == Rt) {
 744     MI.setOpcode(Mips::BLTZALC);
 745     HasRs = true;
 746   } else {
 747     MI.setOpcode(Mips::BLTUC);
 748     HasRs = true;
 749     HasRt = true;
 750   }
 751
 752   if (HasRs)
 753     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 754                                        Rs)));
 755
 756   if (HasRt)
 757     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 758                                        Rt)));
 759
 760   MI.addOperand(MCOperand::createImm(Imm));
 761
 762   return MCDisassembler::Success;
 763 }
 764
 765 template <typename InsnType>
 766 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
 767                                            uint64_t Address,
 768                                            const void *Decoder) {
 769   // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
 770   // (otherwise we would have matched the BLEZL instruction from the earlier
 771   // ISA's instead).
 772   //
 773   // We have:
 774   //    0b000110 sssss ttttt iiiiiiiiiiiiiiii
 775   //      Invalid   if rs == 0
 776   //      BLEZALC   if rs == 0  && rt != 0
 777   //      BGEZALC   if rs == rt && rt != 0
 778   //      BGEUC     if rs != rt && rs != 0  && rt != 0
 779
 780   InsnType Rs = fieldFromInstruction(insn, 21, 5);
 781   InsnType Rt = fieldFromInstruction(insn, 16, 5);
 782   InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
 783   bool HasRs = false;
 784
 785   if (Rt == 0)
 786     return MCDisassembler::Fail;
 787   else if (Rs == 0)
 788     MI.setOpcode(Mips::BLEZALC);
 789   else if (Rs == Rt)
 790     MI.setOpcode(Mips::BGEZALC);
 791   else {
 792     HasRs = true;
 793     MI.setOpcode(Mips::BGEUC);
 794   }
 795
 796   if (HasRs)
 797     MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 798                                        Rs)));
 799   MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
 800                                      Rt)));
 801
 802   MI.addOperand(MCOperand::createImm(Imm));
 803
 804   return MCDisassembler::Success;
 805 }
 806
 807 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
 808 /// according to the given endianess.
 809 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
 810                                       uint64_t &Size, uint32_t &Insn,
 811                                       bool IsBigEndian) {
 812   // We want to read exactly 2 Bytes of data.
 813   if (Bytes.size() < 2) {
 814     Size = 0;
 815     return MCDisassembler::Fail;
 816   }
 817
 818   if (IsBigEndian) {
 819     Insn = (Bytes[0] << 8) | Bytes[1];
 820   } else {
 821     Insn = (Bytes[1] << 8) | Bytes[0];
 822   }
 823
 824   return MCDisassembler::Success;
 825 }
 826
 827 /// Read four bytes from the ArrayRef and return 32 bit word sorted
 828 /// according to the given endianess
 829 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
 830                                       uint64_t &Size, uint32_t &Insn,
 831                                       bool IsBigEndian, bool IsMicroMips) {
 832   // We want to read exactly 4 Bytes of data.
 833   if (Bytes.size() < 4) {
 834     Size = 0;
 835     return MCDisassembler::Fail;
 836   }
 837
 838   // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
 839   // always precede the low 16 bits in the instruction stream (that is, they
 840   // are placed at lower addresses in the instruction stream).
 841   //
 842   // microMIPS byte ordering:
 843   //   Big-endian:    0 | 1 | 2 | 3
 844   //   Little-endian: 1 | 0 | 3 | 2
 845
 846   if (IsBigEndian) {
 847     // Encoded as a big-endian 32-bit word in the stream.
 848     Insn =
 849         (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
 850   } else {
 851     if (IsMicroMips) {
 852       Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
 853              (Bytes[1] << 24);
 854     } else {
 855       Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
 856              (Bytes[3] << 24);
 857     }
 858   }
 859
 860   return MCDisassembler::Success;
 861 }
 862
 863 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
 864                                               ArrayRef<uint8_t> Bytes,
 865                                               uint64_t Address,
 866                                               raw_ostream &VStream,
 867                                               raw_ostream &CStream) const {
 868   uint32_t Insn;
 869   DecodeStatus Result;
 870
 871   if (IsMicroMips) {
 872     Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
 873
 874     if (hasMips32r6()) {
 875       DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n");
 876       // Calling the auto-generated decoder function for microMIPS32R6
 877       // (and microMIPS64R6) 16-bit instructions.
 878       Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn,
 879                                  Address, this, STI);
 880       if (Result != MCDisassembler::Fail) {
 881         Size = 2;
 882         return Result;
 883       }
 884     }
 885
 886     DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
 887     // Calling the auto-generated decoder function for microMIPS 16-bit
 888     // instructions.
 889     Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
 890                                this, STI);
 891     if (Result != MCDisassembler::Fail) {
 892       Size = 2;
 893       return Result;
 894     }
 895
 896     Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
 897     if (Result == MCDisassembler::Fail)
 898       return MCDisassembler::Fail;
 899
 900     if (hasMips32r6()) {
 901       DEBUG(dbgs() << "Trying MicroMips32r632 table (32-bit instructions):\n");
 902       // Calling the auto-generated decoder function.
 903       Result = decodeInstruction(DecoderTableMicroMipsR632, Instr, Insn, Address,
 904                                  this, STI);
 905       if (Result != MCDisassembler::Fail) {
 906         Size = 4;
 907         return Result;
 908       }
 909     }
 910
 911     DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 912     // Calling the auto-generated decoder function.
 913     Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
 914                                this, STI);
 915     if (Result != MCDisassembler::Fail) {
 916       Size = 4;
 917       return Result;
 918     }
 919     return MCDisassembler::Fail;
 920   }
 921
 922   Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
 923   if (Result == MCDisassembler::Fail)
 924     return MCDisassembler::Fail;
 925
 926   if (hasCOP3()) {
 927     DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 928     Result =
 929         decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
 930     if (Result != MCDisassembler::Fail) {
 931       Size = 4;
 932       return Result;
 933     }
 934   }
 935
 936   if (hasMips32r6() && isGP64()) {
 937     DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 938     Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
 939                                Address, this, STI);
 940     if (Result != MCDisassembler::Fail) {
 941       Size = 4;
 942       return Result;
 943     }
 944   }
 945
 946   if (hasMips32r6()) {
 947     DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 948     Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
 949                                Address, this, STI);
 950     if (Result != MCDisassembler::Fail) {
 951       Size = 4;
 952       return Result;
 953     }
 954   }
 955
 956   if (hasCnMips()) {
 957     DEBUG(dbgs() << "Trying CnMips table (32-bit opcodes):\n");
 958     Result = decodeInstruction(DecoderTableCnMips32, Instr, Insn,
 959                                Address, this, STI);
 960     if (Result != MCDisassembler::Fail) {
 961       Size = 4;
 962       return Result;
 963     }
 964   }
 965
 966   if (isGP64()) {
 967     DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
 968     Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
 969                                Address, this, STI);
 970     if (Result != MCDisassembler::Fail) {
 971       Size = 4;
 972       return Result;
 973     }
 974   }
 975
 976   DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 977   // Calling the auto-generated decoder function.
 978   Result =
 979       decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
 980   if (Result != MCDisassembler::Fail) {
 981     Size = 4;
 982     return Result;
 983   }
 984
 985   return MCDisassembler::Fail;
 986 }
 987
 988 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
 989                                                  unsigned RegNo,
 990                                                  uint64_t Address,
 991                                                  const void *Decoder) {
 992
 993   return MCDisassembler::Fail;
 994
 995 }
 996
 997 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
 998                                              unsigned RegNo,
 999                                              uint64_t Address,
1000                                              const void *Decoder) {
1001
1002   if (RegNo > 31)
1003     return MCDisassembler::Fail;
1004
1005   unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
1006   Inst.addOperand(MCOperand::createReg(Reg));
1007   return MCDisassembler::Success;
1008 }
1009
1010 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
1011                                                unsigned RegNo,
1012                                                uint64_t Address,
1013                                                const void *Decoder) {
1014   if (RegNo > 7)
1015     return MCDisassembler::Fail;
1016   unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
1017   Inst.addOperand(MCOperand::createReg(Reg));
1018   return MCDisassembler::Success;
1019 }
1020
1021 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
1022                                                    unsigned RegNo,
1023                                                    uint64_t Address,
1024                                                    const void *Decoder) {
1025   if (RegNo > 7)
1026     return MCDisassembler::Fail;
1027   unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
1028   Inst.addOperand(MCOperand::createReg(Reg));
1029   return MCDisassembler::Success;
1030 }
1031
1032 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
1033                                                     unsigned RegNo,
1034                                                     uint64_t Address,
1035                                                     const void *Decoder) {
1036   if (RegNo > 7)
1037     return MCDisassembler::Fail;
1038   unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
1039   Inst.addOperand(MCOperand::createReg(Reg));
1040   return MCDisassembler::Success;
1041 }
1042
1043 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
1044                                              unsigned RegNo,
1045                                              uint64_t Address,
1046                                              const void *Decoder) {
1047   if (RegNo > 31)
1048     return MCDisassembler::Fail;
1049   unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
1050   Inst.addOperand(MCOperand::createReg(Reg));
1051   return MCDisassembler::Success;
1052 }
1053
1054 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
1055                                            unsigned RegNo,
1056                                            uint64_t Address,
1057                                            const void *Decoder) {
1058   if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
1059     return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1060
1061   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1062 }
1063
1064 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
1065                                             unsigned RegNo,
1066                                             uint64_t Address,
1067                                             const void *Decoder) {
1068   return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1069 }
1070
1071 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
1072                                              unsigned RegNo,
1073                                              uint64_t Address,
1074                                              const void *Decoder) {
1075   if (RegNo > 31)
1076     return MCDisassembler::Fail;
1077
1078   unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
1079   Inst.addOperand(MCOperand::createReg(Reg));
1080   return MCDisassembler::Success;
1081 }
1082
1083 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1084                                              unsigned RegNo,
1085                                              uint64_t Address,
1086                                              const void *Decoder) {
1087   if (RegNo > 31)
1088     return MCDisassembler::Fail;
1089
1090   unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1091   Inst.addOperand(MCOperand::createReg(Reg));
1092   return MCDisassembler::Success;
1093 }
1094
1095 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1096                                            unsigned RegNo,
1097                                            uint64_t Address,
1098                                            const void *Decoder) {
1099   if (RegNo > 31)
1100     return MCDisassembler::Fail;
1101   unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1102   Inst.addOperand(MCOperand::createReg(Reg));
1103   return MCDisassembler::Success;
1104 }
1105
1106 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1107                                            unsigned RegNo,
1108                                            uint64_t Address,
1109                                            const void *Decoder) {
1110   if (RegNo > 7)
1111     return MCDisassembler::Fail;
1112   unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1113   Inst.addOperand(MCOperand::createReg(Reg));
1114   return MCDisassembler::Success;
1115 }
1116
1117 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1118                                              uint64_t Address,
1119                                              const void *Decoder) {
1120   if (RegNo > 31)
1121     return MCDisassembler::Fail;
1122
1123   unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1124   Inst.addOperand(MCOperand::createReg(Reg));
1125   return MCDisassembler::Success;
1126 }
1127
1128 static DecodeStatus DecodeMem(MCInst &Inst,
1129                               unsigned Insn,
1130                               uint64_t Address,
1131                               const void *Decoder) {
1132   int Offset = SignExtend32<16>(Insn & 0xffff);
1133   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1134   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1135
1136   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1137   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1138
1139   if (Inst.getOpcode() == Mips::SC ||
1140       Inst.getOpcode() == Mips::SCD)
1141     Inst.addOperand(MCOperand::createReg(Reg));
1142
1143   Inst.addOperand(MCOperand::createReg(Reg));
1144   Inst.addOperand(MCOperand::createReg(Base));
1145   Inst.addOperand(MCOperand::createImm(Offset));
1146
1147   return MCDisassembler::Success;
1148 }
1149
1150 static DecodeStatus DecodeMemEVA(MCInst &Inst,
1151                                  unsigned Insn,
1152                                  uint64_t Address,
1153                                  const void *Decoder) {
1154   int Offset = SignExtend32<9>(Insn >> 7);
1155   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1156   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1157
1158   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1159   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1160
1161    if (Inst.getOpcode() == Mips::SCE)
1162      Inst.addOperand(MCOperand::createReg(Reg));
1163
1164   Inst.addOperand(MCOperand::createReg(Reg));
1165   Inst.addOperand(MCOperand::createReg(Base));
1166   Inst.addOperand(MCOperand::createImm(Offset));
1167
1168   return MCDisassembler::Success;
1169 }
1170
1171 static DecodeStatus DecodeLoadByte9(MCInst &Inst,
1172                                     unsigned Insn,
1173                                     uint64_t Address,
1174                                     const void *Decoder) {
1175   int Offset = SignExtend32<9>(Insn & 0x1ff);
1176   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1177   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1178
1179   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1180   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1181
1182   Inst.addOperand(MCOperand::createReg(Reg));
1183   Inst.addOperand(MCOperand::createReg(Base));
1184   Inst.addOperand(MCOperand::createImm(Offset));
1185
1186   return MCDisassembler::Success;
1187 }
1188
1189 static DecodeStatus DecodeLoadByte15(MCInst &Inst,
1190                                      unsigned Insn,
1191                                      uint64_t Address,
1192                                      const void *Decoder) {
1193   int Offset = SignExtend32<16>(Insn & 0xffff);
1194   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1195   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1196
1197   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1198   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1199
1200   Inst.addOperand(MCOperand::createReg(Reg));
1201   Inst.addOperand(MCOperand::createReg(Base));
1202   Inst.addOperand(MCOperand::createImm(Offset));
1203
1204   return MCDisassembler::Success;
1205 }
1206
1207 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1208                               unsigned Insn,
1209                               uint64_t Address,
1210                               const void *Decoder) {
1211   int Offset = SignExtend32<16>(Insn & 0xffff);
1212   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1213   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1214
1215   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1216
1217   Inst.addOperand(MCOperand::createReg(Base));
1218   Inst.addOperand(MCOperand::createImm(Offset));
1219   Inst.addOperand(MCOperand::createImm(Hint));
1220
1221   return MCDisassembler::Success;
1222 }
1223
1224 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1225                                     unsigned Insn,
1226                                     uint64_t Address,
1227                                     const void *Decoder) {
1228   int Offset = SignExtend32<12>(Insn & 0xfff);
1229   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1230   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1231
1232   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1233
1234   Inst.addOperand(MCOperand::createReg(Base));
1235   Inst.addOperand(MCOperand::createImm(Offset));
1236   Inst.addOperand(MCOperand::createImm(Hint));
1237
1238   return MCDisassembler::Success;
1239 }
1240
1241 static DecodeStatus DecodePrefeOpMM(MCInst &Inst,
1242                                     unsigned Insn,
1243                                     uint64_t Address,
1244                                     const void *Decoder) {
1245   int Offset = SignExtend32<9>(Insn & 0x1ff);
1246   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1247   unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1248
1249   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1250
1251   Inst.addOperand(MCOperand::createReg(Base));
1252   Inst.addOperand(MCOperand::createImm(Offset));
1253   Inst.addOperand(MCOperand::createImm(Hint));
1254
1255   return MCDisassembler::Success;
1256 }
1257
1258 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst,
1259                                              unsigned Insn,
1260                                              uint64_t Address,
1261                                              const void *Decoder) {
1262   int Offset = SignExtend32<9>(Insn >> 7);
1263   unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1264   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1265
1266   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1267
1268   Inst.addOperand(MCOperand::createReg(Base));
1269   Inst.addOperand(MCOperand::createImm(Offset));
1270   Inst.addOperand(MCOperand::createImm(Hint));
1271
1272   return MCDisassembler::Success;
1273 }
1274
1275 static DecodeStatus DecodeStoreEvaOpMM(MCInst &Inst,
1276                                        unsigned Insn,
1277                                        uint64_t Address,
1278                                        const void *Decoder) {
1279   int Offset = SignExtend32<9>(Insn & 0x1ff);
1280   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1281   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1282
1283   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1284   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1285
1286   Inst.addOperand(MCOperand::createReg(Reg));
1287   Inst.addOperand(MCOperand::createReg(Base));
1288   Inst.addOperand(MCOperand::createImm(Offset));
1289
1290   return MCDisassembler::Success;
1291 }
1292
1293 static DecodeStatus DecodeSyncI(MCInst &Inst,
1294                               unsigned Insn,
1295                               uint64_t Address,
1296                               const void *Decoder) {
1297   int Offset = SignExtend32<16>(Insn & 0xffff);
1298   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1299
1300   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1301
1302   Inst.addOperand(MCOperand::createReg(Base));
1303   Inst.addOperand(MCOperand::createImm(Offset));
1304
1305   return MCDisassembler::Success;
1306 }
1307
1308 static DecodeStatus DecodeSynciR6(MCInst &Inst,
1309                                   unsigned Insn,
1310                                   uint64_t Address,
1311                                   const void *Decoder) {
1312   int Immediate = SignExtend32<16>(Insn & 0xffff);
1313   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1314
1315   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1316
1317   Inst.addOperand(MCOperand::createReg(Base));
1318   Inst.addOperand(MCOperand::createImm(Immediate));
1319
1320   return MCDisassembler::Success;
1321 }
1322
1323 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1324                                     uint64_t Address, const void *Decoder) {
1325   int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1326   unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1327   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1328
1329   Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1330   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1331
1332   Inst.addOperand(MCOperand::createReg(Reg));
1333   Inst.addOperand(MCOperand::createReg(Base));
1334
1335   // The immediate field of an LD/ST instruction is scaled which means it must
1336   // be multiplied (when decoding) by the size (in bytes) of the instructions'
1337   // data format.
1338   // .b - 1 byte
1339   // .h - 2 bytes
1340   // .w - 4 bytes
1341   // .d - 8 bytes
1342   switch(Inst.getOpcode())
1343   {
1344   default:
1345     assert (0 && "Unexpected instruction");
1346     return MCDisassembler::Fail;
1347     break;
1348   case Mips::LD_B:
1349   case Mips::ST_B:
1350     Inst.addOperand(MCOperand::createImm(Offset));
1351     break;
1352   case Mips::LD_H:
1353   case Mips::ST_H:
1354     Inst.addOperand(MCOperand::createImm(Offset * 2));
1355     break;
1356   case Mips::LD_W:
1357   case Mips::ST_W:
1358     Inst.addOperand(MCOperand::createImm(Offset * 4));
1359     break;
1360   case Mips::LD_D:
1361   case Mips::ST_D:
1362     Inst.addOperand(MCOperand::createImm(Offset * 8));
1363     break;
1364   }
1365
1366   return MCDisassembler::Success;
1367 }
1368
1369 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1370                                     unsigned Insn,
1371                                     uint64_t Address,
1372                                     const void *Decoder) {
1373   unsigned Offset = Insn & 0xf;
1374   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1375   unsigned Base = fieldFromInstruction(Insn, 4, 3);
1376
1377   switch (Inst.getOpcode()) {
1378     case Mips::LBU16_MM:
1379     case Mips::LHU16_MM:
1380     case Mips::LW16_MM:
1381       if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1382             == MCDisassembler::Fail)
1383         return MCDisassembler::Fail;
1384       break;
1385     case Mips::SB16_MM:
1386     case Mips::SH16_MM:
1387     case Mips::SW16_MM:
1388       if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1389             == MCDisassembler::Fail)
1390         return MCDisassembler::Fail;
1391       break;
1392   }
1393
1394   if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1395         == MCDisassembler::Fail)
1396     return MCDisassembler::Fail;
1397
1398   switch (Inst.getOpcode()) {
1399     case Mips::LBU16_MM:
1400       if (Offset == 0xf)
1401         Inst.addOperand(MCOperand::createImm(-1));
1402       else
1403         Inst.addOperand(MCOperand::createImm(Offset));
1404       break;
1405     case Mips::SB16_MM:
1406       Inst.addOperand(MCOperand::createImm(Offset));
1407       break;
1408     case Mips::LHU16_MM:
1409     case Mips::SH16_MM:
1410       Inst.addOperand(MCOperand::createImm(Offset << 1));
1411       break;
1412     case Mips::LW16_MM:
1413     case Mips::SW16_MM:
1414       Inst.addOperand(MCOperand::createImm(Offset << 2));
1415       break;
1416   }
1417
1418   return MCDisassembler::Success;
1419 }
1420
1421 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1422                                           unsigned Insn,
1423                                           uint64_t Address,
1424                                           const void *Decoder) {
1425   unsigned Offset = Insn & 0x1F;
1426   unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1427
1428   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1429
1430   Inst.addOperand(MCOperand::createReg(Reg));
1431   Inst.addOperand(MCOperand::createReg(Mips::SP));
1432   Inst.addOperand(MCOperand::createImm(Offset << 2));
1433
1434   return MCDisassembler::Success;
1435 }
1436
1437 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1438                                           unsigned Insn,
1439                                           uint64_t Address,
1440                                           const void *Decoder) {
1441   unsigned Offset = Insn & 0x7F;
1442   unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1443
1444   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1445
1446   Inst.addOperand(MCOperand::createReg(Reg));
1447   Inst.addOperand(MCOperand::createReg(Mips::GP));
1448   Inst.addOperand(MCOperand::createImm(Offset << 2));
1449
1450   return MCDisassembler::Success;
1451 }
1452
1453 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1454                                                unsigned Insn,
1455                                                uint64_t Address,
1456                                                const void *Decoder) {
1457   int Offset = SignExtend32<4>(Insn & 0xf);
1458
1459   if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1460       == MCDisassembler::Fail)
1461     return MCDisassembler::Fail;
1462
1463   Inst.addOperand(MCOperand::createReg(Mips::SP));
1464   Inst.addOperand(MCOperand::createImm(Offset << 2));
1465
1466   return MCDisassembler::Success;
1467 }
1468
1469 static DecodeStatus DecodeMemMMImm9(MCInst &Inst,
1470                                     unsigned Insn,
1471                                     uint64_t Address,
1472                                     const void *Decoder) {
1473   int Offset = SignExtend32<9>(Insn & 0x1ff);
1474   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1475   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1476
1477   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1478   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1479
1480   if (Inst.getOpcode() == Mips::SCE_MM)
1481     Inst.addOperand(MCOperand::createReg(Reg));
1482
1483   Inst.addOperand(MCOperand::createReg(Reg));
1484   Inst.addOperand(MCOperand::createReg(Base));
1485   Inst.addOperand(MCOperand::createImm(Offset));
1486
1487   return MCDisassembler::Success;
1488 }
1489
1490 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1491                                      unsigned Insn,
1492                                      uint64_t Address,
1493                                      const void *Decoder) {
1494   int Offset = SignExtend32<12>(Insn & 0x0fff);
1495   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1496   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1497
1498   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1499   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1500
1501   switch (Inst.getOpcode()) {
1502   case Mips::SWM32_MM:
1503   case Mips::LWM32_MM:
1504     if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1505         == MCDisassembler::Fail)
1506       return MCDisassembler::Fail;
1507     Inst.addOperand(MCOperand::createReg(Base));
1508     Inst.addOperand(MCOperand::createImm(Offset));
1509     break;
1510   case Mips::SC_MM:
1511     Inst.addOperand(MCOperand::createReg(Reg));
1512     // fallthrough
1513   default:
1514     Inst.addOperand(MCOperand::createReg(Reg));
1515     if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1516       Inst.addOperand(MCOperand::createReg(Reg+1));
1517
1518     Inst.addOperand(MCOperand::createReg(Base));
1519     Inst.addOperand(MCOperand::createImm(Offset));
1520   }
1521
1522   return MCDisassembler::Success;
1523 }
1524
1525 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1526                                      unsigned Insn,
1527                                      uint64_t Address,
1528                                      const void *Decoder) {
1529   int Offset = SignExtend32<16>(Insn & 0xffff);
1530   unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1531   unsigned Base = fieldFromInstruction(Insn, 16, 5);
1532
1533   Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1534   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1535
1536   Inst.addOperand(MCOperand::createReg(Reg));
1537   Inst.addOperand(MCOperand::createReg(Base));
1538   Inst.addOperand(MCOperand::createImm(Offset));
1539
1540   return MCDisassembler::Success;
1541 }
1542
1543 static DecodeStatus DecodeFMem(MCInst &Inst,
1544                                unsigned Insn,
1545                                uint64_t Address,
1546                                const void *Decoder) {
1547   int Offset = SignExtend32<16>(Insn & 0xffff);
1548   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1549   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1550
1551   Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1552   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1553
1554   Inst.addOperand(MCOperand::createReg(Reg));
1555   Inst.addOperand(MCOperand::createReg(Base));
1556   Inst.addOperand(MCOperand::createImm(Offset));
1557
1558   return MCDisassembler::Success;
1559 }
1560
1561 static DecodeStatus DecodeFMem2(MCInst &Inst,
1562                                unsigned Insn,
1563                                uint64_t Address,
1564                                const void *Decoder) {
1565   int Offset = SignExtend32<16>(Insn & 0xffff);
1566   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1567   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1568
1569   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1570   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1571
1572   Inst.addOperand(MCOperand::createReg(Reg));
1573   Inst.addOperand(MCOperand::createReg(Base));
1574   Inst.addOperand(MCOperand::createImm(Offset));
1575
1576   return MCDisassembler::Success;
1577 }
1578
1579 static DecodeStatus DecodeFMem3(MCInst &Inst,
1580                                unsigned Insn,
1581                                uint64_t Address,
1582                                const void *Decoder) {
1583   int Offset = SignExtend32<16>(Insn & 0xffff);
1584   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1585   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1586
1587   Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1588   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1589
1590   Inst.addOperand(MCOperand::createReg(Reg));
1591   Inst.addOperand(MCOperand::createReg(Base));
1592   Inst.addOperand(MCOperand::createImm(Offset));
1593
1594   return MCDisassembler::Success;
1595 }
1596
1597 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1598                                     unsigned Insn,
1599                                     uint64_t Address,
1600                                     const void *Decoder) {
1601   int Offset = SignExtend32<11>(Insn & 0x07ff);
1602   unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1603   unsigned Base = fieldFromInstruction(Insn, 11, 5);
1604
1605   Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1606   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1607
1608   Inst.addOperand(MCOperand::createReg(Reg));
1609   Inst.addOperand(MCOperand::createReg(Base));
1610   Inst.addOperand(MCOperand::createImm(Offset));
1611
1612   return MCDisassembler::Success;
1613 }
1614 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1615                                        unsigned Insn,
1616                                        uint64_t Address,
1617                                        const void *Decoder) {
1618   int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1619   unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1620   unsigned Base = fieldFromInstruction(Insn, 21, 5);
1621
1622   Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1623   Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1624
1625   if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1626     Inst.addOperand(MCOperand::createReg(Rt));
1627   }
1628
1629   Inst.addOperand(MCOperand::createReg(Rt));
1630   Inst.addOperand(MCOperand::createReg(Base));
1631   Inst.addOperand(MCOperand::createImm(Offset));
1632
1633   return MCDisassembler::Success;
1634 }
1635
1636 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1637                                               unsigned RegNo,
1638                                               uint64_t Address,
1639                                               const void *Decoder) {
1640   // Currently only hardware register 29 is supported.
1641   if (RegNo != 29)
1642     return  MCDisassembler::Fail;
1643   Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1644   return MCDisassembler::Success;
1645 }
1646
1647 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1648                                               unsigned RegNo,
1649                                               uint64_t Address,
1650                                               const void *Decoder) {
1651   if (RegNo > 30 || RegNo %2)
1652     return MCDisassembler::Fail;
1653
1654   ;
1655   unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1656   Inst.addOperand(MCOperand::createReg(Reg));
1657   return MCDisassembler::Success;
1658 }
1659
1660 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1661                                                 unsigned RegNo,
1662                                                 uint64_t Address,
1663                                                 const void *Decoder) {
1664   if (RegNo >= 4)
1665     return MCDisassembler::Fail;
1666
1667   unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1668   Inst.addOperand(MCOperand::createReg(Reg));
1669   return MCDisassembler::Success;
1670 }
1671
1672 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1673                                                unsigned RegNo,
1674                                                uint64_t Address,
1675                                                const void *Decoder) {
1676   if (RegNo >= 4)
1677     return MCDisassembler::Fail;
1678
1679   unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1680   Inst.addOperand(MCOperand::createReg(Reg));
1681   return MCDisassembler::Success;
1682 }
1683
1684 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1685                                                unsigned RegNo,
1686                                                uint64_t Address,
1687                                                const void *Decoder) {
1688   if (RegNo >= 4)
1689     return MCDisassembler::Fail;
1690
1691   unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1692   Inst.addOperand(MCOperand::createReg(Reg));
1693   return MCDisassembler::Success;
1694 }
1695
1696 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1697                                                unsigned RegNo,
1698                                                uint64_t Address,
1699                                                const void *Decoder) {
1700   if (RegNo > 31)
1701     return MCDisassembler::Fail;
1702
1703   unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1704   Inst.addOperand(MCOperand::createReg(Reg));
1705   return MCDisassembler::Success;
1706 }
1707
1708 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1709                                                unsigned RegNo,
1710                                                uint64_t Address,
1711                                                const void *Decoder) {
1712   if (RegNo > 31)
1713     return MCDisassembler::Fail;
1714
1715   unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1716   Inst.addOperand(MCOperand::createReg(Reg));
1717   return MCDisassembler::Success;
1718 }
1719
1720 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1721                                                unsigned RegNo,
1722                                                uint64_t Address,
1723                                                const void *Decoder) {
1724   if (RegNo > 31)
1725     return MCDisassembler::Fail;
1726
1727   unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1728   Inst.addOperand(MCOperand::createReg(Reg));
1729   return MCDisassembler::Success;
1730 }
1731
1732 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1733                                                unsigned RegNo,
1734                                                uint64_t Address,
1735                                                const void *Decoder) {
1736   if (RegNo > 31)
1737     return MCDisassembler::Fail;
1738
1739   unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1740   Inst.addOperand(MCOperand::createReg(Reg));
1741   return MCDisassembler::Success;
1742 }
1743
1744 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1745                                                unsigned RegNo,
1746                                                uint64_t Address,
1747                                                const void *Decoder) {
1748   if (RegNo > 7)
1749     return MCDisassembler::Fail;
1750
1751   unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1752   Inst.addOperand(MCOperand::createReg(Reg));
1753   return MCDisassembler::Success;
1754 }
1755
1756 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst,
1757                                             unsigned RegNo,
1758                                             uint64_t Address,
1759                                             const void *Decoder) {
1760   if (RegNo > 31)
1761     return MCDisassembler::Fail;
1762
1763   unsigned Reg = getReg(Decoder, Mips::COP0RegClassID, RegNo);
1764   Inst.addOperand(MCOperand::createReg(Reg));
1765   return MCDisassembler::Success;
1766 }
1767
1768 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1769                                             unsigned RegNo,
1770                                             uint64_t Address,
1771                                             const void *Decoder) {
1772   if (RegNo > 31)
1773     return MCDisassembler::Fail;
1774
1775   unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1776   Inst.addOperand(MCOperand::createReg(Reg));
1777   return MCDisassembler::Success;
1778 }
1779
1780 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1781                                        unsigned Offset,
1782                                        uint64_t Address,
1783                                        const void *Decoder) {
1784   int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1785   Inst.addOperand(MCOperand::createImm(BranchOffset));
1786   return MCDisassembler::Success;
1787 }
1788
1789 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1790                                      unsigned Insn,
1791                                      uint64_t Address,
1792                                      const void *Decoder) {
1793
1794   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1795   Inst.addOperand(MCOperand::createImm(JumpOffset));
1796   return MCDisassembler::Success;
1797 }
1798
1799 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1800                                          unsigned Offset,
1801                                          uint64_t Address,
1802                                          const void *Decoder) {
1803   int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1804
1805   Inst.addOperand(MCOperand::createImm(BranchOffset));
1806   return MCDisassembler::Success;
1807 }
1808
1809 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1810                                          unsigned Offset,
1811                                          uint64_t Address,
1812                                          const void *Decoder) {
1813   int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1814
1815   Inst.addOperand(MCOperand::createImm(BranchOffset));
1816   return MCDisassembler::Success;
1817 }
1818
1819 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1820                                           unsigned Offset,
1821                                           uint64_t Address,
1822                                           const void *Decoder) {
1823   int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1824   Inst.addOperand(MCOperand::createImm(BranchOffset));
1825   return MCDisassembler::Success;
1826 }
1827
1828 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1829                                            unsigned Offset,
1830                                            uint64_t Address,
1831                                            const void *Decoder) {
1832   int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1833   Inst.addOperand(MCOperand::createImm(BranchOffset));
1834   return MCDisassembler::Success;
1835 }
1836
1837 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1838                                          unsigned Offset,
1839                                          uint64_t Address,
1840                                          const void *Decoder) {
1841   int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1842   Inst.addOperand(MCOperand::createImm(BranchOffset));
1843   return MCDisassembler::Success;
1844 }
1845
1846 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1847                                        unsigned Insn,
1848                                        uint64_t Address,
1849                                        const void *Decoder) {
1850   unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1851   Inst.addOperand(MCOperand::createImm(JumpOffset));
1852   return MCDisassembler::Success;
1853 }
1854
1855 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1856                                        unsigned Value,
1857                                        uint64_t Address,
1858                                        const void *Decoder) {
1859   if (Value == 0)
1860     Inst.addOperand(MCOperand::createImm(1));
1861   else if (Value == 0x7)
1862     Inst.addOperand(MCOperand::createImm(-1));
1863   else
1864     Inst.addOperand(MCOperand::createImm(Value << 2));
1865   return MCDisassembler::Success;
1866 }
1867
1868 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1869                                     unsigned Value,
1870                                     uint64_t Address,
1871                                     const void *Decoder) {
1872   Inst.addOperand(MCOperand::createImm(Value << 2));
1873   return MCDisassembler::Success;
1874 }
1875
1876 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1877                                   unsigned Value,
1878                                   uint64_t Address,
1879                                   const void *Decoder) {
1880   if (Value == 0x7F)
1881     Inst.addOperand(MCOperand::createImm(-1));
1882   else
1883     Inst.addOperand(MCOperand::createImm(Value));
1884   return MCDisassembler::Success;
1885 }
1886
1887 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst,
1888                                               unsigned Value,
1889                                               uint64_t Address,
1890                                               const void *Decoder) {
1891   Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
1892   return MCDisassembler::Success;
1893 }
1894
1895 static DecodeStatus DecodeSimm4(MCInst &Inst,
1896                                 unsigned Value,
1897                                 uint64_t Address,
1898                                 const void *Decoder) {
1899   Inst.addOperand(MCOperand::createImm(SignExtend32<4>(Value)));
1900   return MCDisassembler::Success;
1901 }
1902
1903 static DecodeStatus DecodeSimm16(MCInst &Inst,
1904                                  unsigned Insn,
1905                                  uint64_t Address,
1906                                  const void *Decoder) {
1907   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Insn)));
1908   return MCDisassembler::Success;
1909 }
1910
1911 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1912                                  unsigned Insn,
1913                                  uint64_t Address,
1914                                  const void *Decoder) {
1915   // We add one to the immediate field as it was encoded as 'imm - 1'.
1916   Inst.addOperand(MCOperand::createImm(Insn + 1));
1917   return MCDisassembler::Success;
1918 }
1919
1920 static DecodeStatus DecodeInsSize(MCInst &Inst,
1921                                   unsigned Insn,
1922                                   uint64_t Address,
1923                                   const void *Decoder) {
1924   // First we need to grab the pos(lsb) from MCInst.
1925   int Pos = Inst.getOperand(2).getImm();
1926   int Size = (int) Insn - Pos + 1;
1927   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1928   return MCDisassembler::Success;
1929 }
1930
1931 static DecodeStatus DecodeExtSize(MCInst &Inst,
1932                                   unsigned Insn,
1933                                   uint64_t Address,
1934                                   const void *Decoder) {
1935   int Size = (int) Insn  + 1;
1936   Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
1937   return MCDisassembler::Success;
1938 }
1939
1940 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1941                                      uint64_t Address, const void *Decoder) {
1942   Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
1943   return MCDisassembler::Success;
1944 }
1945
1946 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1947                                      uint64_t Address, const void *Decoder) {
1948   Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
1949   return MCDisassembler::Success;
1950 }
1951
1952 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1953                                   uint64_t Address, const void *Decoder) {
1954   int32_t DecodedValue;
1955   switch (Insn) {
1956   case 0: DecodedValue = 256; break;
1957   case 1: DecodedValue = 257; break;
1958   case 510: DecodedValue = -258; break;
1959   case 511: DecodedValue = -257; break;
1960   default: DecodedValue = SignExtend32<9>(Insn); break;
1961   }
1962   Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
1963   return MCDisassembler::Success;
1964 }
1965
1966 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1967                                     uint64_t Address, const void *Decoder) {
1968   // Insn must be >= 0, since it is unsigned that condition is always true.
1969   assert(Insn < 16);
1970   int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1971                              255, 32768, 65535};
1972   Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
1973   return MCDisassembler::Success;
1974 }
1975
1976 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1977                                     uint64_t Address, const void *Decoder) {
1978   Inst.addOperand(MCOperand::createImm(Insn << 2));
1979   return MCDisassembler::Success;
1980 }
1981
1982 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1983                                          unsigned Insn,
1984                                          uint64_t Address,
1985                                          const void *Decoder) {
1986   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1987                      Mips::S6, Mips::S7, Mips::FP};
1988   unsigned RegNum;
1989
1990   unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1991
1992   // Empty register lists are not allowed.
1993   if (RegLst == 0)
1994     return MCDisassembler::Fail;
1995
1996   RegNum = RegLst & 0xf;
1997
1998   // RegLst values 10-15, and 26-31 are reserved.
1999   if (RegNum > 9)
2000     return MCDisassembler::Fail;
2001
2002   for (unsigned i = 0; i < RegNum; i++)
2003     Inst.addOperand(MCOperand::createReg(Regs[i]));
2004
2005   if (RegLst & 0x10)
2006     Inst.addOperand(MCOperand::createReg(Mips::RA));
2007
2008   return MCDisassembler::Success;
2009 }
2010
2011 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2012                                            uint64_t Address,
2013                                            const void *Decoder) {
2014   unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
2015   unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
2016   unsigned RegNum = RegLst & 0x3;
2017
2018   for (unsigned i = 0; i <= RegNum; i++)
2019     Inst.addOperand(MCOperand::createReg(Regs[i]));
2020
2021   Inst.addOperand(MCOperand::createReg(Mips::RA));
2022
2023   return MCDisassembler::Success;
2024 }
2025
2026 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
2027                                        uint64_t Address, const void *Decoder) {
2028
2029   unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
2030
2031   switch (RegPair) {
2032   default:
2033     return MCDisassembler::Fail;
2034   case 0:
2035     Inst.addOperand(MCOperand::createReg(Mips::A1));
2036     Inst.addOperand(MCOperand::createReg(Mips::A2));
2037     break;
2038   case 1:
2039     Inst.addOperand(MCOperand::createReg(Mips::A1));
2040     Inst.addOperand(MCOperand::createReg(Mips::A3));
2041     break;
2042   case 2:
2043     Inst.addOperand(MCOperand::createReg(Mips::A2));
2044     Inst.addOperand(MCOperand::createReg(Mips::A3));
2045     break;
2046   case 3:
2047     Inst.addOperand(MCOperand::createReg(Mips::A0));
2048     Inst.addOperand(MCOperand::createReg(Mips::S5));
2049     break;
2050   case 4:
2051     Inst.addOperand(MCOperand::createReg(Mips::A0));
2052     Inst.addOperand(MCOperand::createReg(Mips::S6));
2053     break;
2054   case 5:
2055     Inst.addOperand(MCOperand::createReg(Mips::A0));
2056     Inst.addOperand(MCOperand::createReg(Mips::A1));
2057     break;
2058   case 6:
2059     Inst.addOperand(MCOperand::createReg(Mips::A0));
2060     Inst.addOperand(MCOperand::createReg(Mips::A2));
2061     break;
2062   case 7:
2063     Inst.addOperand(MCOperand::createReg(Mips::A0));
2064     Inst.addOperand(MCOperand::createReg(Mips::A3));
2065     break;
2066   }
2067
2068   return MCDisassembler::Success;
2069 }
2070
2071 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2072                                      uint64_t Address, const void *Decoder) {
2073   Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2074   return MCDisassembler::Success;
2075 }