1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCTargetDesc.h"
11 #include "MipsRegisterInfo.h"
12 #include "llvm/ADT/StringSwitch.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCSymbol.h"
19 #include "llvm/MC/MCParser/MCAsmLexer.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/MC/MCTargetAsmParser.h"
22 #include "llvm/Support/TargetRegistry.h"
27 class MipsAssemblerOptions {
29 MipsAssemblerOptions():
30 aTReg(1), reorder(true), macro(true) {
33 unsigned getATRegNum() {return aTReg;}
34 bool setATReg(unsigned Reg);
36 bool isReorder() {return reorder;}
37 void setReorder() {reorder = true;}
38 void setNoreorder() {reorder = false;}
40 bool isMacro() {return macro;}
41 void setMacro() {macro = true;}
42 void setNomacro() {macro = false;}
52 class MipsAsmParser : public MCTargetAsmParser {
64 MipsAssemblerOptions Options;
67 #define GET_ASSEMBLER_HEADER
68 #include "MipsGenAsmMatcher.inc"
70 bool MatchAndEmitInstruction(SMLoc IDLoc,
71 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
74 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
76 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
77 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
79 bool parseMathOperation(StringRef Name, SMLoc NameLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
82 bool ParseDirective(AsmToken DirectiveID);
84 MipsAsmParser::OperandMatchResultTy
85 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
87 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
90 int tryParseRegister(StringRef Mnemonic);
92 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
95 bool needsExpansion(MCInst &Inst);
97 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
98 SmallVectorImpl<MCInst> &Instructions);
99 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
100 SmallVectorImpl<MCInst> &Instructions);
101 bool reportParseError(StringRef ErrorMsg);
103 bool parseMemOffset(const MCExpr *&Res);
104 bool parseRelocOperand(const MCExpr *&Res);
106 bool parseDirectiveSet();
108 bool parseSetAtDirective();
109 bool parseSetNoAtDirective();
110 bool parseSetMacroDirective();
111 bool parseSetNoMacroDirective();
112 bool parseSetReorderDirective();
113 bool parseSetNoReorderDirective();
115 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
117 bool isMips64() const {
118 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
121 bool isFP64() const {
122 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
125 int matchRegisterName(StringRef Symbol);
127 int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
129 void setFpFormat(FpFormatTy Format) {
133 void setDefaultFpFormat();
135 void setFpFormat(StringRef Format);
137 FpFormatTy getFpFormat() {return FpFormat;}
139 bool requestsDoubleOperand(StringRef Mnemonic);
141 unsigned getReg(int RC,int RegNo);
145 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
146 : MCTargetAsmParser(), STI(sti), Parser(parser) {
147 // Initialize the set of available features.
148 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
151 MCAsmParser &getParser() const { return Parser; }
152 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
159 /// MipsOperand - Instances of this class represent a parsed Mips machine
161 class MipsOperand : public MCParsedAsmOperand {
173 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
195 SMLoc StartLoc, EndLoc;
198 void addRegOperands(MCInst &Inst, unsigned N) const {
199 assert(N == 1 && "Invalid number of operands!");
200 Inst.addOperand(MCOperand::CreateReg(getReg()));
203 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
204 // Add as immediate when possible. Null MCExpr = 0.
206 Inst.addOperand(MCOperand::CreateImm(0));
207 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
208 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
210 Inst.addOperand(MCOperand::CreateExpr(Expr));
213 void addImmOperands(MCInst &Inst, unsigned N) const {
214 assert(N == 1 && "Invalid number of operands!");
215 const MCExpr *Expr = getImm();
219 void addMemOperands(MCInst &Inst, unsigned N) const {
220 assert(N == 2 && "Invalid number of operands!");
222 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
224 const MCExpr *Expr = getMemOff();
228 bool isReg() const { return Kind == k_Register; }
229 bool isImm() const { return Kind == k_Immediate; }
230 bool isToken() const { return Kind == k_Token; }
231 bool isMem() const { return Kind == k_Memory; }
233 StringRef getToken() const {
234 assert(Kind == k_Token && "Invalid access!");
235 return StringRef(Tok.Data, Tok.Length);
238 unsigned getReg() const {
239 assert((Kind == k_Register) && "Invalid access!");
243 const MCExpr *getImm() const {
244 assert((Kind == k_Immediate) && "Invalid access!");
248 unsigned getMemBase() const {
249 assert((Kind == k_Memory) && "Invalid access!");
253 const MCExpr *getMemOff() const {
254 assert((Kind == k_Memory) && "Invalid access!");
258 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
259 MipsOperand *Op = new MipsOperand(k_Token);
260 Op->Tok.Data = Str.data();
261 Op->Tok.Length = Str.size();
267 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
268 MipsOperand *Op = new MipsOperand(k_Register);
269 Op->Reg.RegNum = RegNum;
275 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
276 MipsOperand *Op = new MipsOperand(k_Immediate);
283 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off,
285 MipsOperand *Op = new MipsOperand(k_Memory);
293 /// getStartLoc - Get the location of the first token of this operand.
294 SMLoc getStartLoc() const { return StartLoc; }
295 /// getEndLoc - Get the location of the last token of this operand.
296 SMLoc getEndLoc() const { return EndLoc; }
298 virtual void print(raw_ostream &OS) const {
299 llvm_unreachable("unimplemented!");
304 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
306 switch(Inst.getOpcode()) {
307 case Mips::LoadImm32Reg:
314 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
315 SmallVectorImpl<MCInst> &Instructions){
316 switch(Inst.getOpcode()) {
317 case Mips::LoadImm32Reg:
318 return expandLoadImm(Inst, IDLoc, Instructions);
322 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
323 SmallVectorImpl<MCInst> &Instructions){
325 const MCOperand &ImmOp = Inst.getOperand(1);
326 assert(ImmOp.isImm() && "expected imediate operand kind");
327 const MCOperand &RegOp = Inst.getOperand(0);
328 assert(RegOp.isReg() && "expected register operand kind");
330 int ImmValue = ImmOp.getImm();
331 tmpInst.setLoc(IDLoc);
332 if ( 0 <= ImmValue && ImmValue <= 65535) {
333 // for 0 <= j <= 65535.
334 // li d,j => ori d,$zero,j
335 tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
336 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
338 MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
339 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
340 Instructions.push_back(tmpInst);
341 } else if ( ImmValue < 0 && ImmValue >= -32768) {
342 // for -32768 <= j < 0.
343 // li d,j => addiu d,$zero,j
344 tmpInst.setOpcode(Mips::ADDiu); //TODO:no ADDiu64 in td files?
345 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
347 MCOperand::CreateReg(isMips64() ? Mips::ZERO_64 : Mips::ZERO));
348 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
349 Instructions.push_back(tmpInst);
351 // for any other value of j that is representable as a 32-bit integer.
352 // li d,j => lui d,hi16(j)
354 tmpInst.setOpcode(isMips64() ? Mips::LUi64 : Mips::LUi);
355 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
356 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
357 Instructions.push_back(tmpInst);
359 tmpInst.setOpcode(isMips64() ? Mips::ORi64 : Mips::ORi);
360 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
361 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
362 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
363 tmpInst.setLoc(IDLoc);
364 Instructions.push_back(tmpInst);
369 MatchAndEmitInstruction(SMLoc IDLoc,
370 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
375 MatchInstMapAndConstraints MapAndConstraints;
376 unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst,
377 MapAndConstraints, ErrorInfo,
378 /*matchingInlineAsm*/ false);
380 switch (MatchResult) {
382 case Match_Success: {
383 if (needsExpansion(Inst)) {
384 SmallVector<MCInst, 4> Instructions;
385 expandInstruction(Inst, IDLoc, Instructions);
386 for(unsigned i =0; i < Instructions.size(); i++){
387 Out.EmitInstruction(Instructions[i]);
391 Out.EmitInstruction(Inst);
395 case Match_MissingFeature:
396 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
398 case Match_InvalidOperand: {
399 SMLoc ErrorLoc = IDLoc;
400 if (ErrorInfo != ~0U) {
401 if (ErrorInfo >= Operands.size())
402 return Error(IDLoc, "too few operands for instruction");
404 ErrorLoc = ((MipsOperand*)Operands[ErrorInfo])->getStartLoc();
405 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
408 return Error(ErrorLoc, "invalid operand for instruction");
410 case Match_MnemonicFail:
411 return Error(IDLoc, "invalid instruction");
416 int MipsAsmParser::matchRegisterName(StringRef Name) {
420 CC = StringSwitch<unsigned>(Name)
421 .Case("zero", Mips::ZERO)
422 .Case("a0", Mips::A0)
423 .Case("a1", Mips::A1)
424 .Case("a2", Mips::A2)
425 .Case("a3", Mips::A3)
426 .Case("v0", Mips::V0)
427 .Case("v1", Mips::V1)
428 .Case("s0", Mips::S0)
429 .Case("s1", Mips::S1)
430 .Case("s2", Mips::S2)
431 .Case("s3", Mips::S3)
432 .Case("s4", Mips::S4)
433 .Case("s5", Mips::S5)
434 .Case("s6", Mips::S6)
435 .Case("s7", Mips::S7)
436 .Case("k0", Mips::K0)
437 .Case("k1", Mips::K1)
438 .Case("sp", Mips::SP)
439 .Case("fp", Mips::FP)
440 .Case("gp", Mips::GP)
441 .Case("ra", Mips::RA)
442 .Case("t0", Mips::T0)
443 .Case("t1", Mips::T1)
444 .Case("t2", Mips::T2)
445 .Case("t3", Mips::T3)
446 .Case("t4", Mips::T4)
447 .Case("t5", Mips::T5)
448 .Case("t6", Mips::T6)
449 .Case("t7", Mips::T7)
450 .Case("t8", Mips::T8)
451 .Case("t9", Mips::T9)
452 .Case("at", Mips::AT)
453 .Case("fcc0", Mips::FCC0)
456 CC = StringSwitch<unsigned>(Name)
457 .Case("zero", Mips::ZERO_64)
458 .Case("at", Mips::AT_64)
459 .Case("v0", Mips::V0_64)
460 .Case("v1", Mips::V1_64)
461 .Case("a0", Mips::A0_64)
462 .Case("a1", Mips::A1_64)
463 .Case("a2", Mips::A2_64)
464 .Case("a3", Mips::A3_64)
465 .Case("a4", Mips::T0_64)
466 .Case("a5", Mips::T1_64)
467 .Case("a6", Mips::T2_64)
468 .Case("a7", Mips::T3_64)
469 .Case("t4", Mips::T4_64)
470 .Case("t5", Mips::T5_64)
471 .Case("t6", Mips::T6_64)
472 .Case("t7", Mips::T7_64)
473 .Case("s0", Mips::S0_64)
474 .Case("s1", Mips::S1_64)
475 .Case("s2", Mips::S2_64)
476 .Case("s3", Mips::S3_64)
477 .Case("s4", Mips::S4_64)
478 .Case("s5", Mips::S5_64)
479 .Case("s6", Mips::S6_64)
480 .Case("s7", Mips::S7_64)
481 .Case("t8", Mips::T8_64)
482 .Case("t9", Mips::T9_64)
483 .Case("kt0", Mips::K0_64)
484 .Case("kt1", Mips::K1_64)
485 .Case("gp", Mips::GP_64)
486 .Case("sp", Mips::SP_64)
487 .Case("fp", Mips::FP_64)
488 .Case("s8", Mips::FP_64)
489 .Case("ra", Mips::RA_64)
495 if (Name[0] == 'f') {
496 StringRef NumString = Name.substr(1);
498 if( NumString.getAsInteger(10, IntVal))
499 return -1; // not integer
503 FpFormatTy Format = getFpFormat();
505 if (Format == FP_FORMAT_S || Format == FP_FORMAT_W)
506 return getReg(Mips::FGR32RegClassID, IntVal);
507 if (Format == FP_FORMAT_D) {
509 return getReg(Mips::FGR64RegClassID, IntVal);
511 // only even numbers available as register pairs
512 if (( IntVal > 31) || (IntVal%2 != 0))
514 return getReg(Mips::AFGR64RegClassID, IntVal/2);
520 void MipsAsmParser::setDefaultFpFormat() {
522 if (isMips64() || isFP64())
523 FpFormat = FP_FORMAT_D;
525 FpFormat = FP_FORMAT_S;
528 bool MipsAsmParser::requestsDoubleOperand(StringRef Mnemonic){
530 bool IsDouble = StringSwitch<bool>(Mnemonic.lower())
539 void MipsAsmParser::setFpFormat(StringRef Format) {
541 FpFormat = StringSwitch<FpFormatTy>(Format.lower())
542 .Case(".s", FP_FORMAT_S)
543 .Case(".d", FP_FORMAT_D)
544 .Case(".l", FP_FORMAT_L)
545 .Case(".w", FP_FORMAT_W)
546 .Default(FP_FORMAT_NONE);
549 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
557 unsigned MipsAsmParser::getATReg() {
558 unsigned Reg = Options.getATRegNum();
560 return getReg(Mips::CPU64RegsRegClassID,Reg);
562 return getReg(Mips::CPURegsRegClassID,Reg);
565 unsigned MipsAsmParser::getReg(int RC,int RegNo) {
566 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
569 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic) {
571 if (Mnemonic.lower() == "rdhwr") {
572 // at the moment only hwreg29 is supported
581 // MIPS64 registers are numbered 1 after the 32-bit equivalents
582 return getReg(Mips::CPURegsRegClassID, RegNum) + isMips64();
585 int MipsAsmParser::tryParseRegister(StringRef Mnemonic) {
586 const AsmToken &Tok = Parser.getTok();
589 if (Tok.is(AsmToken::Identifier)) {
590 std::string lowerCase = Tok.getString().lower();
591 RegNum = matchRegisterName(lowerCase);
592 } else if (Tok.is(AsmToken::Integer))
593 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
596 return RegNum; //error
597 // 64 bit div operations require Mips::ZERO instead of MIPS::ZERO_64
598 if (isMips64() && RegNum == Mips::ZERO_64) {
599 if (Mnemonic.find("ddiv") != StringRef::npos)
606 tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
609 SMLoc S = Parser.getTok().getLoc();
612 // FIXME: we should make a more generic method for CCR
613 if ((Mnemonic == "cfc1" || Mnemonic == "ctc1")
614 && Operands.size() == 2 && Parser.getTok().is(AsmToken::Integer)){
615 RegNo = Parser.getTok().getIntVal(); // get the int value
616 // at the moment only fcc0 is supported
620 RegNo = tryParseRegister(Mnemonic);
624 Operands.push_back(MipsOperand::CreateReg(RegNo, S,
625 Parser.getTok().getLoc()));
626 Parser.Lex(); // Eat register token.
630 bool MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
631 StringRef Mnemonic) {
632 // Check if the current operand has a custom associated parser, if so, try to
633 // custom parse the operand, or fallback to the general approach.
634 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
635 if (ResTy == MatchOperand_Success)
637 // If there wasn't a custom match, try the generic matcher below. Otherwise,
638 // there was a match, but an error occurred, in which case, just return that
639 // the operand parsing failed.
640 if (ResTy == MatchOperand_ParseFail)
643 switch (getLexer().getKind()) {
645 Error(Parser.getTok().getLoc(), "unexpected token in operand");
647 case AsmToken::Dollar: {
649 SMLoc S = Parser.getTok().getLoc();
650 Parser.Lex(); // Eat dollar token.
651 // parse register operand
652 if (!tryParseRegisterOperand(Operands, Mnemonic)) {
653 if (getLexer().is(AsmToken::LParen)) {
654 // check if it is indexed addressing operand
655 Operands.push_back(MipsOperand::CreateToken("(", S));
656 Parser.Lex(); // eat parenthesis
657 if (getLexer().isNot(AsmToken::Dollar))
660 Parser.Lex(); // eat dollar
661 if (tryParseRegisterOperand(Operands, Mnemonic))
664 if (!getLexer().is(AsmToken::RParen))
667 S = Parser.getTok().getLoc();
668 Operands.push_back(MipsOperand::CreateToken(")", S));
673 // maybe it is a symbol reference
674 StringRef Identifier;
675 if (Parser.ParseIdentifier(Identifier))
678 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
680 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
682 // Otherwise create a symbol ref.
683 const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
686 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
689 case AsmToken::Identifier:
690 case AsmToken::LParen:
691 case AsmToken::Minus:
693 case AsmToken::Integer:
694 case AsmToken::String: {
695 // quoted label names
697 SMLoc S = Parser.getTok().getLoc();
698 if (getParser().ParseExpression(IdVal))
700 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
701 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
704 case AsmToken::Percent: {
705 // it is a symbol reference or constant expression
707 SMLoc S = Parser.getTok().getLoc(); // start location of the operand
708 if (parseRelocOperand(IdVal))
711 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
713 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
715 } // case AsmToken::Percent
716 } // switch(getLexer().getKind())
720 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
722 Parser.Lex(); // eat % token
723 const AsmToken &Tok = Parser.getTok(); // get next token, operation
724 if (Tok.isNot(AsmToken::Identifier))
727 std::string Str = Tok.getIdentifier().str();
729 Parser.Lex(); // eat identifier
730 // now make expression from the rest of the operand
734 if (getLexer().getKind() == AsmToken::LParen) {
736 Parser.Lex(); // eat '(' token
737 if (getLexer().getKind() == AsmToken::Percent) {
738 Parser.Lex(); // eat % token
739 const AsmToken &nextTok = Parser.getTok();
740 if (nextTok.isNot(AsmToken::Identifier))
743 Str += nextTok.getIdentifier();
744 Parser.Lex(); // eat identifier
745 if (getLexer().getKind() != AsmToken::LParen)
750 if (getParser().ParseParenExpression(IdVal,EndLoc))
753 while (getLexer().getKind() == AsmToken::RParen)
754 Parser.Lex(); // eat ')' token
757 return true; // parenthesis must follow reloc operand
759 // Check the type of the expression
760 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
761 // it's a constant, evaluate lo or hi value
762 int Val = MCE->getValue();
765 } else if (Str == "hi") {
766 Val = (Val & 0xffff0000) >> 16;
768 Res = MCConstantExpr::Create(Val, getContext());
772 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
773 // it's a symbol, create symbolic expression from symbol
774 StringRef Symbol = MSRE->getSymbol().getName();
775 MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
776 Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
782 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
785 StartLoc = Parser.getTok().getLoc();
786 RegNo = tryParseRegister("");
787 EndLoc = Parser.getTok().getLoc();
788 return (RegNo == (unsigned)-1);
791 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res) {
795 switch(getLexer().getKind()) {
798 case AsmToken::Integer:
799 case AsmToken::Minus:
801 return (getParser().ParseExpression(Res));
802 case AsmToken::Percent:
803 return parseRelocOperand(Res);
804 case AsmToken::LParen:
805 return false; // it's probably assuming 0
810 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
811 SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
813 const MCExpr *IdVal = 0;
815 // first operand is the offset
816 S = Parser.getTok().getLoc();
818 if (parseMemOffset(IdVal))
819 return MatchOperand_ParseFail;
821 const AsmToken &Tok = Parser.getTok(); // get next token
822 if (Tok.isNot(AsmToken::LParen)) {
823 Error(Parser.getTok().getLoc(), "'(' expected");
824 return MatchOperand_ParseFail;
827 Parser.Lex(); // Eat '(' token.
829 const AsmToken &Tok1 = Parser.getTok(); //get next token
830 if (Tok1.is(AsmToken::Dollar)) {
831 Parser.Lex(); // Eat '$' token.
832 if (tryParseRegisterOperand(Operands,"")) {
833 Error(Parser.getTok().getLoc(), "unexpected token in operand");
834 return MatchOperand_ParseFail;
838 Error(Parser.getTok().getLoc(), "unexpected token in operand");
839 return MatchOperand_ParseFail;
842 const AsmToken &Tok2 = Parser.getTok(); // get next token
843 if (Tok2.isNot(AsmToken::RParen)) {
844 Error(Parser.getTok().getLoc(), "')' expected");
845 return MatchOperand_ParseFail;
848 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
850 Parser.Lex(); // Eat ')' token.
853 IdVal = MCConstantExpr::Create(0, getContext());
855 // now replace register operand with the mem operand
856 MipsOperand* op = static_cast<MipsOperand*>(Operands.back());
857 int RegNo = op->getReg();
858 // remove register from operands
860 // and add memory operand
861 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
863 return MatchOperand_Success;
866 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
868 MCSymbolRefExpr::VariantKind VK
869 = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
870 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
871 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
872 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
873 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
874 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
875 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
876 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
877 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
878 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
879 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
880 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
881 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
882 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
883 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
884 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
885 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
886 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
887 .Default(MCSymbolRefExpr::VK_None);
892 static int ConvertCcString(StringRef CondString) {
893 int CC = StringSwitch<unsigned>(CondString)
916 parseMathOperation(StringRef Name, SMLoc NameLoc,
917 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
919 size_t Start = Name.find('.'), Next = Name.rfind('.');
920 StringRef Format1 = Name.slice(Start, Next);
921 // and add the first format to the operands
922 Operands.push_back(MipsOperand::CreateToken(Format1, NameLoc));
923 // now for the second format
924 StringRef Format2 = Name.slice(Next, StringRef::npos);
925 Operands.push_back(MipsOperand::CreateToken(Format2, NameLoc));
927 // set the format for the first register
928 setFpFormat(Format1);
930 // Read the remaining operands.
931 if (getLexer().isNot(AsmToken::EndOfStatement)) {
932 // Read the first operand.
933 if (ParseOperand(Operands, Name)) {
934 SMLoc Loc = getLexer().getLoc();
935 Parser.EatToEndOfStatement();
936 return Error(Loc, "unexpected token in argument list");
939 if (getLexer().isNot(AsmToken::Comma)) {
940 SMLoc Loc = getLexer().getLoc();
941 Parser.EatToEndOfStatement();
942 return Error(Loc, "unexpected token in argument list");
945 Parser.Lex(); // Eat the comma.
947 //set the format for the first register
948 setFpFormat(Format2);
950 // Parse and remember the operand.
951 if (ParseOperand(Operands, Name)) {
952 SMLoc Loc = getLexer().getLoc();
953 Parser.EatToEndOfStatement();
954 return Error(Loc, "unexpected token in argument list");
958 if (getLexer().isNot(AsmToken::EndOfStatement)) {
959 SMLoc Loc = getLexer().getLoc();
960 Parser.EatToEndOfStatement();
961 return Error(Loc, "unexpected token in argument list");
964 Parser.Lex(); // Consume the EndOfStatement
969 ParseInstruction(StringRef Name, SMLoc NameLoc,
970 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
971 // floating point instructions: should register be treated as double?
972 if (requestsDoubleOperand(Name)) {
973 setFpFormat(FP_FORMAT_D);
974 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
977 setDefaultFpFormat();
978 // Create the leading tokens for the mnemonic, split by '.' characters.
979 size_t Start = 0, Next = Name.find('.');
980 StringRef Mnemonic = Name.slice(Start, Next);
982 Operands.push_back(MipsOperand::CreateToken(Mnemonic, NameLoc));
984 if (Next != StringRef::npos) {
985 // there is a format token in mnemonic
986 // StringRef Rest = Name.slice(Next, StringRef::npos);
987 size_t Dot = Name.find('.', Next+1);
988 StringRef Format = Name.slice(Next, Dot);
989 if (Dot == StringRef::npos) //only one '.' in a string, it's a format
990 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
992 if (Name.startswith("c.")){
993 // floating point compare, add '.' and immediate represent for cc
994 Operands.push_back(MipsOperand::CreateToken(".", NameLoc));
995 int Cc = ConvertCcString(Format);
997 return Error(NameLoc, "Invalid conditional code");
999 SMLoc E = SMLoc::getFromPointer(
1000 Parser.getTok().getLoc().getPointer() -1 );
1001 Operands.push_back(MipsOperand::CreateImm(
1002 MCConstantExpr::Create(Cc, getContext()), NameLoc, E));
1004 // trunc, ceil, floor ...
1005 return parseMathOperation(Name, NameLoc, Operands);
1008 // the rest is a format
1009 Format = Name.slice(Dot, StringRef::npos);
1010 Operands.push_back(MipsOperand::CreateToken(Format, NameLoc));
1013 setFpFormat(Format);
1017 // Read the remaining operands.
1018 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1019 // Read the first operand.
1020 if (ParseOperand(Operands, Name)) {
1021 SMLoc Loc = getLexer().getLoc();
1022 Parser.EatToEndOfStatement();
1023 return Error(Loc, "unexpected token in argument list");
1026 while (getLexer().is(AsmToken::Comma) ) {
1027 Parser.Lex(); // Eat the comma.
1029 // Parse and remember the operand.
1030 if (ParseOperand(Operands, Name)) {
1031 SMLoc Loc = getLexer().getLoc();
1032 Parser.EatToEndOfStatement();
1033 return Error(Loc, "unexpected token in argument list");
1038 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1039 SMLoc Loc = getLexer().getLoc();
1040 Parser.EatToEndOfStatement();
1041 return Error(Loc, "unexpected token in argument list");
1044 Parser.Lex(); // Consume the EndOfStatement
1048 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
1049 SMLoc Loc = getLexer().getLoc();
1050 Parser.EatToEndOfStatement();
1051 return Error(Loc, ErrorMsg);
1054 bool MipsAsmParser::parseSetNoAtDirective() {
1055 // line should look like:
1058 Options.setATReg(0);
1061 // if this is not the end of the statement, report error
1062 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1063 reportParseError("unexpected token in statement");
1066 Parser.Lex(); // Consume the EndOfStatement
1069 bool MipsAsmParser::parseSetAtDirective() {
1071 // .set at - defaults to $1
1074 if (getLexer().is(AsmToken::EndOfStatement)) {
1075 Options.setATReg(1);
1076 Parser.Lex(); // Consume the EndOfStatement
1078 } else if (getLexer().is(AsmToken::Equal)) {
1079 getParser().Lex(); //eat '='
1080 if (getLexer().isNot(AsmToken::Dollar)) {
1081 reportParseError("unexpected token in statement");
1084 Parser.Lex(); // eat '$'
1085 if (getLexer().isNot(AsmToken::Integer)) {
1086 reportParseError("unexpected token in statement");
1089 const AsmToken &Reg = Parser.getTok();
1090 if (!Options.setATReg(Reg.getIntVal())) {
1091 reportParseError("unexpected token in statement");
1094 getParser().Lex(); //eat reg
1096 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1097 reportParseError("unexpected token in statement");
1100 Parser.Lex(); // Consume the EndOfStatement
1103 reportParseError("unexpected token in statement");
1108 bool MipsAsmParser::parseSetReorderDirective() {
1110 // if this is not the end of the statement, report error
1111 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1112 reportParseError("unexpected token in statement");
1115 Options.setReorder();
1116 Parser.Lex(); // Consume the EndOfStatement
1120 bool MipsAsmParser::parseSetNoReorderDirective() {
1122 // if this is not the end of the statement, report error
1123 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1124 reportParseError("unexpected token in statement");
1127 Options.setNoreorder();
1128 Parser.Lex(); // Consume the EndOfStatement
1132 bool MipsAsmParser::parseSetMacroDirective() {
1134 // if this is not the end of the statement, report error
1135 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1136 reportParseError("unexpected token in statement");
1140 Parser.Lex(); // Consume the EndOfStatement
1144 bool MipsAsmParser::parseSetNoMacroDirective() {
1146 // if this is not the end of the statement, report error
1147 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1148 reportParseError("`noreorder' must be set before `nomacro'");
1151 if (Options.isReorder()) {
1152 reportParseError("`noreorder' must be set before `nomacro'");
1155 Options.setNomacro();
1156 Parser.Lex(); // Consume the EndOfStatement
1159 bool MipsAsmParser::parseDirectiveSet() {
1162 const AsmToken &Tok = Parser.getTok();
1164 if (Tok.getString() == "noat") {
1165 return parseSetNoAtDirective();
1166 } else if (Tok.getString() == "at") {
1167 return parseSetAtDirective();
1168 } else if (Tok.getString() == "reorder") {
1169 return parseSetReorderDirective();
1170 } else if (Tok.getString() == "noreorder") {
1171 return parseSetNoReorderDirective();
1172 } else if (Tok.getString() == "macro") {
1173 return parseSetMacroDirective();
1174 } else if (Tok.getString() == "nomacro") {
1175 return parseSetNoMacroDirective();
1176 } else if (Tok.getString() == "nomips16") {
1177 // ignore this directive for now
1178 Parser.EatToEndOfStatement();
1180 } else if (Tok.getString() == "nomicromips") {
1181 // ignore this directive for now
1182 Parser.EatToEndOfStatement();
1188 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
1190 if (DirectiveID.getString() == ".ent") {
1191 // ignore this directive for now
1196 if (DirectiveID.getString() == ".end") {
1197 // ignore this directive for now
1202 if (DirectiveID.getString() == ".frame") {
1203 // ignore this directive for now
1204 Parser.EatToEndOfStatement();
1208 if (DirectiveID.getString() == ".set") {
1209 return parseDirectiveSet();
1212 if (DirectiveID.getString() == ".fmask") {
1213 // ignore this directive for now
1214 Parser.EatToEndOfStatement();
1218 if (DirectiveID.getString() == ".mask") {
1219 // ignore this directive for now
1220 Parser.EatToEndOfStatement();
1224 if (DirectiveID.getString() == ".gpword") {
1225 // ignore this directive for now
1226 Parser.EatToEndOfStatement();
1233 extern "C" void LLVMInitializeMipsAsmParser() {
1234 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
1235 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
1236 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
1237 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
1240 #define GET_REGISTER_MATCHER
1241 #define GET_MATCHER_IMPLEMENTATION
1242 #include "MipsGenAsmMatcher.inc"