1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/TargetRegistry.h"
36 class MipsAssemblerOptions {
38 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
40 unsigned getATRegNum() { return aTReg; }
41 bool setATReg(unsigned Reg);
43 bool isReorder() { return reorder; }
44 void setReorder() { reorder = true; }
45 void setNoreorder() { reorder = false; }
47 bool isMacro() { return macro; }
48 void setMacro() { macro = true; }
49 void setNomacro() { macro = false; }
59 class MipsAsmParser : public MCTargetAsmParser {
61 MipsTargetStreamer &getTargetStreamer() {
62 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
63 return static_cast<MipsTargetStreamer &>(TS);
68 MipsAssemblerOptions Options;
69 bool hasConsumedDollar;
71 #define GET_ASSEMBLER_HEADER
72 #include "MipsGenAsmMatcher.inc"
74 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
75 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
76 MCStreamer &Out, unsigned &ErrorInfo,
77 bool MatchingInlineAsm);
79 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
81 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
83 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
85 bool ParseDirective(AsmToken DirectiveID);
87 MipsAsmParser::OperandMatchResultTy
88 parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
90 MipsAsmParser::OperandMatchResultTy
91 parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands, int RegKind);
93 MipsAsmParser::OperandMatchResultTy
94 parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
97 MipsAsmParser::OperandMatchResultTy
98 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
100 bool parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
103 MipsAsmParser::OperandMatchResultTy
104 parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
106 MipsAsmParser::OperandMatchResultTy
107 parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
109 MipsAsmParser::OperandMatchResultTy
110 parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
112 MipsAsmParser::OperandMatchResultTy
113 parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
115 MipsAsmParser::OperandMatchResultTy
116 parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
118 MipsAsmParser::OperandMatchResultTy
119 parseAFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
121 MipsAsmParser::OperandMatchResultTy
122 parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
124 MipsAsmParser::OperandMatchResultTy
125 parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
127 MipsAsmParser::OperandMatchResultTy
128 parseFGRH32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
130 MipsAsmParser::OperandMatchResultTy
131 parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
133 MipsAsmParser::OperandMatchResultTy
134 parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
136 MipsAsmParser::OperandMatchResultTy
137 parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
139 MipsAsmParser::OperandMatchResultTy
140 parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
142 MipsAsmParser::OperandMatchResultTy
143 parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
145 MipsAsmParser::OperandMatchResultTy
146 parseMSA128BRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
148 MipsAsmParser::OperandMatchResultTy
149 parseMSA128HRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
151 MipsAsmParser::OperandMatchResultTy
152 parseMSA128WRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
154 MipsAsmParser::OperandMatchResultTy
155 parseMSA128DRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
157 MipsAsmParser::OperandMatchResultTy
158 parseMSA128CtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
160 MipsAsmParser::OperandMatchResultTy
161 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
163 MipsAsmParser::OperandMatchResultTy
164 parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
166 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
169 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
172 int tryParseRegister(bool is64BitReg);
174 bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
177 bool needsExpansion(MCInst &Inst);
179 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
180 SmallVectorImpl<MCInst> &Instructions);
181 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
182 SmallVectorImpl<MCInst> &Instructions);
183 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
184 SmallVectorImpl<MCInst> &Instructions);
185 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
186 SmallVectorImpl<MCInst> &Instructions);
187 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
188 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
190 bool reportParseError(StringRef ErrorMsg);
192 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
193 bool parseRelocOperand(const MCExpr *&Res);
195 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
197 bool isEvaluated(const MCExpr *Expr);
198 bool parseDirectiveSet();
199 bool parseDirectiveOption();
201 bool parseSetAtDirective();
202 bool parseSetNoAtDirective();
203 bool parseSetMacroDirective();
204 bool parseSetNoMacroDirective();
205 bool parseSetReorderDirective();
206 bool parseSetNoReorderDirective();
207 bool parseSetMips16Directive();
208 bool parseSetNoMips16Directive();
210 bool parseSetAssignment();
212 bool parseDirectiveWord(unsigned Size, SMLoc L);
213 bool parseDirectiveGpWord();
215 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
217 bool isMips64() const {
218 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
221 bool isFP64() const {
222 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
225 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
227 bool isMicroMips() const {
228 return STI.getFeatureBits() & Mips::FeatureMicroMips;
231 int matchRegisterName(StringRef Symbol, bool is64BitReg);
233 int matchCPURegisterName(StringRef Symbol);
235 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
237 int matchFPURegisterName(StringRef Name);
239 int matchFCCRegisterName(StringRef Name);
241 int matchACRegisterName(StringRef Name);
243 int matchMSA128RegisterName(StringRef Name);
245 int matchMSA128CtrlRegisterName(StringRef Name);
247 int regKindToRegClass(int RegKind);
249 unsigned getReg(int RC, int RegNo);
253 // Warn if RegNo is the current assembler temporary.
254 void warnIfAssemblerTemporary(int RegNo);
256 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
257 SmallVectorImpl<MCInst> &Instructions);
259 // Helper function that checks if the value of a vector index is within the
260 // boundaries of accepted values for each RegisterKind
261 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
262 bool validateMSAIndex(int Val, int RegKind);
264 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
265 if (!(STI.getFeatureBits() & Feature)) {
266 setAvailableFeatures(ComputeAvailableFeatures(
267 STI.ToggleFeature(FeatureString)));
271 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
272 if (STI.getFeatureBits() & Feature) {
273 setAvailableFeatures(ComputeAvailableFeatures(
274 STI.ToggleFeature(FeatureString)));
279 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
280 const MCInstrInfo &MII)
281 : MCTargetAsmParser(), STI(sti), Parser(parser),
282 hasConsumedDollar(false) {
283 // Initialize the set of available features.
284 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
286 // Assert exactly one ABI was chosen.
287 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
288 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
289 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
290 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
293 MCAsmParser &getParser() const { return Parser; }
294 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
300 /// MipsOperand - Instances of this class represent a parsed Mips machine
302 class MipsOperand : public MCParsedAsmOperand {
340 MipsOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
368 SMLoc StartLoc, EndLoc;
371 void addRegOperands(MCInst &Inst, unsigned N) const {
372 assert(N == 1 && "Invalid number of operands!");
373 Inst.addOperand(MCOperand::CreateReg(getReg()));
376 void addPtrRegOperands(MCInst &Inst, unsigned N) const {
377 assert(N == 1 && "Invalid number of operands!");
378 Inst.addOperand(MCOperand::CreateReg(getPtrReg()));
381 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
382 // Add as immediate when possible. Null MCExpr = 0.
384 Inst.addOperand(MCOperand::CreateImm(0));
385 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
386 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
388 Inst.addOperand(MCOperand::CreateExpr(Expr));
391 void addImmOperands(MCInst &Inst, unsigned N) const {
392 assert(N == 1 && "Invalid number of operands!");
393 const MCExpr *Expr = getImm();
397 void addMemOperands(MCInst &Inst, unsigned N) const {
398 assert(N == 2 && "Invalid number of operands!");
400 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
402 const MCExpr *Expr = getMemOff();
406 bool isReg() const { return Kind == k_Register; }
407 bool isImm() const { return Kind == k_Immediate; }
408 bool isToken() const { return Kind == k_Token; }
409 bool isMem() const { return Kind == k_Memory; }
410 bool isPtrReg() const { return Kind == k_PtrReg; }
411 bool isInvNum() const { return Kind == k_Immediate; }
412 bool isLSAImm() const { return Kind == k_LSAImm; }
414 StringRef getToken() const {
415 assert(Kind == k_Token && "Invalid access!");
416 return StringRef(Tok.Data, Tok.Length);
419 unsigned getReg() const {
420 assert((Kind == k_Register) && "Invalid access!");
424 unsigned getPtrReg() const {
425 assert((Kind == k_PtrReg) && "Invalid access!");
429 void setRegKind(RegisterKind RegKind) {
430 assert((Kind == k_Register || Kind == k_PtrReg) && "Invalid access!");
434 const MCExpr *getImm() const {
435 assert((Kind == k_Immediate || Kind == k_LSAImm) && "Invalid access!");
439 unsigned getMemBase() const {
440 assert((Kind == k_Memory) && "Invalid access!");
444 const MCExpr *getMemOff() const {
445 assert((Kind == k_Memory) && "Invalid access!");
449 static MipsOperand *CreateToken(StringRef Str, SMLoc S) {
450 MipsOperand *Op = new MipsOperand(k_Token);
451 Op->Tok.Data = Str.data();
452 Op->Tok.Length = Str.size();
458 static MipsOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
459 MipsOperand *Op = new MipsOperand(k_Register);
460 Op->Reg.RegNum = RegNum;
466 static MipsOperand *CreatePtrReg(unsigned RegNum, SMLoc S, SMLoc E) {
467 MipsOperand *Op = new MipsOperand(k_PtrReg);
468 Op->Reg.RegNum = RegNum;
474 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
475 MipsOperand *Op = new MipsOperand(k_Immediate);
482 static MipsOperand *CreateLSAImm(const MCExpr *Val, SMLoc S, SMLoc E) {
483 MipsOperand *Op = new MipsOperand(k_LSAImm);
490 static MipsOperand *CreateMem(unsigned Base, const MCExpr *Off, SMLoc S,
492 MipsOperand *Op = new MipsOperand(k_Memory);
500 bool isGPR32Asm() const {
501 return Kind == k_Register && Reg.Kind == Kind_GPR32;
503 void addRegAsmOperands(MCInst &Inst, unsigned N) const {
504 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
507 bool isGPR64Asm() const {
508 return Kind == k_Register && Reg.Kind == Kind_GPR64;
511 bool isHWRegsAsm() const {
512 assert((Kind == k_Register) && "Invalid access!");
513 return Reg.Kind == Kind_HWRegs;
516 bool isCCRAsm() const {
517 assert((Kind == k_Register) && "Invalid access!");
518 return Reg.Kind == Kind_CCRRegs;
521 bool isAFGR64Asm() const {
522 return Kind == k_Register && Reg.Kind == Kind_AFGR64Regs;
525 bool isFGR64Asm() const {
526 return Kind == k_Register && Reg.Kind == Kind_FGR64Regs;
529 bool isFGR32Asm() const {
530 return (Kind == k_Register) && Reg.Kind == Kind_FGR32Regs;
533 bool isFGRH32Asm() const {
534 return (Kind == k_Register) && Reg.Kind == Kind_FGRH32Regs;
537 bool isFCCRegsAsm() const {
538 return (Kind == k_Register) && Reg.Kind == Kind_FCCRegs;
541 bool isACC64DSPAsm() const {
542 return Kind == k_Register && Reg.Kind == Kind_ACC64DSP;
545 bool isLO32DSPAsm() const {
546 return Kind == k_Register && Reg.Kind == Kind_LO32DSP;
549 bool isHI32DSPAsm() const {
550 return Kind == k_Register && Reg.Kind == Kind_HI32DSP;
553 bool isCOP2Asm() const { return Kind == k_Register && Reg.Kind == Kind_COP2; }
555 bool isMSA128BAsm() const {
556 return Kind == k_Register && Reg.Kind == Kind_MSA128BRegs;
559 bool isMSA128HAsm() const {
560 return Kind == k_Register && Reg.Kind == Kind_MSA128HRegs;
563 bool isMSA128WAsm() const {
564 return Kind == k_Register && Reg.Kind == Kind_MSA128WRegs;
567 bool isMSA128DAsm() const {
568 return Kind == k_Register && Reg.Kind == Kind_MSA128DRegs;
571 bool isMSA128CRAsm() const {
572 return Kind == k_Register && Reg.Kind == Kind_MSA128CtrlRegs;
575 /// getStartLoc - Get the location of the first token of this operand.
576 SMLoc getStartLoc() const { return StartLoc; }
577 /// getEndLoc - Get the location of the last token of this operand.
578 SMLoc getEndLoc() const { return EndLoc; }
580 virtual void print(raw_ostream &OS) const {
581 llvm_unreachable("unimplemented!");
583 }; // class MipsOperand
587 extern const MCInstrDesc MipsInsts[];
589 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
590 return MipsInsts[Opcode];
593 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
594 SmallVectorImpl<MCInst> &Instructions) {
595 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
599 if (MCID.isBranch() || MCID.isCall()) {
600 const unsigned Opcode = Inst.getOpcode();
608 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
609 Offset = Inst.getOperand(2);
611 break; // We'll deal with this situation later on when applying fixups.
612 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
613 return Error(IDLoc, "branch target out of range");
614 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
615 return Error(IDLoc, "branch to misaligned address");
625 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
626 Offset = Inst.getOperand(1);
628 break; // We'll deal with this situation later on when applying fixups.
629 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
630 return Error(IDLoc, "branch target out of range");
631 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
632 return Error(IDLoc, "branch to misaligned address");
637 if (MCID.hasDelaySlot() && Options.isReorder()) {
638 // If this instruction has a delay slot and .set reorder is active,
639 // emit a NOP after it.
640 Instructions.push_back(Inst);
642 NopInst.setOpcode(Mips::SLL);
643 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
644 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
645 NopInst.addOperand(MCOperand::CreateImm(0));
646 Instructions.push_back(NopInst);
650 if (MCID.mayLoad() || MCID.mayStore()) {
651 // Check the offset of memory operand, if it is a symbol
652 // reference or immediate we may have to expand instructions.
653 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
654 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
655 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
656 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
657 MCOperand &Op = Inst.getOperand(i);
659 int MemOffset = Op.getImm();
660 if (MemOffset < -32768 || MemOffset > 32767) {
661 // Offset can't exceed 16bit value.
662 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
665 } else if (Op.isExpr()) {
666 const MCExpr *Expr = Op.getExpr();
667 if (Expr->getKind() == MCExpr::SymbolRef) {
668 const MCSymbolRefExpr *SR =
669 static_cast<const MCSymbolRefExpr *>(Expr);
670 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
672 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
675 } else if (!isEvaluated(Expr)) {
676 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
684 if (needsExpansion(Inst))
685 expandInstruction(Inst, IDLoc, Instructions);
687 Instructions.push_back(Inst);
692 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
694 switch (Inst.getOpcode()) {
695 case Mips::LoadImm32Reg:
696 case Mips::LoadAddr32Imm:
697 case Mips::LoadAddr32Reg:
708 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
709 SmallVectorImpl<MCInst> &Instructions) {
710 switch (Inst.getOpcode()) {
711 case Mips::LoadImm32Reg:
712 return expandLoadImm(Inst, IDLoc, Instructions);
713 case Mips::LoadAddr32Imm:
714 return expandLoadAddressImm(Inst, IDLoc, Instructions);
715 case Mips::LoadAddr32Reg:
716 return expandLoadAddressReg(Inst, IDLoc, Instructions);
718 Instructions.push_back(MCInstBuilder(Mips::ADDi)
719 .addReg(Inst.getOperand(0).getReg())
720 .addReg(Inst.getOperand(1).getReg())
721 .addImm(-Inst.getOperand(2).getImm()));
724 Instructions.push_back(MCInstBuilder(Mips::ADDiu)
725 .addReg(Inst.getOperand(0).getReg())
726 .addReg(Inst.getOperand(1).getReg())
727 .addImm(-Inst.getOperand(2).getImm()));
730 Instructions.push_back(MCInstBuilder(Mips::DADDi)
731 .addReg(Inst.getOperand(0).getReg())
732 .addReg(Inst.getOperand(1).getReg())
733 .addImm(-Inst.getOperand(2).getImm()));
736 Instructions.push_back(MCInstBuilder(Mips::DADDiu)
737 .addReg(Inst.getOperand(0).getReg())
738 .addReg(Inst.getOperand(1).getReg())
739 .addImm(-Inst.getOperand(2).getImm()));
744 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
745 SmallVectorImpl<MCInst> &Instructions) {
747 const MCOperand &ImmOp = Inst.getOperand(1);
748 assert(ImmOp.isImm() && "expected immediate operand kind");
749 const MCOperand &RegOp = Inst.getOperand(0);
750 assert(RegOp.isReg() && "expected register operand kind");
752 int ImmValue = ImmOp.getImm();
753 tmpInst.setLoc(IDLoc);
754 if (0 <= ImmValue && ImmValue <= 65535) {
755 // For 0 <= j <= 65535.
756 // li d,j => ori d,$zero,j
757 tmpInst.setOpcode(Mips::ORi);
758 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
759 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
760 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
761 Instructions.push_back(tmpInst);
762 } else if (ImmValue < 0 && ImmValue >= -32768) {
763 // For -32768 <= j < 0.
764 // li d,j => addiu d,$zero,j
765 tmpInst.setOpcode(Mips::ADDiu);
766 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
767 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
768 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
769 Instructions.push_back(tmpInst);
771 // For any other value of j that is representable as a 32-bit integer.
772 // li d,j => lui d,hi16(j)
774 tmpInst.setOpcode(Mips::LUi);
775 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
776 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
777 Instructions.push_back(tmpInst);
779 tmpInst.setOpcode(Mips::ORi);
780 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
781 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
782 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
783 tmpInst.setLoc(IDLoc);
784 Instructions.push_back(tmpInst);
789 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
790 SmallVectorImpl<MCInst> &Instructions) {
792 const MCOperand &ImmOp = Inst.getOperand(2);
793 assert(ImmOp.isImm() && "expected immediate operand kind");
794 const MCOperand &SrcRegOp = Inst.getOperand(1);
795 assert(SrcRegOp.isReg() && "expected register operand kind");
796 const MCOperand &DstRegOp = Inst.getOperand(0);
797 assert(DstRegOp.isReg() && "expected register operand kind");
798 int ImmValue = ImmOp.getImm();
799 if (-32768 <= ImmValue && ImmValue <= 65535) {
800 // For -32768 <= j <= 65535.
801 // la d,j(s) => addiu d,s,j
802 tmpInst.setOpcode(Mips::ADDiu);
803 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
804 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
805 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
806 Instructions.push_back(tmpInst);
808 // For any other value of j that is representable as a 32-bit integer.
809 // la d,j(s) => lui d,hi16(j)
812 tmpInst.setOpcode(Mips::LUi);
813 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
814 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
815 Instructions.push_back(tmpInst);
817 tmpInst.setOpcode(Mips::ORi);
818 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
819 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
820 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
821 Instructions.push_back(tmpInst);
823 tmpInst.setOpcode(Mips::ADDu);
824 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
825 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
826 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
827 Instructions.push_back(tmpInst);
832 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
833 SmallVectorImpl<MCInst> &Instructions) {
835 const MCOperand &ImmOp = Inst.getOperand(1);
836 assert(ImmOp.isImm() && "expected immediate operand kind");
837 const MCOperand &RegOp = Inst.getOperand(0);
838 assert(RegOp.isReg() && "expected register operand kind");
839 int ImmValue = ImmOp.getImm();
840 if (-32768 <= ImmValue && ImmValue <= 65535) {
841 // For -32768 <= j <= 65535.
842 // la d,j => addiu d,$zero,j
843 tmpInst.setOpcode(Mips::ADDiu);
844 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
845 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
846 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
847 Instructions.push_back(tmpInst);
849 // For any other value of j that is representable as a 32-bit integer.
850 // la d,j => lui d,hi16(j)
852 tmpInst.setOpcode(Mips::LUi);
853 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
854 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
855 Instructions.push_back(tmpInst);
857 tmpInst.setOpcode(Mips::ORi);
858 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
859 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
860 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
861 Instructions.push_back(tmpInst);
865 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
866 SmallVectorImpl<MCInst> &Instructions,
867 bool isLoad, bool isImmOpnd) {
868 const MCSymbolRefExpr *SR;
870 unsigned ImmOffset, HiOffset, LoOffset;
871 const MCExpr *ExprOffset;
873 unsigned AtRegNum = getReg(
874 (isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
875 // 1st operand is either the source or destination register.
876 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
877 unsigned RegOpNum = Inst.getOperand(0).getReg();
878 // 2nd operand is the base register.
879 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
880 unsigned BaseRegNum = Inst.getOperand(1).getReg();
881 // 3rd operand is either an immediate or expression.
883 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
884 ImmOffset = Inst.getOperand(2).getImm();
885 LoOffset = ImmOffset & 0x0000ffff;
886 HiOffset = (ImmOffset & 0xffff0000) >> 16;
887 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
888 if (LoOffset & 0x8000)
891 ExprOffset = Inst.getOperand(2).getExpr();
892 // All instructions will have the same location.
893 TempInst.setLoc(IDLoc);
894 // 1st instruction in expansion is LUi. For load instruction we can use
895 // the dst register as a temporary if base and dst are different,
896 // but for stores we must use $at.
897 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
898 TempInst.setOpcode(Mips::LUi);
899 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
901 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
903 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
904 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
905 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
906 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
908 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
910 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
911 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
914 // Add the instruction to the list.
915 Instructions.push_back(TempInst);
916 // Prepare TempInst for next instruction.
918 // Add temp register to base.
919 TempInst.setOpcode(Mips::ADDu);
920 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
921 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
922 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
923 Instructions.push_back(TempInst);
925 // And finally, create original instruction with low part
926 // of offset and new base.
927 TempInst.setOpcode(Inst.getOpcode());
928 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
929 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
931 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
933 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
934 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
935 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
937 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
939 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
940 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
943 Instructions.push_back(TempInst);
947 bool MipsAsmParser::MatchAndEmitInstruction(
948 SMLoc IDLoc, unsigned &Opcode,
949 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
950 unsigned &ErrorInfo, bool MatchingInlineAsm) {
952 SmallVector<MCInst, 8> Instructions;
953 unsigned MatchResult =
954 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
956 switch (MatchResult) {
959 case Match_Success: {
960 if (processInstruction(Inst, IDLoc, Instructions))
962 for (unsigned i = 0; i < Instructions.size(); i++)
963 Out.EmitInstruction(Instructions[i], STI);
966 case Match_MissingFeature:
967 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
969 case Match_InvalidOperand: {
970 SMLoc ErrorLoc = IDLoc;
971 if (ErrorInfo != ~0U) {
972 if (ErrorInfo >= Operands.size())
973 return Error(IDLoc, "too few operands for instruction");
975 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
976 if (ErrorLoc == SMLoc())
980 return Error(ErrorLoc, "invalid operand for instruction");
982 case Match_MnemonicFail:
983 return Error(IDLoc, "invalid instruction");
988 void MipsAsmParser::warnIfAssemblerTemporary(int RegNo) {
989 if ((RegNo != 0) && ((int)Options.getATRegNum() == RegNo)) {
991 Warning(getLexer().getLoc(), "Used $at without \".set noat\"");
993 Warning(getLexer().getLoc(), Twine("Used $") + Twine(RegNo) +
994 " with \".set at=$" + Twine(RegNo) +
999 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1002 CC = StringSwitch<unsigned>(Name)
1037 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1038 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1039 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1040 if (isMips64() && 8 <= CC && CC <= 11)
1043 if (CC == -1 && isMips64())
1044 CC = StringSwitch<unsigned>(Name)
1054 warnIfAssemblerTemporary(CC);
1059 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1061 if (Name[0] == 'f') {
1062 StringRef NumString = Name.substr(1);
1064 if (NumString.getAsInteger(10, IntVal))
1065 return -1; // This is not an integer.
1066 if (IntVal > 31) // Maximum index for fpu register.
1073 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1075 if (Name.startswith("fcc")) {
1076 StringRef NumString = Name.substr(3);
1078 if (NumString.getAsInteger(10, IntVal))
1079 return -1; // This is not an integer.
1080 if (IntVal > 7) // There are only 8 fcc registers.
1087 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1089 if (Name.startswith("ac")) {
1090 StringRef NumString = Name.substr(2);
1092 if (NumString.getAsInteger(10, IntVal))
1093 return -1; // This is not an integer.
1094 if (IntVal > 3) // There are only 3 acc registers.
1101 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1104 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1113 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1116 CC = StringSwitch<unsigned>(Name)
1119 .Case("msaaccess", 2)
1121 .Case("msamodify", 4)
1122 .Case("msarequest", 5)
1124 .Case("msaunmap", 7)
1130 int MipsAsmParser::matchRegisterName(StringRef Name, bool is64BitReg) {
1133 CC = matchCPURegisterName(Name);
1135 return matchRegisterByNumber(CC, is64BitReg ? Mips::GPR64RegClassID
1136 : Mips::GPR32RegClassID);
1137 CC = matchFPURegisterName(Name);
1138 // TODO: decide about fpu register class
1140 return matchRegisterByNumber(CC, isFP64() ? Mips::FGR64RegClassID
1141 : Mips::FGR32RegClassID);
1142 return matchMSA128RegisterName(Name);
1145 int MipsAsmParser::regKindToRegClass(int RegKind) {
1148 case MipsOperand::Kind_GPR32:
1149 return Mips::GPR32RegClassID;
1150 case MipsOperand::Kind_GPR64:
1151 return Mips::GPR64RegClassID;
1152 case MipsOperand::Kind_HWRegs:
1153 return Mips::HWRegsRegClassID;
1154 case MipsOperand::Kind_FGR32Regs:
1155 return Mips::FGR32RegClassID;
1156 case MipsOperand::Kind_FGRH32Regs:
1157 return Mips::FGRH32RegClassID;
1158 case MipsOperand::Kind_FGR64Regs:
1159 return Mips::FGR64RegClassID;
1160 case MipsOperand::Kind_AFGR64Regs:
1161 return Mips::AFGR64RegClassID;
1162 case MipsOperand::Kind_CCRRegs:
1163 return Mips::CCRRegClassID;
1164 case MipsOperand::Kind_ACC64DSP:
1165 return Mips::ACC64DSPRegClassID;
1166 case MipsOperand::Kind_FCCRegs:
1167 return Mips::FCCRegClassID;
1168 case MipsOperand::Kind_MSA128BRegs:
1169 return Mips::MSA128BRegClassID;
1170 case MipsOperand::Kind_MSA128HRegs:
1171 return Mips::MSA128HRegClassID;
1172 case MipsOperand::Kind_MSA128WRegs:
1173 return Mips::MSA128WRegClassID;
1174 case MipsOperand::Kind_MSA128DRegs:
1175 return Mips::MSA128DRegClassID;
1176 case MipsOperand::Kind_MSA128CtrlRegs:
1177 return Mips::MSACtrlRegClassID;
1183 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1191 int MipsAsmParser::getATReg() {
1192 int AT = Options.getATRegNum();
1194 TokError("Pseudo instruction requires $at, which is not available");
1198 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1199 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1202 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1204 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
1207 if (RegClass == Mips::GPR32RegClassID || RegClass == Mips::GPR64RegClassID)
1208 warnIfAssemblerTemporary(RegNum);
1210 return getReg(RegClass, RegNum);
1213 int MipsAsmParser::tryParseRegister(bool is64BitReg) {
1214 const AsmToken &Tok = Parser.getTok();
1217 if (Tok.is(AsmToken::Identifier)) {
1218 std::string lowerCase = Tok.getString().lower();
1219 RegNum = matchRegisterName(lowerCase, is64BitReg);
1220 } else if (Tok.is(AsmToken::Integer))
1221 RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
1222 is64BitReg ? Mips::GPR64RegClassID
1223 : Mips::GPR32RegClassID);
1227 bool MipsAsmParser::tryParseRegisterOperand(
1228 SmallVectorImpl<MCParsedAsmOperand *> &Operands, bool is64BitReg) {
1230 SMLoc S = Parser.getTok().getLoc();
1233 RegNo = tryParseRegister(is64BitReg);
1238 MipsOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1239 Parser.Lex(); // Eat register token.
1244 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1245 StringRef Mnemonic) {
1246 // Check if the current operand has a custom associated parser, if so, try to
1247 // custom parse the operand, or fallback to the general approach.
1248 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1249 if (ResTy == MatchOperand_Success)
1251 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1252 // there was a match, but an error occurred, in which case, just return that
1253 // the operand parsing failed.
1254 if (ResTy == MatchOperand_ParseFail)
1257 switch (getLexer().getKind()) {
1259 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1261 case AsmToken::Dollar: {
1262 // Parse the register.
1263 SMLoc S = Parser.getTok().getLoc();
1264 Parser.Lex(); // Eat dollar token.
1265 // Parse the register operand.
1266 if (!tryParseRegisterOperand(Operands, isMips64())) {
1267 if (getLexer().is(AsmToken::LParen)) {
1268 // Check if it is indexed addressing operand.
1269 Operands.push_back(MipsOperand::CreateToken("(", S));
1270 Parser.Lex(); // Eat the parenthesis.
1271 if (getLexer().isNot(AsmToken::Dollar))
1274 Parser.Lex(); // Eat the dollar
1275 if (tryParseRegisterOperand(Operands, isMips64()))
1278 if (!getLexer().is(AsmToken::RParen))
1281 S = Parser.getTok().getLoc();
1282 Operands.push_back(MipsOperand::CreateToken(")", S));
1287 // Maybe it is a symbol reference.
1288 StringRef Identifier;
1289 if (Parser.parseIdentifier(Identifier))
1292 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1293 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1294 // Otherwise create a symbol reference.
1296 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1298 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1301 case AsmToken::Identifier:
1302 // For instruction aliases like "bc1f $Label" dedicated parser will
1303 // eat the '$' sign before failing. So in order to look for appropriate
1304 // label we must check first if we have already consumed '$'.
1305 if (hasConsumedDollar) {
1306 hasConsumedDollar = false;
1307 SMLoc S = Parser.getTok().getLoc();
1308 StringRef Identifier;
1309 if (Parser.parseIdentifier(Identifier))
1312 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1313 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1314 // Create a symbol reference.
1316 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1318 Operands.push_back(MipsOperand::CreateImm(Res, S, E));
1321 // Look for the existing symbol, we should check if
1322 // we need to assign the proper RegisterKind.
1323 if (searchSymbolAlias(Operands, MipsOperand::Kind_None))
1325 // Else drop to expression parsing.
1326 case AsmToken::LParen:
1327 case AsmToken::Minus:
1328 case AsmToken::Plus:
1329 case AsmToken::Integer:
1330 case AsmToken::String: {
1331 // Quoted label names.
1332 const MCExpr *IdVal;
1333 SMLoc S = Parser.getTok().getLoc();
1334 if (getParser().parseExpression(IdVal))
1336 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1337 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1340 case AsmToken::Percent: {
1341 // It is a symbol reference or constant expression.
1342 const MCExpr *IdVal;
1343 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1344 if (parseRelocOperand(IdVal))
1347 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1349 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1351 } // case AsmToken::Percent
1352 } // switch(getLexer().getKind())
1356 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1357 StringRef RelocStr) {
1359 // Check the type of the expression.
1360 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1361 // It's a constant, evaluate lo or hi value.
1362 if (RelocStr == "lo") {
1363 short Val = MCE->getValue();
1364 Res = MCConstantExpr::Create(Val, getContext());
1365 } else if (RelocStr == "hi") {
1366 int Val = MCE->getValue();
1367 int LoSign = Val & 0x8000;
1368 Val = (Val & 0xffff0000) >> 16;
1369 // Lower part is treated as a signed int, so if it is negative
1370 // we must add 1 to the hi part to compensate.
1373 Res = MCConstantExpr::Create(Val, getContext());
1375 llvm_unreachable("Invalid RelocStr value");
1380 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1381 // It's a symbol, create a symbolic expression from the symbol.
1382 StringRef Symbol = MSRE->getSymbol().getName();
1383 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1384 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1388 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1389 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1391 // Check for %hi(sym1-sym2) and %lo(sym1-sym2) expressions.
1392 if (isa<MCSymbolRefExpr>(BE->getLHS()) && isa<MCSymbolRefExpr>(BE->getRHS())
1393 && (VK == MCSymbolRefExpr::VK_Mips_ABS_HI
1394 || VK == MCSymbolRefExpr::VK_Mips_ABS_LO)) {
1395 // Create target expression for %hi(sym1-sym2) and %lo(sym1-sym2).
1396 if (VK == MCSymbolRefExpr::VK_Mips_ABS_HI)
1397 return MipsMCExpr::CreateHi(Expr, getContext());
1398 return MipsMCExpr::CreateLo(Expr, getContext());
1401 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1402 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1403 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1407 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1408 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1409 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1412 // Just return the original expression.
1416 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1418 switch (Expr->getKind()) {
1419 case MCExpr::Constant:
1421 case MCExpr::SymbolRef:
1422 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1423 case MCExpr::Binary:
1424 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1425 if (!isEvaluated(BE->getLHS()))
1427 return isEvaluated(BE->getRHS());
1430 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1431 case MCExpr::Target:
1437 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1438 Parser.Lex(); // Eat the % token.
1439 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1440 if (Tok.isNot(AsmToken::Identifier))
1443 std::string Str = Tok.getIdentifier().str();
1445 Parser.Lex(); // Eat the identifier.
1446 // Now make an expression from the rest of the operand.
1447 const MCExpr *IdVal;
1450 if (getLexer().getKind() == AsmToken::LParen) {
1452 Parser.Lex(); // Eat the '(' token.
1453 if (getLexer().getKind() == AsmToken::Percent) {
1454 Parser.Lex(); // Eat the % token.
1455 const AsmToken &nextTok = Parser.getTok();
1456 if (nextTok.isNot(AsmToken::Identifier))
1459 Str += nextTok.getIdentifier();
1460 Parser.Lex(); // Eat the identifier.
1461 if (getLexer().getKind() != AsmToken::LParen)
1466 if (getParser().parseParenExpression(IdVal, EndLoc))
1469 while (getLexer().getKind() == AsmToken::RParen)
1470 Parser.Lex(); // Eat the ')' token.
1473 return true; // Parenthesis must follow the relocation operand.
1475 Res = evaluateRelocExpr(IdVal, Str);
1479 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1481 StartLoc = Parser.getTok().getLoc();
1482 RegNo = tryParseRegister(isMips64());
1483 EndLoc = Parser.getTok().getLoc();
1484 return (RegNo == (unsigned)-1);
1487 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1491 while (getLexer().getKind() == AsmToken::LParen)
1494 switch (getLexer().getKind()) {
1497 case AsmToken::Identifier:
1498 case AsmToken::LParen:
1499 case AsmToken::Integer:
1500 case AsmToken::Minus:
1501 case AsmToken::Plus:
1503 Result = getParser().parseParenExpression(Res, S);
1505 Result = (getParser().parseExpression(Res));
1506 while (getLexer().getKind() == AsmToken::RParen)
1509 case AsmToken::Percent:
1510 Result = parseRelocOperand(Res);
1515 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1516 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1518 const MCExpr *IdVal = 0;
1520 bool isParenExpr = false;
1521 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1522 // First operand is the offset.
1523 S = Parser.getTok().getLoc();
1525 if (getLexer().getKind() == AsmToken::LParen) {
1530 if (getLexer().getKind() != AsmToken::Dollar) {
1531 if (parseMemOffset(IdVal, isParenExpr))
1532 return MatchOperand_ParseFail;
1534 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1535 if (Tok.isNot(AsmToken::LParen)) {
1536 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1537 if (Mnemonic->getToken() == "la") {
1539 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1540 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E));
1541 return MatchOperand_Success;
1543 if (Tok.is(AsmToken::EndOfStatement)) {
1545 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1547 // Zero register assumed, add a memory operand with ZERO as its base.
1548 Operands.push_back(MipsOperand::CreateMem(
1549 isMips64() ? Mips::ZERO_64 : Mips::ZERO, IdVal, S, E));
1550 return MatchOperand_Success;
1552 Error(Parser.getTok().getLoc(), "'(' expected");
1553 return MatchOperand_ParseFail;
1556 Parser.Lex(); // Eat the '(' token.
1559 Res = parseRegs(Operands, isMips64() ? (int)MipsOperand::Kind_GPR64
1560 : (int)MipsOperand::Kind_GPR32);
1561 if (Res != MatchOperand_Success)
1564 if (Parser.getTok().isNot(AsmToken::RParen)) {
1565 Error(Parser.getTok().getLoc(), "')' expected");
1566 return MatchOperand_ParseFail;
1569 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1571 Parser.Lex(); // Eat the ')' token.
1574 IdVal = MCConstantExpr::Create(0, getContext());
1576 // Replace the register operand with the memory operand.
1577 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1578 int RegNo = op->getReg();
1579 // Remove the register from the operands.
1580 Operands.pop_back();
1581 // Add the memory operand.
1582 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1584 if (IdVal->EvaluateAsAbsolute(Imm))
1585 IdVal = MCConstantExpr::Create(Imm, getContext());
1586 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1587 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1591 Operands.push_back(MipsOperand::CreateMem(RegNo, IdVal, S, E));
1593 return MatchOperand_Success;
1596 bool MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1598 // If the first token is not '$' we have an error.
1599 if (Parser.getTok().isNot(AsmToken::Dollar))
1602 SMLoc S = Parser.getTok().getLoc();
1604 AsmToken::TokenKind TkKind = getLexer().getKind();
1607 if (TkKind == AsmToken::Integer) {
1608 Reg = matchRegisterByNumber(Parser.getTok().getIntVal(),
1609 regKindToRegClass(RegKind));
1612 } else if (TkKind == AsmToken::Identifier) {
1613 if ((Reg = matchCPURegisterName(Parser.getTok().getString().lower())) == -1)
1615 Reg = getReg(regKindToRegClass(RegKind), Reg);
1620 MipsOperand *Op = MipsOperand::CreatePtrReg(Reg, S, Parser.getTok().getLoc());
1621 Op->setRegKind((MipsOperand::RegisterKind)RegKind);
1622 Operands.push_back(Op);
1627 MipsAsmParser::OperandMatchResultTy
1628 MipsAsmParser::parsePtrReg(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1629 MipsOperand::RegisterKind RegKind =
1630 isN64() ? MipsOperand::Kind_GPR64 : MipsOperand::Kind_GPR32;
1632 // Parse index register.
1633 if (!parsePtrReg(Operands, RegKind))
1634 return MatchOperand_NoMatch;
1637 if (Parser.getTok().isNot(AsmToken::LParen))
1638 return MatchOperand_NoMatch;
1640 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1643 // Parse base register.
1644 if (!parsePtrReg(Operands, RegKind))
1645 return MatchOperand_NoMatch;
1648 if (Parser.getTok().isNot(AsmToken::RParen))
1649 return MatchOperand_NoMatch;
1651 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1654 return MatchOperand_Success;
1657 MipsAsmParser::OperandMatchResultTy
1658 MipsAsmParser::parseRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1660 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1661 if (getLexer().getKind() == AsmToken::Identifier && !hasConsumedDollar) {
1662 if (searchSymbolAlias(Operands, Kind))
1663 return MatchOperand_Success;
1664 return MatchOperand_NoMatch;
1666 SMLoc S = Parser.getTok().getLoc();
1667 // If the first token is not '$', we have an error.
1668 if (Parser.getTok().isNot(AsmToken::Dollar) && !hasConsumedDollar)
1669 return MatchOperand_NoMatch;
1670 if (!hasConsumedDollar) {
1671 Parser.Lex(); // Eat the '$'
1672 hasConsumedDollar = true;
1674 if (getLexer().getKind() == AsmToken::Identifier) {
1676 std::string RegName = Parser.getTok().getString().lower();
1677 // Match register by name
1679 case MipsOperand::Kind_GPR32:
1680 case MipsOperand::Kind_GPR64:
1681 RegNum = matchCPURegisterName(RegName);
1683 case MipsOperand::Kind_AFGR64Regs:
1684 case MipsOperand::Kind_FGR64Regs:
1685 case MipsOperand::Kind_FGR32Regs:
1686 case MipsOperand::Kind_FGRH32Regs:
1687 RegNum = matchFPURegisterName(RegName);
1688 if (RegKind == MipsOperand::Kind_AFGR64Regs)
1690 else if (RegKind == MipsOperand::Kind_FGRH32Regs && !isFP64())
1691 if (RegNum != -1 && RegNum % 2 != 0)
1692 Warning(S, "Float register should be even.");
1694 case MipsOperand::Kind_FCCRegs:
1695 RegNum = matchFCCRegisterName(RegName);
1697 case MipsOperand::Kind_ACC64DSP:
1698 RegNum = matchACRegisterName(RegName);
1701 break; // No match, value is set to -1.
1703 // No match found, return _NoMatch to give a chance to other round.
1705 return MatchOperand_NoMatch;
1707 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1709 return MatchOperand_NoMatch;
1712 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1713 Op->setRegKind(Kind);
1714 Operands.push_back(Op);
1715 hasConsumedDollar = false;
1716 Parser.Lex(); // Eat the register name.
1717 return MatchOperand_Success;
1718 } else if (getLexer().getKind() == AsmToken::Integer) {
1719 unsigned RegNum = Parser.getTok().getIntVal();
1720 if (Kind == MipsOperand::Kind_HWRegs) {
1722 return MatchOperand_NoMatch;
1723 // Only hwreg 29 is supported, found at index 0.
1726 int Reg = matchRegisterByNumber(RegNum, regKindToRegClass(Kind));
1728 return MatchOperand_NoMatch;
1729 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
1730 Op->setRegKind(Kind);
1731 Operands.push_back(Op);
1732 hasConsumedDollar = false;
1733 Parser.Lex(); // Eat the register number.
1734 if ((RegKind == MipsOperand::Kind_GPR32) &&
1735 (getLexer().is(AsmToken::LParen))) {
1736 // Check if it is indexed addressing operand.
1737 Operands.push_back(MipsOperand::CreateToken("(", getLexer().getLoc()));
1738 Parser.Lex(); // Eat the parenthesis.
1739 if (parseRegs(Operands, RegKind) != MatchOperand_Success)
1740 return MatchOperand_NoMatch;
1741 if (getLexer().isNot(AsmToken::RParen))
1742 return MatchOperand_NoMatch;
1743 Operands.push_back(MipsOperand::CreateToken(")", getLexer().getLoc()));
1746 return MatchOperand_Success;
1748 return MatchOperand_NoMatch;
1751 bool MipsAsmParser::validateMSAIndex(int Val, int RegKind) {
1752 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1760 case MipsOperand::Kind_MSA128BRegs:
1762 case MipsOperand::Kind_MSA128HRegs:
1764 case MipsOperand::Kind_MSA128WRegs:
1766 case MipsOperand::Kind_MSA128DRegs:
1771 MipsAsmParser::OperandMatchResultTy
1772 MipsAsmParser::parseMSARegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1774 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1775 SMLoc S = Parser.getTok().getLoc();
1776 std::string RegName;
1778 if (Parser.getTok().isNot(AsmToken::Dollar))
1779 return MatchOperand_NoMatch;
1783 return MatchOperand_ParseFail;
1784 case MipsOperand::Kind_MSA128BRegs:
1785 case MipsOperand::Kind_MSA128HRegs:
1786 case MipsOperand::Kind_MSA128WRegs:
1787 case MipsOperand::Kind_MSA128DRegs:
1791 Parser.Lex(); // Eat the '$'.
1792 if (getLexer().getKind() == AsmToken::Identifier)
1793 RegName = Parser.getTok().getString().lower();
1795 return MatchOperand_ParseFail;
1797 int RegNum = matchMSA128RegisterName(RegName);
1799 if (RegNum < 0 || RegNum > 31)
1800 return MatchOperand_ParseFail;
1802 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1804 return MatchOperand_ParseFail;
1806 MipsOperand *Op = MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1807 Op->setRegKind(Kind);
1808 Operands.push_back(Op);
1810 Parser.Lex(); // Eat the register identifier.
1812 // MSA registers may be suffixed with an index in the form of:
1813 // 1) Immediate expression.
1814 // 2) General Purpose Register.
1816 // 1) copy_s.b $29,$w0[0]
1817 // 2) sld.b $w0,$w1[$1]
1819 if (Parser.getTok().isNot(AsmToken::LBrac))
1820 return MatchOperand_Success;
1822 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1824 Operands.push_back(MipsOperand::CreateToken("[", Parser.getTok().getLoc()));
1825 Parser.Lex(); // Parse the '[' token.
1827 if (Parser.getTok().is(AsmToken::Dollar)) {
1828 // This must be a GPR.
1830 SMLoc VIdx = Parser.getTok().getLoc();
1831 Parser.Lex(); // Parse the '$' token.
1833 // GPR have aliases and we must account for that. Example: $30 == $fp
1834 if (getLexer().getKind() == AsmToken::Integer) {
1835 unsigned RegNum = Parser.getTok().getIntVal();
1836 int Reg = matchRegisterByNumber(
1837 RegNum, regKindToRegClass(MipsOperand::Kind_GPR32));
1839 Error(VIdx, "invalid general purpose register");
1840 return MatchOperand_ParseFail;
1843 RegOp = MipsOperand::CreateReg(Reg, VIdx, Parser.getTok().getLoc());
1844 } else if (getLexer().getKind() == AsmToken::Identifier) {
1846 std::string RegName = Parser.getTok().getString().lower();
1848 RegNum = matchCPURegisterName(RegName);
1850 Error(VIdx, "general purpose register expected");
1851 return MatchOperand_ParseFail;
1853 RegNum = getReg(regKindToRegClass(MipsOperand::Kind_GPR32), RegNum);
1854 RegOp = MipsOperand::CreateReg(RegNum, VIdx, Parser.getTok().getLoc());
1856 return MatchOperand_ParseFail;
1858 RegOp->setRegKind(MipsOperand::Kind_GPR32);
1859 Operands.push_back(RegOp);
1860 Parser.Lex(); // Eat the register identifier.
1862 if (Parser.getTok().isNot(AsmToken::RBrac))
1863 return MatchOperand_ParseFail;
1865 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1866 Parser.Lex(); // Parse the ']' token.
1868 return MatchOperand_Success;
1871 // The index must be a constant expression then.
1872 SMLoc VIdx = Parser.getTok().getLoc();
1873 const MCExpr *ImmVal;
1875 if (getParser().parseExpression(ImmVal))
1876 return MatchOperand_ParseFail;
1878 const MCConstantExpr *expr = dyn_cast<MCConstantExpr>(ImmVal);
1879 if (!expr || !validateMSAIndex((int)expr->getValue(), Kind)) {
1880 Error(VIdx, "invalid immediate value");
1881 return MatchOperand_ParseFail;
1884 SMLoc E = Parser.getTok().getEndLoc();
1886 if (Parser.getTok().isNot(AsmToken::RBrac))
1887 return MatchOperand_ParseFail;
1890 Mnemonic->getToken() == "insve.b" || Mnemonic->getToken() == "insve.h" ||
1891 Mnemonic->getToken() == "insve.w" || Mnemonic->getToken() == "insve.d";
1893 // The second vector index of insve instructions is always 0.
1894 if (insve && Operands.size() > 6) {
1895 if (expr->getValue() != 0) {
1896 Error(VIdx, "immediate value must be 0");
1897 return MatchOperand_ParseFail;
1899 Operands.push_back(MipsOperand::CreateToken("0", VIdx));
1901 Operands.push_back(MipsOperand::CreateImm(expr, VIdx, E));
1903 Operands.push_back(MipsOperand::CreateToken("]", Parser.getTok().getLoc()));
1905 Parser.Lex(); // Parse the ']' token.
1907 return MatchOperand_Success;
1910 MipsAsmParser::OperandMatchResultTy
1911 MipsAsmParser::parseMSACtrlRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1913 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
1915 if (Kind != MipsOperand::Kind_MSA128CtrlRegs)
1916 return MatchOperand_NoMatch;
1918 if (Parser.getTok().isNot(AsmToken::Dollar))
1919 return MatchOperand_ParseFail;
1921 SMLoc S = Parser.getTok().getLoc();
1923 Parser.Lex(); // Eat the '$' symbol.
1926 if (getLexer().getKind() == AsmToken::Identifier)
1927 RegNum = matchMSA128CtrlRegisterName(Parser.getTok().getString().lower());
1928 else if (getLexer().getKind() == AsmToken::Integer)
1929 RegNum = Parser.getTok().getIntVal();
1931 return MatchOperand_ParseFail;
1933 if (RegNum < 0 || RegNum > 7)
1934 return MatchOperand_ParseFail;
1936 int RegVal = getReg(regKindToRegClass(Kind), RegNum);
1938 return MatchOperand_ParseFail;
1940 MipsOperand *RegOp =
1941 MipsOperand::CreateReg(RegVal, S, Parser.getTok().getLoc());
1942 RegOp->setRegKind(MipsOperand::Kind_MSA128CtrlRegs);
1943 Operands.push_back(RegOp);
1944 Parser.Lex(); // Eat the register identifier.
1946 return MatchOperand_Success;
1949 MipsAsmParser::OperandMatchResultTy
1950 MipsAsmParser::parseGPR64(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1953 return MatchOperand_NoMatch;
1954 return parseRegs(Operands, (int)MipsOperand::Kind_GPR64);
1957 MipsAsmParser::OperandMatchResultTy
1958 MipsAsmParser::parseGPR32(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1959 return parseRegs(Operands, (int)MipsOperand::Kind_GPR32);
1962 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseAFGR64Regs(
1963 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1966 return MatchOperand_NoMatch;
1967 return parseRegs(Operands, (int)MipsOperand::Kind_AFGR64Regs);
1970 MipsAsmParser::OperandMatchResultTy
1971 MipsAsmParser::parseFGR64Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1973 return MatchOperand_NoMatch;
1974 return parseRegs(Operands, (int)MipsOperand::Kind_FGR64Regs);
1977 MipsAsmParser::OperandMatchResultTy
1978 MipsAsmParser::parseFGR32Regs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1979 return parseRegs(Operands, (int)MipsOperand::Kind_FGR32Regs);
1982 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseFGRH32Regs(
1983 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1984 return parseRegs(Operands, (int)MipsOperand::Kind_FGRH32Regs);
1987 MipsAsmParser::OperandMatchResultTy
1988 MipsAsmParser::parseFCCRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1989 return parseRegs(Operands, (int)MipsOperand::Kind_FCCRegs);
1992 MipsAsmParser::OperandMatchResultTy
1993 MipsAsmParser::parseACC64DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1994 return parseRegs(Operands, (int)MipsOperand::Kind_ACC64DSP);
1997 MipsAsmParser::OperandMatchResultTy
1998 MipsAsmParser::parseLO32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1999 // If the first token is not '$' we have an error.
2000 if (Parser.getTok().isNot(AsmToken::Dollar))
2001 return MatchOperand_NoMatch;
2003 SMLoc S = Parser.getTok().getLoc();
2004 Parser.Lex(); // Eat the '$'
2006 const AsmToken &Tok = Parser.getTok(); // Get next token.
2008 if (Tok.isNot(AsmToken::Identifier))
2009 return MatchOperand_NoMatch;
2011 if (!Tok.getIdentifier().startswith("ac"))
2012 return MatchOperand_NoMatch;
2014 StringRef NumString = Tok.getIdentifier().substr(2);
2017 if (NumString.getAsInteger(10, IntVal))
2018 return MatchOperand_NoMatch;
2020 unsigned Reg = matchRegisterByNumber(IntVal, Mips::LO32DSPRegClassID);
2022 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2023 Op->setRegKind(MipsOperand::Kind_LO32DSP);
2024 Operands.push_back(Op);
2026 Parser.Lex(); // Eat the register number.
2027 return MatchOperand_Success;
2030 MipsAsmParser::OperandMatchResultTy
2031 MipsAsmParser::parseHI32DSP(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2032 // If the first token is not '$' we have an error.
2033 if (Parser.getTok().isNot(AsmToken::Dollar))
2034 return MatchOperand_NoMatch;
2036 SMLoc S = Parser.getTok().getLoc();
2037 Parser.Lex(); // Eat the '$'
2039 const AsmToken &Tok = Parser.getTok(); // Get next token.
2041 if (Tok.isNot(AsmToken::Identifier))
2042 return MatchOperand_NoMatch;
2044 if (!Tok.getIdentifier().startswith("ac"))
2045 return MatchOperand_NoMatch;
2047 StringRef NumString = Tok.getIdentifier().substr(2);
2050 if (NumString.getAsInteger(10, IntVal))
2051 return MatchOperand_NoMatch;
2053 unsigned Reg = matchRegisterByNumber(IntVal, Mips::HI32DSPRegClassID);
2055 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2056 Op->setRegKind(MipsOperand::Kind_HI32DSP);
2057 Operands.push_back(Op);
2059 Parser.Lex(); // Eat the register number.
2060 return MatchOperand_Success;
2063 MipsAsmParser::OperandMatchResultTy
2064 MipsAsmParser::parseCOP2(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2065 // If the first token is not '$' we have an error.
2066 if (Parser.getTok().isNot(AsmToken::Dollar))
2067 return MatchOperand_NoMatch;
2069 SMLoc S = Parser.getTok().getLoc();
2070 Parser.Lex(); // Eat the '$'
2072 const AsmToken &Tok = Parser.getTok(); // Get next token.
2074 if (Tok.isNot(AsmToken::Integer))
2075 return MatchOperand_NoMatch;
2077 unsigned IntVal = Tok.getIntVal();
2079 unsigned Reg = matchRegisterByNumber(IntVal, Mips::COP2RegClassID);
2081 MipsOperand *Op = MipsOperand::CreateReg(Reg, S, Parser.getTok().getLoc());
2082 Op->setRegKind(MipsOperand::Kind_COP2);
2083 Operands.push_back(Op);
2085 Parser.Lex(); // Eat the register number.
2086 return MatchOperand_Success;
2089 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128BRegs(
2090 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2091 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128BRegs);
2094 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128HRegs(
2095 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2096 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128HRegs);
2099 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128WRegs(
2100 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2101 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128WRegs);
2104 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128DRegs(
2105 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2106 return parseMSARegs(Operands, (int)MipsOperand::Kind_MSA128DRegs);
2109 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMSA128CtrlRegs(
2110 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2111 return parseMSACtrlRegs(Operands, (int)MipsOperand::Kind_MSA128CtrlRegs);
2114 bool MipsAsmParser::searchSymbolAlias(
2115 SmallVectorImpl<MCParsedAsmOperand *> &Operands, unsigned RegKind) {
2117 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
2119 SMLoc S = Parser.getTok().getLoc();
2121 if (Sym->isVariable())
2122 Expr = Sym->getVariableValue();
2125 if (Expr->getKind() == MCExpr::SymbolRef) {
2126 MipsOperand::RegisterKind Kind = (MipsOperand::RegisterKind)RegKind;
2127 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
2128 const StringRef DefSymbol = Ref->getSymbol().getName();
2129 if (DefSymbol.startswith("$")) {
2131 APInt IntVal(32, -1);
2132 if (!DefSymbol.substr(1).getAsInteger(10, IntVal))
2133 RegNum = matchRegisterByNumber(IntVal.getZExtValue(),
2134 isMips64() ? Mips::GPR64RegClassID
2135 : Mips::GPR32RegClassID);
2137 // Lookup for the register with the corresponding name.
2139 case MipsOperand::Kind_AFGR64Regs:
2140 case MipsOperand::Kind_FGR64Regs:
2141 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2143 case MipsOperand::Kind_FGR32Regs:
2144 RegNum = matchFPURegisterName(DefSymbol.substr(1));
2146 case MipsOperand::Kind_GPR64:
2147 case MipsOperand::Kind_GPR32:
2149 RegNum = matchCPURegisterName(DefSymbol.substr(1));
2153 RegNum = getReg(regKindToRegClass(Kind), RegNum);
2158 MipsOperand::CreateReg(RegNum, S, Parser.getTok().getLoc());
2159 op->setRegKind(Kind);
2160 Operands.push_back(op);
2164 } else if (Expr->getKind() == MCExpr::Constant) {
2166 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
2168 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc());
2169 Operands.push_back(op);
2176 MipsAsmParser::OperandMatchResultTy
2177 MipsAsmParser::parseHWRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2178 return parseRegs(Operands, (int)MipsOperand::Kind_HWRegs);
2181 MipsAsmParser::OperandMatchResultTy
2182 MipsAsmParser::parseCCRRegs(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2183 return parseRegs(Operands, (int)MipsOperand::Kind_CCRRegs);
2186 MipsAsmParser::OperandMatchResultTy
2187 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2188 const MCExpr *IdVal;
2189 // If the first token is '$' we may have register operand.
2190 if (Parser.getTok().is(AsmToken::Dollar))
2191 return MatchOperand_NoMatch;
2192 SMLoc S = Parser.getTok().getLoc();
2193 if (getParser().parseExpression(IdVal))
2194 return MatchOperand_ParseFail;
2195 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
2196 assert(MCE && "Unexpected MCExpr type.");
2197 int64_t Val = MCE->getValue();
2198 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2199 Operands.push_back(MipsOperand::CreateImm(
2200 MCConstantExpr::Create(0 - Val, getContext()), S, E));
2201 return MatchOperand_Success;
2204 MipsAsmParser::OperandMatchResultTy
2205 MipsAsmParser::parseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2206 switch (getLexer().getKind()) {
2208 return MatchOperand_NoMatch;
2209 case AsmToken::LParen:
2210 case AsmToken::Plus:
2211 case AsmToken::Minus:
2212 case AsmToken::Integer:
2217 SMLoc S = Parser.getTok().getLoc();
2219 if (getParser().parseExpression(Expr))
2220 return MatchOperand_ParseFail;
2223 if (!Expr->EvaluateAsAbsolute(Val)) {
2224 Error(S, "expected immediate value");
2225 return MatchOperand_ParseFail;
2228 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
2229 // and because the CPU always adds one to the immediate field, the allowed
2230 // range becomes 1..4. We'll only check the range here and will deal
2231 // with the addition/subtraction when actually decoding/encoding
2233 if (Val < 1 || Val > 4) {
2234 Error(S, "immediate not in range (1..4)");
2235 return MatchOperand_ParseFail;
2239 MipsOperand::CreateLSAImm(Expr, S, Parser.getTok().getLoc()));
2240 return MatchOperand_Success;
2243 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
2245 MCSymbolRefExpr::VariantKind VK =
2246 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
2247 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
2248 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
2249 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
2250 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
2251 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
2252 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
2253 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
2254 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
2255 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
2256 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
2257 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
2258 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
2259 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
2260 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
2261 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
2262 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
2263 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
2264 .Default(MCSymbolRefExpr::VK_None);
2269 bool MipsAsmParser::ParseInstruction(
2270 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2271 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2272 // Check if we have valid mnemonic
2273 if (!mnemonicIsValid(Name, 0)) {
2274 Parser.eatToEndOfStatement();
2275 return Error(NameLoc, "Unknown instruction");
2277 // First operand in MCInst is instruction mnemonic.
2278 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc));
2280 // Read the remaining operands.
2281 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2282 // Read the first operand.
2283 if (ParseOperand(Operands, Name)) {
2284 SMLoc Loc = getLexer().getLoc();
2285 Parser.eatToEndOfStatement();
2286 return Error(Loc, "unexpected token in argument list");
2289 while (getLexer().is(AsmToken::Comma)) {
2290 Parser.Lex(); // Eat the comma.
2291 // Parse and remember the operand.
2292 if (ParseOperand(Operands, Name)) {
2293 SMLoc Loc = getLexer().getLoc();
2294 Parser.eatToEndOfStatement();
2295 return Error(Loc, "unexpected token in argument list");
2299 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2300 SMLoc Loc = getLexer().getLoc();
2301 Parser.eatToEndOfStatement();
2302 return Error(Loc, "unexpected token in argument list");
2304 Parser.Lex(); // Consume the EndOfStatement.
2308 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2309 SMLoc Loc = getLexer().getLoc();
2310 Parser.eatToEndOfStatement();
2311 return Error(Loc, ErrorMsg);
2314 bool MipsAsmParser::parseSetNoAtDirective() {
2315 // Line should look like: ".set noat".
2317 Options.setATReg(0);
2320 // If this is not the end of the statement, report an error.
2321 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2322 reportParseError("unexpected token in statement");
2325 Parser.Lex(); // Consume the EndOfStatement.
2329 bool MipsAsmParser::parseSetAtDirective() {
2330 // Line can be .set at - defaults to $1
2334 if (getLexer().is(AsmToken::EndOfStatement)) {
2335 Options.setATReg(1);
2336 Parser.Lex(); // Consume the EndOfStatement.
2338 } else if (getLexer().is(AsmToken::Equal)) {
2339 getParser().Lex(); // Eat the '='.
2340 if (getLexer().isNot(AsmToken::Dollar)) {
2341 reportParseError("unexpected token in statement");
2344 Parser.Lex(); // Eat the '$'.
2345 const AsmToken &Reg = Parser.getTok();
2346 if (Reg.is(AsmToken::Identifier)) {
2347 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2348 } else if (Reg.is(AsmToken::Integer)) {
2349 AtRegNo = Reg.getIntVal();
2351 reportParseError("unexpected token in statement");
2355 if (AtRegNo < 0 || AtRegNo > 31) {
2356 reportParseError("unexpected token in statement");
2360 if (!Options.setATReg(AtRegNo)) {
2361 reportParseError("unexpected token in statement");
2364 getParser().Lex(); // Eat the register.
2366 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2367 reportParseError("unexpected token in statement");
2370 Parser.Lex(); // Consume the EndOfStatement.
2373 reportParseError("unexpected token in statement");
2378 bool MipsAsmParser::parseSetReorderDirective() {
2380 // If this is not the end of the statement, report an error.
2381 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2382 reportParseError("unexpected token in statement");
2385 Options.setReorder();
2386 getTargetStreamer().emitDirectiveSetReorder();
2387 Parser.Lex(); // Consume the EndOfStatement.
2391 bool MipsAsmParser::parseSetNoReorderDirective() {
2393 // If this is not the end of the statement, report an error.
2394 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2395 reportParseError("unexpected token in statement");
2398 Options.setNoreorder();
2399 getTargetStreamer().emitDirectiveSetNoReorder();
2400 Parser.Lex(); // Consume the EndOfStatement.
2404 bool MipsAsmParser::parseSetMacroDirective() {
2406 // If this is not the end of the statement, report an error.
2407 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2408 reportParseError("unexpected token in statement");
2412 Parser.Lex(); // Consume the EndOfStatement.
2416 bool MipsAsmParser::parseSetNoMacroDirective() {
2418 // If this is not the end of the statement, report an error.
2419 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2420 reportParseError("`noreorder' must be set before `nomacro'");
2423 if (Options.isReorder()) {
2424 reportParseError("`noreorder' must be set before `nomacro'");
2427 Options.setNomacro();
2428 Parser.Lex(); // Consume the EndOfStatement.
2432 bool MipsAsmParser::parseSetMips16Directive() {
2434 // If this is not the end of the statement, report an error.
2435 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2436 reportParseError("unexpected token in statement");
2439 getTargetStreamer().emitDirectiveSetMips16();
2440 Parser.Lex(); // Consume the EndOfStatement.
2444 bool MipsAsmParser::parseSetNoMips16Directive() {
2446 // If this is not the end of the statement, report an error.
2447 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2448 reportParseError("unexpected token in statement");
2451 // For now do nothing.
2452 Parser.Lex(); // Consume the EndOfStatement.
2456 bool MipsAsmParser::parseSetAssignment() {
2458 const MCExpr *Value;
2460 if (Parser.parseIdentifier(Name))
2461 reportParseError("expected identifier after .set");
2463 if (getLexer().isNot(AsmToken::Comma))
2464 return reportParseError("unexpected token in .set directive");
2467 if (Parser.parseExpression(Value))
2468 return reportParseError("expected valid expression after comma");
2470 // Check if the Name already exists as a symbol.
2471 MCSymbol *Sym = getContext().LookupSymbol(Name);
2473 return reportParseError("symbol already defined");
2474 Sym = getContext().GetOrCreateSymbol(Name);
2475 Sym->setVariableValue(Value);
2480 bool MipsAsmParser::parseDirectiveSet() {
2482 // Get the next token.
2483 const AsmToken &Tok = Parser.getTok();
2485 if (Tok.getString() == "noat") {
2486 return parseSetNoAtDirective();
2487 } else if (Tok.getString() == "at") {
2488 return parseSetAtDirective();
2489 } else if (Tok.getString() == "reorder") {
2490 return parseSetReorderDirective();
2491 } else if (Tok.getString() == "noreorder") {
2492 return parseSetNoReorderDirective();
2493 } else if (Tok.getString() == "macro") {
2494 return parseSetMacroDirective();
2495 } else if (Tok.getString() == "nomacro") {
2496 return parseSetNoMacroDirective();
2497 } else if (Tok.getString() == "mips16") {
2498 return parseSetMips16Directive();
2499 } else if (Tok.getString() == "nomips16") {
2500 return parseSetNoMips16Directive();
2501 } else if (Tok.getString() == "nomicromips") {
2502 getTargetStreamer().emitDirectiveSetNoMicroMips();
2503 Parser.eatToEndOfStatement();
2505 } else if (Tok.getString() == "micromips") {
2506 getTargetStreamer().emitDirectiveSetMicroMips();
2507 Parser.eatToEndOfStatement();
2509 } else if (Tok.getString() == "mips32r2") {
2510 Parser.Lex(); // Eat token.
2511 if (getLexer().isNot(AsmToken::EndOfStatement))
2512 return reportParseError("unexpected token in .set directive");
2513 setFeatureBits(Mips::FeatureMips32r2,"mips32r2");
2514 getTargetStreamer().emitDirectiveSetMips32R2();
2516 } else if (Tok.getString() == "dsp") {
2517 Parser.Lex(); // Eat token.
2518 if (getLexer().isNot(AsmToken::EndOfStatement))
2519 return reportParseError("unexpected token in .set directive");
2520 setFeatureBits(Mips::FeatureDSP, "dsp");
2521 getTargetStreamer().emitDirectiveSetDsp();
2524 // It is just an identifier, look for an assignment.
2525 parseSetAssignment();
2532 /// parseDirectiveWord
2533 /// ::= .word [ expression (, expression)* ]
2534 bool MipsAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2535 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2537 const MCExpr *Value;
2538 if (getParser().parseExpression(Value))
2541 getParser().getStreamer().EmitValue(Value, Size);
2543 if (getLexer().is(AsmToken::EndOfStatement))
2546 // FIXME: Improve diagnostic.
2547 if (getLexer().isNot(AsmToken::Comma))
2548 return Error(L, "unexpected token in directive");
2557 /// parseDirectiveGpWord
2558 /// ::= .gpword local_sym
2559 bool MipsAsmParser::parseDirectiveGpWord() {
2560 const MCExpr *Value;
2561 // EmitGPRel32Value requires an expression, so we are using base class
2562 // method to evaluate the expression.
2563 if (getParser().parseExpression(Value))
2565 getParser().getStreamer().EmitGPRel32Value(Value);
2567 if (getLexer().isNot(AsmToken::EndOfStatement))
2568 return Error(getLexer().getLoc(), "unexpected token in directive");
2569 Parser.Lex(); // Eat EndOfStatement token.
2573 bool MipsAsmParser::parseDirectiveOption() {
2574 // Get the option token.
2575 AsmToken Tok = Parser.getTok();
2576 // At the moment only identifiers are supported.
2577 if (Tok.isNot(AsmToken::Identifier)) {
2578 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2579 Parser.eatToEndOfStatement();
2583 StringRef Option = Tok.getIdentifier();
2585 if (Option == "pic0") {
2586 getTargetStreamer().emitDirectiveOptionPic0();
2588 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2589 Error(Parser.getTok().getLoc(),
2590 "unexpected token in .option pic0 directive");
2591 Parser.eatToEndOfStatement();
2597 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2598 Parser.eatToEndOfStatement();
2602 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2603 StringRef IDVal = DirectiveID.getString();
2605 if (IDVal == ".ent") {
2606 // Ignore this directive for now.
2611 if (IDVal == ".end") {
2612 // Ignore this directive for now.
2617 if (IDVal == ".frame") {
2618 // Ignore this directive for now.
2619 Parser.eatToEndOfStatement();
2623 if (IDVal == ".set") {
2624 return parseDirectiveSet();
2627 if (IDVal == ".fmask") {
2628 // Ignore this directive for now.
2629 Parser.eatToEndOfStatement();
2633 if (IDVal == ".mask") {
2634 // Ignore this directive for now.
2635 Parser.eatToEndOfStatement();
2639 if (IDVal == ".gpword") {
2640 // Ignore this directive for now.
2641 parseDirectiveGpWord();
2645 if (IDVal == ".word") {
2646 parseDirectiveWord(4, DirectiveID.getLoc());
2650 if (IDVal == ".option")
2651 return parseDirectiveOption();
2653 if (IDVal == ".abicalls") {
2654 getTargetStreamer().emitDirectiveAbiCalls();
2655 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2656 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2658 Parser.eatToEndOfStatement();
2666 extern "C" void LLVMInitializeMipsAsmParser() {
2667 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2668 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2669 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2670 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2673 #define GET_REGISTER_MATCHER
2674 #define GET_MATCHER_IMPLEMENTATION
2675 #include "MipsGenAsmMatcher.inc"