1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
32 #define DEBUG_TYPE "mips-asm-parser"
39 class MipsAssemblerOptions {
41 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
43 unsigned getATRegNum() { return aTReg; }
44 bool setATReg(unsigned Reg);
46 bool isReorder() { return reorder; }
47 void setReorder() { reorder = true; }
48 void setNoreorder() { reorder = false; }
50 bool isMacro() { return macro; }
51 void setMacro() { macro = true; }
52 void setNomacro() { macro = false; }
62 class MipsAsmParser : public MCTargetAsmParser {
63 MipsTargetStreamer &getTargetStreamer() {
64 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
65 return static_cast<MipsTargetStreamer &>(TS);
70 MipsAssemblerOptions Options;
72 #define GET_ASSEMBLER_HEADER
73 #include "MipsGenAsmMatcher.inc"
75 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
76 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
77 MCStreamer &Out, unsigned &ErrorInfo,
78 bool MatchingInlineAsm);
80 /// Parse a register as used in CFI directives
81 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
83 bool ParseParenSuffix(StringRef Name,
84 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
86 bool ParseBracketSuffix(StringRef Name,
87 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
89 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
91 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
93 bool ParseDirective(AsmToken DirectiveID);
95 MipsAsmParser::OperandMatchResultTy
96 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
98 MipsAsmParser::OperandMatchResultTy MatchAnyRegisterNameWithoutDollar(
99 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
102 MipsAsmParser::OperandMatchResultTy
103 MatchAnyRegisterWithoutDollar(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
106 MipsAsmParser::OperandMatchResultTy
107 ParseAnyRegister(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
109 MipsAsmParser::OperandMatchResultTy
110 ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
112 MipsAsmParser::OperandMatchResultTy
113 ParseJumpTarget(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
115 MipsAsmParser::OperandMatchResultTy
116 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
118 MipsAsmParser::OperandMatchResultTy
119 ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
121 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
123 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
126 bool needsExpansion(MCInst &Inst);
128 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
129 SmallVectorImpl<MCInst> &Instructions);
130 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
131 SmallVectorImpl<MCInst> &Instructions);
132 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
133 SmallVectorImpl<MCInst> &Instructions);
134 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
135 SmallVectorImpl<MCInst> &Instructions);
136 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
137 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
139 bool reportParseError(StringRef ErrorMsg);
141 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
142 bool parseRelocOperand(const MCExpr *&Res);
144 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
146 bool isEvaluated(const MCExpr *Expr);
147 bool parseSetFeature(uint64_t Feature);
148 bool parseDirectiveCPSetup();
149 bool parseDirectiveNaN();
150 bool parseDirectiveSet();
151 bool parseDirectiveOption();
153 bool parseSetAtDirective();
154 bool parseSetNoAtDirective();
155 bool parseSetMacroDirective();
156 bool parseSetNoMacroDirective();
157 bool parseSetReorderDirective();
158 bool parseSetNoReorderDirective();
159 bool parseSetNoMips16Directive();
161 bool parseSetAssignment();
163 bool parseDataDirective(unsigned Size, SMLoc L);
164 bool parseDirectiveGpWord();
165 bool parseDirectiveGpDWord();
167 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
169 bool isGP64() const {
170 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
173 bool isFP64() const {
174 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
177 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
178 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
180 bool isMicroMips() const {
181 return STI.getFeatureBits() & Mips::FeatureMicroMips;
184 bool parseRegister(unsigned &RegNum);
186 bool eatComma(StringRef ErrorStr);
188 int matchCPURegisterName(StringRef Symbol);
190 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
192 int matchFPURegisterName(StringRef Name);
194 int matchFCCRegisterName(StringRef Name);
196 int matchACRegisterName(StringRef Name);
198 int matchMSA128RegisterName(StringRef Name);
200 int matchMSA128CtrlRegisterName(StringRef Name);
202 unsigned getReg(int RC, int RegNo);
204 unsigned getGPR(int RegNo);
208 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
209 SmallVectorImpl<MCInst> &Instructions);
211 // Helper function that checks if the value of a vector index is within the
212 // boundaries of accepted values for each RegisterKind
213 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
214 bool validateMSAIndex(int Val, int RegKind);
216 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
217 if (!(STI.getFeatureBits() & Feature)) {
218 setAvailableFeatures(ComputeAvailableFeatures(
219 STI.ToggleFeature(FeatureString)));
223 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
224 if (STI.getFeatureBits() & Feature) {
225 setAvailableFeatures(ComputeAvailableFeatures(
226 STI.ToggleFeature(FeatureString)));
231 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
232 const MCInstrInfo &MII)
233 : MCTargetAsmParser(), STI(sti), Parser(parser) {
234 // Initialize the set of available features.
235 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
237 // Assert exactly one ABI was chosen.
238 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
239 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
240 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
241 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
244 MCAsmParser &getParser() const { return Parser; }
245 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
247 /// Warn if RegNo is the current assembler temporary.
248 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
254 /// MipsOperand - Instances of this class represent a parsed Mips machine
256 class MipsOperand : public MCParsedAsmOperand {
258 /// Broad categories of register classes
259 /// The exact class is finalized by the render method.
261 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
262 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
264 RegKind_FCC = 4, /// FCC
265 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
266 RegKind_MSACtrl = 16, /// MSA control registers
267 RegKind_COP2 = 32, /// COP2
268 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
270 RegKind_CCR = 128, /// CCR
271 RegKind_HWRegs = 256, /// HWRegs
273 /// Potentially any (e.g. $1)
274 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
275 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
276 RegKind_CCR | RegKind_HWRegs
281 k_Immediate, /// An immediate (possibly involving symbol references)
282 k_Memory, /// Base + Offset Memory Address
283 k_PhysRegister, /// A physical register from the Mips namespace
284 k_RegisterIndex, /// A register index in one or more RegKind.
285 k_Token /// A simple token
288 MipsOperand(KindTy K, MipsAsmParser &Parser)
289 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
291 /// For diagnostics, and checking the assembler temporary
292 MipsAsmParser &AsmParser;
300 unsigned Num; /// Register Number
304 unsigned Index; /// Index into the register class
305 RegKind Kind; /// Bitfield of the kinds it could possibly be
306 const MCRegisterInfo *RegInfo;
320 struct PhysRegOp PhysReg;
321 struct RegIdxOp RegIdx;
326 SMLoc StartLoc, EndLoc;
328 /// Internal constructor for register kinds
329 static MipsOperand *CreateReg(unsigned Index, RegKind RegKind,
330 const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
331 MipsAsmParser &Parser) {
332 MipsOperand *Op = new MipsOperand(k_RegisterIndex, Parser);
333 Op->RegIdx.Index = Index;
334 Op->RegIdx.RegInfo = RegInfo;
335 Op->RegIdx.Kind = RegKind;
342 /// Coerce the register to GPR32 and return the real register for the current
344 unsigned getGPR32Reg() const {
345 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
346 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
347 unsigned ClassID = Mips::GPR32RegClassID;
348 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
351 /// Coerce the register to GPR64 and return the real register for the current
353 unsigned getGPR64Reg() const {
354 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
355 unsigned ClassID = Mips::GPR64RegClassID;
356 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
360 /// Coerce the register to AFGR64 and return the real register for the current
362 unsigned getAFGR64Reg() const {
363 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
364 if (RegIdx.Index % 2 != 0)
365 AsmParser.Warning(StartLoc, "Float register should be even.");
366 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
367 .getRegister(RegIdx.Index / 2);
370 /// Coerce the register to FGR64 and return the real register for the current
372 unsigned getFGR64Reg() const {
373 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
374 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
375 .getRegister(RegIdx.Index);
378 /// Coerce the register to FGR32 and return the real register for the current
380 unsigned getFGR32Reg() const {
381 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
382 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
383 .getRegister(RegIdx.Index);
386 /// Coerce the register to FGRH32 and return the real register for the current
388 unsigned getFGRH32Reg() const {
389 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
390 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
391 .getRegister(RegIdx.Index);
394 /// Coerce the register to FCC and return the real register for the current
396 unsigned getFCCReg() const {
397 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
398 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
399 .getRegister(RegIdx.Index);
402 /// Coerce the register to MSA128 and return the real register for the current
404 unsigned getMSA128Reg() const {
405 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
406 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
408 unsigned ClassID = Mips::MSA128BRegClassID;
409 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
412 /// Coerce the register to MSACtrl and return the real register for the
414 unsigned getMSACtrlReg() const {
415 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
416 unsigned ClassID = Mips::MSACtrlRegClassID;
417 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
420 /// Coerce the register to COP2 and return the real register for the
422 unsigned getCOP2Reg() const {
423 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
424 unsigned ClassID = Mips::COP2RegClassID;
425 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
428 /// Coerce the register to ACC64DSP and return the real register for the
430 unsigned getACC64DSPReg() const {
431 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
432 unsigned ClassID = Mips::ACC64DSPRegClassID;
433 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
436 /// Coerce the register to HI32DSP and return the real register for the
438 unsigned getHI32DSPReg() const {
439 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
440 unsigned ClassID = Mips::HI32DSPRegClassID;
441 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
444 /// Coerce the register to LO32DSP and return the real register for the
446 unsigned getLO32DSPReg() const {
447 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
448 unsigned ClassID = Mips::LO32DSPRegClassID;
449 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
452 /// Coerce the register to CCR and return the real register for the
454 unsigned getCCRReg() const {
455 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
456 unsigned ClassID = Mips::CCRRegClassID;
457 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
460 /// Coerce the register to HWRegs and return the real register for the
462 unsigned getHWRegsReg() const {
463 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
464 unsigned ClassID = Mips::HWRegsRegClassID;
465 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
469 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
470 // Add as immediate when possible. Null MCExpr = 0.
472 Inst.addOperand(MCOperand::CreateImm(0));
473 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
474 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
476 Inst.addOperand(MCOperand::CreateExpr(Expr));
479 void addRegOperands(MCInst &Inst, unsigned N) const {
480 llvm_unreachable("Use a custom parser instead");
483 /// Render the operand to an MCInst as a GPR32
484 /// Asserts if the wrong number of operands are requested, or the operand
485 /// is not a k_RegisterIndex compatible with RegKind_GPR
486 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
487 assert(N == 1 && "Invalid number of operands!");
488 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
491 /// Render the operand to an MCInst as a GPR64
492 /// Asserts if the wrong number of operands are requested, or the operand
493 /// is not a k_RegisterIndex compatible with RegKind_GPR
494 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
495 assert(N == 1 && "Invalid number of operands!");
496 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
499 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
500 assert(N == 1 && "Invalid number of operands!");
501 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
504 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
505 assert(N == 1 && "Invalid number of operands!");
506 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
509 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
510 assert(N == 1 && "Invalid number of operands!");
511 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
514 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
515 assert(N == 1 && "Invalid number of operands!");
516 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
519 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
520 assert(N == 1 && "Invalid number of operands!");
521 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
524 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
525 assert(N == 1 && "Invalid number of operands!");
526 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
529 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
530 assert(N == 1 && "Invalid number of operands!");
531 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
534 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
535 assert(N == 1 && "Invalid number of operands!");
536 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
539 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
540 assert(N == 1 && "Invalid number of operands!");
541 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
544 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
545 assert(N == 1 && "Invalid number of operands!");
546 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
549 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
550 assert(N == 1 && "Invalid number of operands!");
551 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
554 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
555 assert(N == 1 && "Invalid number of operands!");
556 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
559 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
560 assert(N == 1 && "Invalid number of operands!");
561 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
564 void addImmOperands(MCInst &Inst, unsigned N) const {
565 assert(N == 1 && "Invalid number of operands!");
566 const MCExpr *Expr = getImm();
570 void addMemOperands(MCInst &Inst, unsigned N) const {
571 assert(N == 2 && "Invalid number of operands!");
573 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
575 const MCExpr *Expr = getMemOff();
580 // As a special case until we sort out the definition of div/divu, pretend
581 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
582 if (isGPRAsmReg() && RegIdx.Index == 0)
585 return Kind == k_PhysRegister;
587 bool isRegIdx() const { return Kind == k_RegisterIndex; }
588 bool isImm() const { return Kind == k_Immediate; }
589 bool isConstantImm() const {
590 return isImm() && dyn_cast<MCConstantExpr>(getImm());
592 bool isToken() const {
593 // Note: It's not possible to pretend that other operand kinds are tokens.
594 // The matcher emitter checks tokens first.
595 return Kind == k_Token;
597 bool isMem() const { return Kind == k_Memory; }
598 bool isInvNum() const { return Kind == k_Immediate; }
599 bool isLSAImm() const {
600 if (!isConstantImm())
602 int64_t Val = getConstantImm();
603 return 1 <= Val && Val <= 4;
606 StringRef getToken() const {
607 assert(Kind == k_Token && "Invalid access!");
608 return StringRef(Tok.Data, Tok.Length);
611 unsigned getReg() const {
612 // As a special case until we sort out the definition of div/divu, pretend
613 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
614 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
615 RegIdx.Kind & RegKind_GPR)
616 return getGPR32Reg(); // FIXME: GPR64 too
618 assert(Kind == k_PhysRegister && "Invalid access!");
622 const MCExpr *getImm() const {
623 assert((Kind == k_Immediate) && "Invalid access!");
627 int64_t getConstantImm() const {
628 const MCExpr *Val = getImm();
629 return static_cast<const MCConstantExpr *>(Val)->getValue();
632 MipsOperand *getMemBase() const {
633 assert((Kind == k_Memory) && "Invalid access!");
637 const MCExpr *getMemOff() const {
638 assert((Kind == k_Memory) && "Invalid access!");
642 static MipsOperand *CreateToken(StringRef Str, SMLoc S,
643 MipsAsmParser &Parser) {
644 MipsOperand *Op = new MipsOperand(k_Token, Parser);
645 Op->Tok.Data = Str.data();
646 Op->Tok.Length = Str.size();
652 /// Create a numeric register (e.g. $1). The exact register remains
653 /// unresolved until an instruction successfully matches
654 static MipsOperand *CreateNumericReg(unsigned Index,
655 const MCRegisterInfo *RegInfo, SMLoc S,
656 SMLoc E, MipsAsmParser &Parser) {
657 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
658 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
661 /// Create a register that is definitely a GPR.
662 /// This is typically only used for named registers such as $gp.
663 static MipsOperand *CreateGPRReg(unsigned Index,
664 const MCRegisterInfo *RegInfo, SMLoc S,
665 SMLoc E, MipsAsmParser &Parser) {
666 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
669 /// Create a register that is definitely a FGR.
670 /// This is typically only used for named registers such as $f0.
671 static MipsOperand *CreateFGRReg(unsigned Index,
672 const MCRegisterInfo *RegInfo, SMLoc S,
673 SMLoc E, MipsAsmParser &Parser) {
674 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
677 /// Create a register that is definitely an FCC.
678 /// This is typically only used for named registers such as $fcc0.
679 static MipsOperand *CreateFCCReg(unsigned Index,
680 const MCRegisterInfo *RegInfo, SMLoc S,
681 SMLoc E, MipsAsmParser &Parser) {
682 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
685 /// Create a register that is definitely an ACC.
686 /// This is typically only used for named registers such as $ac0.
687 static MipsOperand *CreateACCReg(unsigned Index,
688 const MCRegisterInfo *RegInfo, SMLoc S,
689 SMLoc E, MipsAsmParser &Parser) {
690 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
693 /// Create a register that is definitely an MSA128.
694 /// This is typically only used for named registers such as $w0.
695 static MipsOperand *CreateMSA128Reg(unsigned Index,
696 const MCRegisterInfo *RegInfo, SMLoc S,
697 SMLoc E, MipsAsmParser &Parser) {
698 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
701 /// Create a register that is definitely an MSACtrl.
702 /// This is typically only used for named registers such as $msaaccess.
703 static MipsOperand *CreateMSACtrlReg(unsigned Index,
704 const MCRegisterInfo *RegInfo, SMLoc S,
705 SMLoc E, MipsAsmParser &Parser) {
706 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
709 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
710 MipsAsmParser &Parser) {
711 MipsOperand *Op = new MipsOperand(k_Immediate, Parser);
718 static MipsOperand *CreateMem(MipsOperand *Base, const MCExpr *Off, SMLoc S,
719 SMLoc E, MipsAsmParser &Parser) {
720 MipsOperand *Op = new MipsOperand(k_Memory, Parser);
728 bool isGPRAsmReg() const {
729 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
731 bool isFGRAsmReg() const {
732 // AFGR64 is $0-$15 but we handle this in getAFGR64()
733 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
735 bool isHWRegsAsmReg() const {
736 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
738 bool isCCRAsmReg() const {
739 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
741 bool isFCCAsmReg() const {
742 return isRegIdx() && RegIdx.Kind & RegKind_FCC && RegIdx.Index <= 7;
744 bool isACCAsmReg() const {
745 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
747 bool isCOP2AsmReg() const {
748 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
750 bool isMSA128AsmReg() const {
751 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
753 bool isMSACtrlAsmReg() const {
754 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
757 /// getStartLoc - Get the location of the first token of this operand.
758 SMLoc getStartLoc() const { return StartLoc; }
759 /// getEndLoc - Get the location of the last token of this operand.
760 SMLoc getEndLoc() const { return EndLoc; }
762 virtual ~MipsOperand() {
770 case k_RegisterIndex:
776 virtual void print(raw_ostream &OS) const {
791 OS << "PhysReg<" << PhysReg.Num << ">";
793 case k_RegisterIndex:
794 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
801 }; // class MipsOperand
805 extern const MCInstrDesc MipsInsts[];
807 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
808 return MipsInsts[Opcode];
811 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
812 SmallVectorImpl<MCInst> &Instructions) {
813 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
817 if (MCID.isBranch() || MCID.isCall()) {
818 const unsigned Opcode = Inst.getOpcode();
828 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
829 Offset = Inst.getOperand(2);
831 break; // We'll deal with this situation later on when applying fixups.
832 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
833 return Error(IDLoc, "branch target out of range");
834 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
835 return Error(IDLoc, "branch to misaligned address");
849 case Mips::BGEZAL_MM:
850 case Mips::BLTZAL_MM:
853 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
854 Offset = Inst.getOperand(1);
856 break; // We'll deal with this situation later on when applying fixups.
857 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
858 return Error(IDLoc, "branch target out of range");
859 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
860 return Error(IDLoc, "branch to misaligned address");
865 if (MCID.hasDelaySlot() && Options.isReorder()) {
866 // If this instruction has a delay slot and .set reorder is active,
867 // emit a NOP after it.
868 Instructions.push_back(Inst);
870 NopInst.setOpcode(Mips::SLL);
871 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
872 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
873 NopInst.addOperand(MCOperand::CreateImm(0));
874 Instructions.push_back(NopInst);
878 if (MCID.mayLoad() || MCID.mayStore()) {
879 // Check the offset of memory operand, if it is a symbol
880 // reference or immediate we may have to expand instructions.
881 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
882 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
883 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
884 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
885 MCOperand &Op = Inst.getOperand(i);
887 int MemOffset = Op.getImm();
888 if (MemOffset < -32768 || MemOffset > 32767) {
889 // Offset can't exceed 16bit value.
890 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
893 } else if (Op.isExpr()) {
894 const MCExpr *Expr = Op.getExpr();
895 if (Expr->getKind() == MCExpr::SymbolRef) {
896 const MCSymbolRefExpr *SR =
897 static_cast<const MCSymbolRefExpr *>(Expr);
898 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
900 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
903 } else if (!isEvaluated(Expr)) {
904 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
912 if (needsExpansion(Inst))
913 expandInstruction(Inst, IDLoc, Instructions);
915 Instructions.push_back(Inst);
920 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
922 switch (Inst.getOpcode()) {
923 case Mips::LoadImm32Reg:
924 case Mips::LoadAddr32Imm:
925 case Mips::LoadAddr32Reg:
932 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
933 SmallVectorImpl<MCInst> &Instructions) {
934 switch (Inst.getOpcode()) {
935 case Mips::LoadImm32Reg:
936 return expandLoadImm(Inst, IDLoc, Instructions);
937 case Mips::LoadAddr32Imm:
938 return expandLoadAddressImm(Inst, IDLoc, Instructions);
939 case Mips::LoadAddr32Reg:
940 return expandLoadAddressReg(Inst, IDLoc, Instructions);
944 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
945 SmallVectorImpl<MCInst> &Instructions) {
947 const MCOperand &ImmOp = Inst.getOperand(1);
948 assert(ImmOp.isImm() && "expected immediate operand kind");
949 const MCOperand &RegOp = Inst.getOperand(0);
950 assert(RegOp.isReg() && "expected register operand kind");
952 int ImmValue = ImmOp.getImm();
953 tmpInst.setLoc(IDLoc);
954 if (0 <= ImmValue && ImmValue <= 65535) {
955 // For 0 <= j <= 65535.
956 // li d,j => ori d,$zero,j
957 tmpInst.setOpcode(Mips::ORi);
958 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
959 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
960 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
961 Instructions.push_back(tmpInst);
962 } else if (ImmValue < 0 && ImmValue >= -32768) {
963 // For -32768 <= j < 0.
964 // li d,j => addiu d,$zero,j
965 tmpInst.setOpcode(Mips::ADDiu);
966 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
967 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
968 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
969 Instructions.push_back(tmpInst);
971 // For any other value of j that is representable as a 32-bit integer.
972 // li d,j => lui d,hi16(j)
974 tmpInst.setOpcode(Mips::LUi);
975 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
976 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
977 Instructions.push_back(tmpInst);
979 tmpInst.setOpcode(Mips::ORi);
980 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
981 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
982 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
983 tmpInst.setLoc(IDLoc);
984 Instructions.push_back(tmpInst);
989 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
990 SmallVectorImpl<MCInst> &Instructions) {
992 const MCOperand &ImmOp = Inst.getOperand(2);
993 assert(ImmOp.isImm() && "expected immediate operand kind");
994 const MCOperand &SrcRegOp = Inst.getOperand(1);
995 assert(SrcRegOp.isReg() && "expected register operand kind");
996 const MCOperand &DstRegOp = Inst.getOperand(0);
997 assert(DstRegOp.isReg() && "expected register operand kind");
998 int ImmValue = ImmOp.getImm();
999 if (-32768 <= ImmValue && ImmValue <= 65535) {
1000 // For -32768 <= j <= 65535.
1001 // la d,j(s) => addiu d,s,j
1002 tmpInst.setOpcode(Mips::ADDiu);
1003 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1004 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1005 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1006 Instructions.push_back(tmpInst);
1008 // For any other value of j that is representable as a 32-bit integer.
1009 // la d,j(s) => lui d,hi16(j)
1012 tmpInst.setOpcode(Mips::LUi);
1013 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1014 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1015 Instructions.push_back(tmpInst);
1017 tmpInst.setOpcode(Mips::ORi);
1018 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1019 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1020 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1021 Instructions.push_back(tmpInst);
1023 tmpInst.setOpcode(Mips::ADDu);
1024 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1025 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1026 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1027 Instructions.push_back(tmpInst);
1032 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1033 SmallVectorImpl<MCInst> &Instructions) {
1035 const MCOperand &ImmOp = Inst.getOperand(1);
1036 assert(ImmOp.isImm() && "expected immediate operand kind");
1037 const MCOperand &RegOp = Inst.getOperand(0);
1038 assert(RegOp.isReg() && "expected register operand kind");
1039 int ImmValue = ImmOp.getImm();
1040 if (-32768 <= ImmValue && ImmValue <= 65535) {
1041 // For -32768 <= j <= 65535.
1042 // la d,j => addiu d,$zero,j
1043 tmpInst.setOpcode(Mips::ADDiu);
1044 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1045 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1046 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1047 Instructions.push_back(tmpInst);
1049 // For any other value of j that is representable as a 32-bit integer.
1050 // la d,j => lui d,hi16(j)
1052 tmpInst.setOpcode(Mips::LUi);
1053 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1054 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1055 Instructions.push_back(tmpInst);
1057 tmpInst.setOpcode(Mips::ORi);
1058 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1059 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1060 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1061 Instructions.push_back(tmpInst);
1065 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1066 SmallVectorImpl<MCInst> &Instructions,
1067 bool isLoad, bool isImmOpnd) {
1068 const MCSymbolRefExpr *SR;
1070 unsigned ImmOffset, HiOffset, LoOffset;
1071 const MCExpr *ExprOffset;
1073 unsigned AtRegNum = getReg(
1074 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
1075 // 1st operand is either the source or destination register.
1076 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1077 unsigned RegOpNum = Inst.getOperand(0).getReg();
1078 // 2nd operand is the base register.
1079 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1080 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1081 // 3rd operand is either an immediate or expression.
1083 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1084 ImmOffset = Inst.getOperand(2).getImm();
1085 LoOffset = ImmOffset & 0x0000ffff;
1086 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1087 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1088 if (LoOffset & 0x8000)
1091 ExprOffset = Inst.getOperand(2).getExpr();
1092 // All instructions will have the same location.
1093 TempInst.setLoc(IDLoc);
1094 // 1st instruction in expansion is LUi. For load instruction we can use
1095 // the dst register as a temporary if base and dst are different,
1096 // but for stores we must use $at.
1097 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
1098 TempInst.setOpcode(Mips::LUi);
1099 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1101 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1103 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1104 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1105 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1106 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1108 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1110 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1111 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1114 // Add the instruction to the list.
1115 Instructions.push_back(TempInst);
1116 // Prepare TempInst for next instruction.
1118 // Add temp register to base.
1119 TempInst.setOpcode(Mips::ADDu);
1120 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1121 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1122 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1123 Instructions.push_back(TempInst);
1125 // And finally, create original instruction with low part
1126 // of offset and new base.
1127 TempInst.setOpcode(Inst.getOpcode());
1128 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1129 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1131 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1133 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1134 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1135 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1137 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1139 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1140 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1143 Instructions.push_back(TempInst);
1147 bool MipsAsmParser::MatchAndEmitInstruction(
1148 SMLoc IDLoc, unsigned &Opcode,
1149 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
1150 unsigned &ErrorInfo, bool MatchingInlineAsm) {
1152 SmallVector<MCInst, 8> Instructions;
1153 unsigned MatchResult =
1154 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1156 switch (MatchResult) {
1159 case Match_Success: {
1160 if (processInstruction(Inst, IDLoc, Instructions))
1162 for (unsigned i = 0; i < Instructions.size(); i++)
1163 Out.EmitInstruction(Instructions[i], STI);
1166 case Match_MissingFeature:
1167 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1169 case Match_InvalidOperand: {
1170 SMLoc ErrorLoc = IDLoc;
1171 if (ErrorInfo != ~0U) {
1172 if (ErrorInfo >= Operands.size())
1173 return Error(IDLoc, "too few operands for instruction");
1175 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
1176 if (ErrorLoc == SMLoc())
1180 return Error(ErrorLoc, "invalid operand for instruction");
1182 case Match_MnemonicFail:
1183 return Error(IDLoc, "invalid instruction");
1188 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1189 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1191 Warning(Loc, "Used $at without \".set noat\"");
1193 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1194 Twine(RegIndex) + "\"");
1198 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1201 CC = StringSwitch<unsigned>(Name)
1237 if (isN32() || isN64()) {
1238 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1239 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1240 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1241 if (8 <= CC && CC <= 11)
1245 CC = StringSwitch<unsigned>(Name)
1258 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1260 if (Name[0] == 'f') {
1261 StringRef NumString = Name.substr(1);
1263 if (NumString.getAsInteger(10, IntVal))
1264 return -1; // This is not an integer.
1265 if (IntVal > 31) // Maximum index for fpu register.
1272 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1274 if (Name.startswith("fcc")) {
1275 StringRef NumString = Name.substr(3);
1277 if (NumString.getAsInteger(10, IntVal))
1278 return -1; // This is not an integer.
1279 if (IntVal > 7) // There are only 8 fcc registers.
1286 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1288 if (Name.startswith("ac")) {
1289 StringRef NumString = Name.substr(2);
1291 if (NumString.getAsInteger(10, IntVal))
1292 return -1; // This is not an integer.
1293 if (IntVal > 3) // There are only 3 acc registers.
1300 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1303 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1312 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1315 CC = StringSwitch<unsigned>(Name)
1318 .Case("msaaccess", 2)
1320 .Case("msamodify", 4)
1321 .Case("msarequest", 5)
1323 .Case("msaunmap", 7)
1329 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1337 int MipsAsmParser::getATReg() {
1338 int AT = Options.getATRegNum();
1340 TokError("Pseudo instruction requires $at, which is not available");
1344 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1345 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1348 unsigned MipsAsmParser::getGPR(int RegNo) {
1349 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1353 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1355 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1358 return getReg(RegClass, RegNum);
1362 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1363 StringRef Mnemonic) {
1364 DEBUG(dbgs() << "ParseOperand\n");
1366 // Check if the current operand has a custom associated parser, if so, try to
1367 // custom parse the operand, or fallback to the general approach.
1368 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1369 if (ResTy == MatchOperand_Success)
1371 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1372 // there was a match, but an error occurred, in which case, just return that
1373 // the operand parsing failed.
1374 if (ResTy == MatchOperand_ParseFail)
1377 DEBUG(dbgs() << ".. Generic Parser\n");
1379 switch (getLexer().getKind()) {
1381 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1383 case AsmToken::Dollar: {
1384 // Parse the register.
1385 SMLoc S = Parser.getTok().getLoc();
1387 // Almost all registers have been parsed by custom parsers. There is only
1388 // one exception to this. $zero (and it's alias $0) will reach this point
1389 // for div, divu, and similar instructions because it is not an operand
1390 // to the instruction definition but an explicit register. Special case
1391 // this situation for now.
1392 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1395 // Maybe it is a symbol reference.
1396 StringRef Identifier;
1397 if (Parser.parseIdentifier(Identifier))
1400 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1401 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1402 // Otherwise create a symbol reference.
1404 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1406 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1409 // Else drop to expression parsing.
1410 case AsmToken::LParen:
1411 case AsmToken::Minus:
1412 case AsmToken::Plus:
1413 case AsmToken::Integer:
1414 case AsmToken::String: {
1415 DEBUG(dbgs() << ".. generic integer\n");
1416 OperandMatchResultTy ResTy = ParseImm(Operands);
1417 return ResTy != MatchOperand_Success;
1419 case AsmToken::Percent: {
1420 // It is a symbol reference or constant expression.
1421 const MCExpr *IdVal;
1422 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1423 if (parseRelocOperand(IdVal))
1426 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1428 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1430 } // case AsmToken::Percent
1431 } // switch(getLexer().getKind())
1435 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1436 StringRef RelocStr) {
1438 // Check the type of the expression.
1439 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1440 // It's a constant, evaluate reloc value.
1442 switch (getVariantKind(RelocStr)) {
1443 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1444 // Get the 1st 16-bits.
1445 Val = MCE->getValue() & 0xffff;
1447 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1448 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1449 // 16 bits being negative.
1450 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1452 case MCSymbolRefExpr::VK_Mips_HIGHER:
1453 // Get the 3rd 16-bits.
1454 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1456 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1457 // Get the 4th 16-bits.
1458 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1461 report_fatal_error("Unsupported reloc value!");
1463 return MCConstantExpr::Create(Val, getContext());
1466 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1467 // It's a symbol, create a symbolic expression from the symbol.
1468 StringRef Symbol = MSRE->getSymbol().getName();
1469 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1470 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1474 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1475 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1477 // Try to create target expression.
1478 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1479 return MipsMCExpr::Create(VK, Expr, getContext());
1481 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1482 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1483 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1487 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1488 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1489 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1492 // Just return the original expression.
1496 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1498 switch (Expr->getKind()) {
1499 case MCExpr::Constant:
1501 case MCExpr::SymbolRef:
1502 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1503 case MCExpr::Binary:
1504 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1505 if (!isEvaluated(BE->getLHS()))
1507 return isEvaluated(BE->getRHS());
1510 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1511 case MCExpr::Target:
1517 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1518 Parser.Lex(); // Eat the % token.
1519 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1520 if (Tok.isNot(AsmToken::Identifier))
1523 std::string Str = Tok.getIdentifier().str();
1525 Parser.Lex(); // Eat the identifier.
1526 // Now make an expression from the rest of the operand.
1527 const MCExpr *IdVal;
1530 if (getLexer().getKind() == AsmToken::LParen) {
1532 Parser.Lex(); // Eat the '(' token.
1533 if (getLexer().getKind() == AsmToken::Percent) {
1534 Parser.Lex(); // Eat the % token.
1535 const AsmToken &nextTok = Parser.getTok();
1536 if (nextTok.isNot(AsmToken::Identifier))
1539 Str += nextTok.getIdentifier();
1540 Parser.Lex(); // Eat the identifier.
1541 if (getLexer().getKind() != AsmToken::LParen)
1546 if (getParser().parseParenExpression(IdVal, EndLoc))
1549 while (getLexer().getKind() == AsmToken::RParen)
1550 Parser.Lex(); // Eat the ')' token.
1553 return true; // Parenthesis must follow the relocation operand.
1555 Res = evaluateRelocExpr(IdVal, Str);
1559 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1561 SmallVector<MCParsedAsmOperand *, 1> Operands;
1562 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1563 if (ResTy == MatchOperand_Success) {
1564 assert(Operands.size() == 1);
1565 MipsOperand &Operand = *static_cast<MipsOperand *>(Operands.front());
1566 StartLoc = Operand.getStartLoc();
1567 EndLoc = Operand.getEndLoc();
1569 // AFAIK, we only support numeric registers and named GPR's in CFI
1571 // Don't worry about eating tokens before failing. Using an unrecognised
1572 // register is a parse error.
1573 if (Operand.isGPRAsmReg()) {
1574 // Resolve to GPR32 or GPR64 appropriately.
1575 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1580 return (RegNo == (unsigned)-1);
1583 assert(Operands.size() == 0);
1584 return (RegNo == (unsigned)-1);
1587 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1591 while (getLexer().getKind() == AsmToken::LParen)
1594 switch (getLexer().getKind()) {
1597 case AsmToken::Identifier:
1598 case AsmToken::LParen:
1599 case AsmToken::Integer:
1600 case AsmToken::Minus:
1601 case AsmToken::Plus:
1603 Result = getParser().parseParenExpression(Res, S);
1605 Result = (getParser().parseExpression(Res));
1606 while (getLexer().getKind() == AsmToken::RParen)
1609 case AsmToken::Percent:
1610 Result = parseRelocOperand(Res);
1615 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1616 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1617 DEBUG(dbgs() << "parseMemOperand\n");
1618 const MCExpr *IdVal = 0;
1620 bool isParenExpr = false;
1621 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1622 // First operand is the offset.
1623 S = Parser.getTok().getLoc();
1625 if (getLexer().getKind() == AsmToken::LParen) {
1630 if (getLexer().getKind() != AsmToken::Dollar) {
1631 if (parseMemOffset(IdVal, isParenExpr))
1632 return MatchOperand_ParseFail;
1634 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1635 if (Tok.isNot(AsmToken::LParen)) {
1636 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1637 if (Mnemonic->getToken() == "la") {
1639 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1640 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1641 return MatchOperand_Success;
1643 if (Tok.is(AsmToken::EndOfStatement)) {
1645 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1647 // Zero register assumed, add a memory operand with ZERO as its base.
1648 // "Base" will be managed by k_Memory.
1649 MipsOperand *Base = MipsOperand::CreateGPRReg(
1650 0, getContext().getRegisterInfo(), S, E, *this);
1651 Operands.push_back(MipsOperand::CreateMem(Base, IdVal, S, E, *this));
1652 return MatchOperand_Success;
1654 Error(Parser.getTok().getLoc(), "'(' expected");
1655 return MatchOperand_ParseFail;
1658 Parser.Lex(); // Eat the '(' token.
1661 Res = ParseAnyRegister(Operands);
1662 if (Res != MatchOperand_Success)
1665 if (Parser.getTok().isNot(AsmToken::RParen)) {
1666 Error(Parser.getTok().getLoc(), "')' expected");
1667 return MatchOperand_ParseFail;
1670 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1672 Parser.Lex(); // Eat the ')' token.
1675 IdVal = MCConstantExpr::Create(0, getContext());
1677 // Replace the register operand with the memory operand.
1678 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1679 // Remove the register from the operands.
1680 // "op" will be managed by k_Memory.
1681 Operands.pop_back();
1682 // Add the memory operand.
1683 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1685 if (IdVal->EvaluateAsAbsolute(Imm))
1686 IdVal = MCConstantExpr::Create(Imm, getContext());
1687 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1688 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1692 Operands.push_back(MipsOperand::CreateMem(op, IdVal, S, E, *this));
1693 return MatchOperand_Success;
1696 bool MipsAsmParser::searchSymbolAlias(
1697 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1699 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1701 SMLoc S = Parser.getTok().getLoc();
1703 if (Sym->isVariable())
1704 Expr = Sym->getVariableValue();
1707 if (Expr->getKind() == MCExpr::SymbolRef) {
1708 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1709 const StringRef DefSymbol = Ref->getSymbol().getName();
1710 if (DefSymbol.startswith("$")) {
1711 OperandMatchResultTy ResTy =
1712 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1713 if (ResTy == MatchOperand_Success) {
1716 } else if (ResTy == MatchOperand_ParseFail)
1717 llvm_unreachable("Should never ParseFail");
1720 } else if (Expr->getKind() == MCExpr::Constant) {
1722 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1724 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this);
1725 Operands.push_back(op);
1732 MipsAsmParser::OperandMatchResultTy
1733 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(
1734 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
1736 int Index = matchCPURegisterName(Identifier);
1738 Operands.push_back(MipsOperand::CreateGPRReg(
1739 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1740 return MatchOperand_Success;
1743 Index = matchFPURegisterName(Identifier);
1745 Operands.push_back(MipsOperand::CreateFGRReg(
1746 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1747 return MatchOperand_Success;
1750 Index = matchFCCRegisterName(Identifier);
1752 Operands.push_back(MipsOperand::CreateFCCReg(
1753 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1754 return MatchOperand_Success;
1757 Index = matchACRegisterName(Identifier);
1759 Operands.push_back(MipsOperand::CreateACCReg(
1760 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1761 return MatchOperand_Success;
1764 Index = matchMSA128RegisterName(Identifier);
1766 Operands.push_back(MipsOperand::CreateMSA128Reg(
1767 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1768 return MatchOperand_Success;
1771 Index = matchMSA128CtrlRegisterName(Identifier);
1773 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1774 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1775 return MatchOperand_Success;
1778 return MatchOperand_NoMatch;
1781 MipsAsmParser::OperandMatchResultTy
1782 MipsAsmParser::MatchAnyRegisterWithoutDollar(
1783 SmallVectorImpl<MCParsedAsmOperand *> &Operands, SMLoc S) {
1784 auto Token = Parser.getLexer().peekTok(false);
1786 if (Token.is(AsmToken::Identifier)) {
1787 DEBUG(dbgs() << ".. identifier\n");
1788 StringRef Identifier = Token.getIdentifier();
1789 OperandMatchResultTy ResTy =
1790 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1792 } else if (Token.is(AsmToken::Integer)) {
1793 DEBUG(dbgs() << ".. integer\n");
1794 Operands.push_back(MipsOperand::CreateNumericReg(
1795 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1797 return MatchOperand_Success;
1800 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1802 return MatchOperand_NoMatch;
1805 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseAnyRegister(
1806 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1807 DEBUG(dbgs() << "ParseAnyRegister\n");
1809 auto Token = Parser.getTok();
1811 SMLoc S = Token.getLoc();
1813 if (Token.isNot(AsmToken::Dollar)) {
1814 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
1815 if (Token.is(AsmToken::Identifier)) {
1816 if (searchSymbolAlias(Operands))
1817 return MatchOperand_Success;
1819 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
1820 return MatchOperand_NoMatch;
1822 DEBUG(dbgs() << ".. $\n");
1824 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
1825 if (ResTy == MatchOperand_Success) {
1827 Parser.Lex(); // identifier
1832 MipsAsmParser::OperandMatchResultTy
1833 MipsAsmParser::ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1834 switch (getLexer().getKind()) {
1836 return MatchOperand_NoMatch;
1837 case AsmToken::LParen:
1838 case AsmToken::Minus:
1839 case AsmToken::Plus:
1840 case AsmToken::Integer:
1841 case AsmToken::String:
1845 const MCExpr *IdVal;
1846 SMLoc S = Parser.getTok().getLoc();
1847 if (getParser().parseExpression(IdVal))
1848 return MatchOperand_ParseFail;
1850 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1851 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1852 return MatchOperand_Success;
1855 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseJumpTarget(
1856 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1857 DEBUG(dbgs() << "ParseJumpTarget\n");
1859 SMLoc S = getLexer().getLoc();
1861 // Integers and expressions are acceptable
1862 OperandMatchResultTy ResTy = ParseImm(Operands);
1863 if (ResTy != MatchOperand_NoMatch)
1866 // Registers are a valid target and have priority over symbols.
1867 ResTy = ParseAnyRegister(Operands);
1868 if (ResTy != MatchOperand_NoMatch)
1871 const MCExpr *Expr = nullptr;
1872 if (Parser.parseExpression(Expr)) {
1873 // We have no way of knowing if a symbol was consumed so we must ParseFail
1874 return MatchOperand_ParseFail;
1877 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
1878 return MatchOperand_Success;
1881 MipsAsmParser::OperandMatchResultTy
1882 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1883 const MCExpr *IdVal;
1884 // If the first token is '$' we may have register operand.
1885 if (Parser.getTok().is(AsmToken::Dollar))
1886 return MatchOperand_NoMatch;
1887 SMLoc S = Parser.getTok().getLoc();
1888 if (getParser().parseExpression(IdVal))
1889 return MatchOperand_ParseFail;
1890 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1891 assert(MCE && "Unexpected MCExpr type.");
1892 int64_t Val = MCE->getValue();
1893 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1894 Operands.push_back(MipsOperand::CreateImm(
1895 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
1896 return MatchOperand_Success;
1899 MipsAsmParser::OperandMatchResultTy
1900 MipsAsmParser::ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1901 switch (getLexer().getKind()) {
1903 return MatchOperand_NoMatch;
1904 case AsmToken::LParen:
1905 case AsmToken::Plus:
1906 case AsmToken::Minus:
1907 case AsmToken::Integer:
1912 SMLoc S = Parser.getTok().getLoc();
1914 if (getParser().parseExpression(Expr))
1915 return MatchOperand_ParseFail;
1918 if (!Expr->EvaluateAsAbsolute(Val)) {
1919 Error(S, "expected immediate value");
1920 return MatchOperand_ParseFail;
1923 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
1924 // and because the CPU always adds one to the immediate field, the allowed
1925 // range becomes 1..4. We'll only check the range here and will deal
1926 // with the addition/subtraction when actually decoding/encoding
1928 if (Val < 1 || Val > 4) {
1929 Error(S, "immediate not in range (1..4)");
1930 return MatchOperand_ParseFail;
1934 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
1935 return MatchOperand_Success;
1938 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1940 MCSymbolRefExpr::VariantKind VK =
1941 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1942 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1943 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1944 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1945 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1946 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1947 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1948 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1949 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1950 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1951 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1952 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1953 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1954 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1955 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1956 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1957 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1958 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1959 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
1960 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
1961 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
1962 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
1963 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
1964 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
1965 .Default(MCSymbolRefExpr::VK_None);
1967 assert (VK != MCSymbolRefExpr::VK_None);
1972 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
1974 /// ::= '(', register, ')'
1975 /// handle it before we iterate so we don't get tripped up by the lack of
1977 bool MipsAsmParser::ParseParenSuffix(
1978 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1979 if (getLexer().is(AsmToken::LParen)) {
1981 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
1983 if (ParseOperand(Operands, Name)) {
1984 SMLoc Loc = getLexer().getLoc();
1985 Parser.eatToEndOfStatement();
1986 return Error(Loc, "unexpected token in argument list");
1988 if (Parser.getTok().isNot(AsmToken::RParen)) {
1989 SMLoc Loc = getLexer().getLoc();
1990 Parser.eatToEndOfStatement();
1991 return Error(Loc, "unexpected token, expected ')'");
1994 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2000 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2001 /// either one of these.
2002 /// ::= '[', register, ']'
2003 /// ::= '[', integer, ']'
2004 /// handle it before we iterate so we don't get tripped up by the lack of
2006 bool MipsAsmParser::ParseBracketSuffix(
2007 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2008 if (getLexer().is(AsmToken::LBrac)) {
2010 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2012 if (ParseOperand(Operands, Name)) {
2013 SMLoc Loc = getLexer().getLoc();
2014 Parser.eatToEndOfStatement();
2015 return Error(Loc, "unexpected token in argument list");
2017 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2018 SMLoc Loc = getLexer().getLoc();
2019 Parser.eatToEndOfStatement();
2020 return Error(Loc, "unexpected token, expected ']'");
2023 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2029 bool MipsAsmParser::ParseInstruction(
2030 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2031 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2032 DEBUG(dbgs() << "ParseInstruction\n");
2033 // Check if we have valid mnemonic
2034 if (!mnemonicIsValid(Name, 0)) {
2035 Parser.eatToEndOfStatement();
2036 return Error(NameLoc, "Unknown instruction");
2038 // First operand in MCInst is instruction mnemonic.
2039 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2041 // Read the remaining operands.
2042 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2043 // Read the first operand.
2044 if (ParseOperand(Operands, Name)) {
2045 SMLoc Loc = getLexer().getLoc();
2046 Parser.eatToEndOfStatement();
2047 return Error(Loc, "unexpected token in argument list");
2049 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2051 // AFAIK, parenthesis suffixes are never on the first operand
2053 while (getLexer().is(AsmToken::Comma)) {
2054 Parser.Lex(); // Eat the comma.
2055 // Parse and remember the operand.
2056 if (ParseOperand(Operands, Name)) {
2057 SMLoc Loc = getLexer().getLoc();
2058 Parser.eatToEndOfStatement();
2059 return Error(Loc, "unexpected token in argument list");
2061 // Parse bracket and parenthesis suffixes before we iterate
2062 if (getLexer().is(AsmToken::LBrac)) {
2063 if (ParseBracketSuffix(Name, Operands))
2065 } else if (getLexer().is(AsmToken::LParen) &&
2066 ParseParenSuffix(Name, Operands))
2070 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2071 SMLoc Loc = getLexer().getLoc();
2072 Parser.eatToEndOfStatement();
2073 return Error(Loc, "unexpected token in argument list");
2075 Parser.Lex(); // Consume the EndOfStatement.
2079 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2080 SMLoc Loc = getLexer().getLoc();
2081 Parser.eatToEndOfStatement();
2082 return Error(Loc, ErrorMsg);
2085 bool MipsAsmParser::parseSetNoAtDirective() {
2086 // Line should look like: ".set noat".
2088 Options.setATReg(0);
2091 // If this is not the end of the statement, report an error.
2092 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2093 reportParseError("unexpected token in statement");
2096 Parser.Lex(); // Consume the EndOfStatement.
2100 bool MipsAsmParser::parseSetAtDirective() {
2101 // Line can be .set at - defaults to $1
2105 if (getLexer().is(AsmToken::EndOfStatement)) {
2106 Options.setATReg(1);
2107 Parser.Lex(); // Consume the EndOfStatement.
2109 } else if (getLexer().is(AsmToken::Equal)) {
2110 getParser().Lex(); // Eat the '='.
2111 if (getLexer().isNot(AsmToken::Dollar)) {
2112 reportParseError("unexpected token in statement");
2115 Parser.Lex(); // Eat the '$'.
2116 const AsmToken &Reg = Parser.getTok();
2117 if (Reg.is(AsmToken::Identifier)) {
2118 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2119 } else if (Reg.is(AsmToken::Integer)) {
2120 AtRegNo = Reg.getIntVal();
2122 reportParseError("unexpected token in statement");
2126 if (AtRegNo < 0 || AtRegNo > 31) {
2127 reportParseError("unexpected token in statement");
2131 if (!Options.setATReg(AtRegNo)) {
2132 reportParseError("unexpected token in statement");
2135 getParser().Lex(); // Eat the register.
2137 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2138 reportParseError("unexpected token in statement");
2141 Parser.Lex(); // Consume the EndOfStatement.
2144 reportParseError("unexpected token in statement");
2149 bool MipsAsmParser::parseSetReorderDirective() {
2151 // If this is not the end of the statement, report an error.
2152 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2153 reportParseError("unexpected token in statement");
2156 Options.setReorder();
2157 getTargetStreamer().emitDirectiveSetReorder();
2158 Parser.Lex(); // Consume the EndOfStatement.
2162 bool MipsAsmParser::parseSetNoReorderDirective() {
2164 // If this is not the end of the statement, report an error.
2165 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2166 reportParseError("unexpected token in statement");
2169 Options.setNoreorder();
2170 getTargetStreamer().emitDirectiveSetNoReorder();
2171 Parser.Lex(); // Consume the EndOfStatement.
2175 bool MipsAsmParser::parseSetMacroDirective() {
2177 // If this is not the end of the statement, report an error.
2178 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2179 reportParseError("unexpected token in statement");
2183 Parser.Lex(); // Consume the EndOfStatement.
2187 bool MipsAsmParser::parseSetNoMacroDirective() {
2189 // If this is not the end of the statement, report an error.
2190 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2191 reportParseError("`noreorder' must be set before `nomacro'");
2194 if (Options.isReorder()) {
2195 reportParseError("`noreorder' must be set before `nomacro'");
2198 Options.setNomacro();
2199 Parser.Lex(); // Consume the EndOfStatement.
2203 bool MipsAsmParser::parseSetNoMips16Directive() {
2205 // If this is not the end of the statement, report an error.
2206 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2207 reportParseError("unexpected token in statement");
2210 // For now do nothing.
2211 Parser.Lex(); // Consume the EndOfStatement.
2215 bool MipsAsmParser::parseSetAssignment() {
2217 const MCExpr *Value;
2219 if (Parser.parseIdentifier(Name))
2220 reportParseError("expected identifier after .set");
2222 if (getLexer().isNot(AsmToken::Comma))
2223 return reportParseError("unexpected token in .set directive");
2226 if (Parser.parseExpression(Value))
2227 return reportParseError("expected valid expression after comma");
2229 // Check if the Name already exists as a symbol.
2230 MCSymbol *Sym = getContext().LookupSymbol(Name);
2232 return reportParseError("symbol already defined");
2233 Sym = getContext().GetOrCreateSymbol(Name);
2234 Sym->setVariableValue(Value);
2239 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2241 if (getLexer().isNot(AsmToken::EndOfStatement))
2242 return reportParseError("unexpected token in .set directive");
2245 default: llvm_unreachable("Unimplemented feature");
2246 case Mips::FeatureDSP:
2247 setFeatureBits(Mips::FeatureDSP, "dsp");
2248 getTargetStreamer().emitDirectiveSetDsp();
2250 case Mips::FeatureMicroMips:
2251 getTargetStreamer().emitDirectiveSetMicroMips();
2253 case Mips::FeatureMips16:
2254 getTargetStreamer().emitDirectiveSetMips16();
2256 case Mips::FeatureMips32r2:
2257 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2258 getTargetStreamer().emitDirectiveSetMips32R2();
2260 case Mips::FeatureMips64:
2261 setFeatureBits(Mips::FeatureMips64, "mips64");
2262 getTargetStreamer().emitDirectiveSetMips64();
2264 case Mips::FeatureMips64r2:
2265 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2266 getTargetStreamer().emitDirectiveSetMips64R2();
2272 bool MipsAsmParser::parseRegister(unsigned &RegNum) {
2273 if (!getLexer().is(AsmToken::Dollar))
2278 const AsmToken &Reg = Parser.getTok();
2279 if (Reg.is(AsmToken::Identifier)) {
2280 RegNum = matchCPURegisterName(Reg.getIdentifier());
2281 } else if (Reg.is(AsmToken::Integer)) {
2282 RegNum = Reg.getIntVal();
2291 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2292 if (getLexer().isNot(AsmToken::Comma)) {
2293 SMLoc Loc = getLexer().getLoc();
2294 Parser.eatToEndOfStatement();
2295 return Error(Loc, ErrorStr);
2298 Parser.Lex(); // Eat the comma.
2302 bool MipsAsmParser::parseDirectiveCPSetup() {
2305 bool SaveIsReg = true;
2307 if (!parseRegister(FuncReg))
2308 return reportParseError("expected register containing function address");
2309 FuncReg = getGPR(FuncReg);
2311 if (!eatComma("expected comma parsing directive"))
2314 if (!parseRegister(Save)) {
2315 const AsmToken &Tok = Parser.getTok();
2316 if (Tok.is(AsmToken::Integer)) {
2317 Save = Tok.getIntVal();
2321 return reportParseError("expected save register or stack offset");
2323 Save = getGPR(Save);
2325 if (!eatComma("expected comma parsing directive"))
2329 if (Parser.parseIdentifier(Name))
2330 reportParseError("expected identifier");
2331 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2332 unsigned GPReg = getGPR(matchCPURegisterName("gp"));
2334 // FIXME: The code below this point should be in the TargetStreamers.
2335 // Only N32 and N64 emit anything for .cpsetup
2336 // FIXME: We should only emit something for PIC mode too.
2337 if (!isN32() && !isN64())
2340 MCStreamer &TS = getStreamer();
2342 // Either store the old $gp in a register or on the stack
2344 // move $save, $gpreg
2345 Inst.setOpcode(Mips::DADDu);
2346 Inst.addOperand(MCOperand::CreateReg(Save));
2347 Inst.addOperand(MCOperand::CreateReg(GPReg));
2348 Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
2350 // sd $gpreg, offset($sp)
2351 Inst.setOpcode(Mips::SD);
2352 Inst.addOperand(MCOperand::CreateReg(GPReg));
2353 Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
2354 Inst.addOperand(MCOperand::CreateImm(Save));
2356 TS.EmitInstruction(Inst, STI);
2359 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
2360 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI,
2362 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
2363 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO,
2365 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
2366 Inst.setOpcode(Mips::LUi);
2367 Inst.addOperand(MCOperand::CreateReg(GPReg));
2368 Inst.addOperand(MCOperand::CreateExpr(HiExpr));
2369 TS.EmitInstruction(Inst, STI);
2372 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
2373 Inst.setOpcode(Mips::ADDiu);
2374 Inst.addOperand(MCOperand::CreateReg(GPReg));
2375 Inst.addOperand(MCOperand::CreateReg(GPReg));
2376 Inst.addOperand(MCOperand::CreateExpr(LoExpr));
2377 TS.EmitInstruction(Inst, STI);
2380 // daddu $gp, $gp, $funcreg
2381 Inst.setOpcode(Mips::DADDu);
2382 Inst.addOperand(MCOperand::CreateReg(GPReg));
2383 Inst.addOperand(MCOperand::CreateReg(GPReg));
2384 Inst.addOperand(MCOperand::CreateReg(FuncReg));
2385 TS.EmitInstruction(Inst, STI);
2389 bool MipsAsmParser::parseDirectiveNaN() {
2390 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2391 const AsmToken &Tok = Parser.getTok();
2393 if (Tok.getString() == "2008") {
2395 getTargetStreamer().emitDirectiveNaN2008();
2397 } else if (Tok.getString() == "legacy") {
2399 getTargetStreamer().emitDirectiveNaNLegacy();
2403 // If we don't recognize the option passed to the .nan
2404 // directive (e.g. no option or unknown option), emit an error.
2405 reportParseError("invalid option in .nan directive");
2409 bool MipsAsmParser::parseDirectiveSet() {
2411 // Get the next token.
2412 const AsmToken &Tok = Parser.getTok();
2414 if (Tok.getString() == "noat") {
2415 return parseSetNoAtDirective();
2416 } else if (Tok.getString() == "at") {
2417 return parseSetAtDirective();
2418 } else if (Tok.getString() == "reorder") {
2419 return parseSetReorderDirective();
2420 } else if (Tok.getString() == "noreorder") {
2421 return parseSetNoReorderDirective();
2422 } else if (Tok.getString() == "macro") {
2423 return parseSetMacroDirective();
2424 } else if (Tok.getString() == "nomacro") {
2425 return parseSetNoMacroDirective();
2426 } else if (Tok.getString() == "mips16") {
2427 return parseSetFeature(Mips::FeatureMips16);
2428 } else if (Tok.getString() == "nomips16") {
2429 return parseSetNoMips16Directive();
2430 } else if (Tok.getString() == "nomicromips") {
2431 getTargetStreamer().emitDirectiveSetNoMicroMips();
2432 Parser.eatToEndOfStatement();
2434 } else if (Tok.getString() == "micromips") {
2435 return parseSetFeature(Mips::FeatureMicroMips);
2436 } else if (Tok.getString() == "mips32r2") {
2437 return parseSetFeature(Mips::FeatureMips32r2);
2438 } else if (Tok.getString() == "mips64") {
2439 return parseSetFeature(Mips::FeatureMips64);
2440 } else if (Tok.getString() == "mips64r2") {
2441 return parseSetFeature(Mips::FeatureMips64r2);
2442 } else if (Tok.getString() == "dsp") {
2443 return parseSetFeature(Mips::FeatureDSP);
2445 // It is just an identifier, look for an assignment.
2446 parseSetAssignment();
2453 /// parseDataDirective
2454 /// ::= .word [ expression (, expression)* ]
2455 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2456 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2458 const MCExpr *Value;
2459 if (getParser().parseExpression(Value))
2462 getParser().getStreamer().EmitValue(Value, Size);
2464 if (getLexer().is(AsmToken::EndOfStatement))
2467 // FIXME: Improve diagnostic.
2468 if (getLexer().isNot(AsmToken::Comma))
2469 return Error(L, "unexpected token in directive");
2478 /// parseDirectiveGpWord
2479 /// ::= .gpword local_sym
2480 bool MipsAsmParser::parseDirectiveGpWord() {
2481 const MCExpr *Value;
2482 // EmitGPRel32Value requires an expression, so we are using base class
2483 // method to evaluate the expression.
2484 if (getParser().parseExpression(Value))
2486 getParser().getStreamer().EmitGPRel32Value(Value);
2488 if (getLexer().isNot(AsmToken::EndOfStatement))
2489 return Error(getLexer().getLoc(), "unexpected token in directive");
2490 Parser.Lex(); // Eat EndOfStatement token.
2494 /// parseDirectiveGpDWord
2495 /// ::= .gpdword local_sym
2496 bool MipsAsmParser::parseDirectiveGpDWord() {
2497 const MCExpr *Value;
2498 // EmitGPRel64Value requires an expression, so we are using base class
2499 // method to evaluate the expression.
2500 if (getParser().parseExpression(Value))
2502 getParser().getStreamer().EmitGPRel64Value(Value);
2504 if (getLexer().isNot(AsmToken::EndOfStatement))
2505 return Error(getLexer().getLoc(), "unexpected token in directive");
2506 Parser.Lex(); // Eat EndOfStatement token.
2510 bool MipsAsmParser::parseDirectiveOption() {
2511 // Get the option token.
2512 AsmToken Tok = Parser.getTok();
2513 // At the moment only identifiers are supported.
2514 if (Tok.isNot(AsmToken::Identifier)) {
2515 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2516 Parser.eatToEndOfStatement();
2520 StringRef Option = Tok.getIdentifier();
2522 if (Option == "pic0") {
2523 getTargetStreamer().emitDirectiveOptionPic0();
2525 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2526 Error(Parser.getTok().getLoc(),
2527 "unexpected token in .option pic0 directive");
2528 Parser.eatToEndOfStatement();
2533 if (Option == "pic2") {
2534 getTargetStreamer().emitDirectiveOptionPic2();
2536 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2537 Error(Parser.getTok().getLoc(),
2538 "unexpected token in .option pic2 directive");
2539 Parser.eatToEndOfStatement();
2545 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2546 Parser.eatToEndOfStatement();
2550 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2551 StringRef IDVal = DirectiveID.getString();
2553 if (IDVal == ".dword") {
2554 parseDataDirective(8, DirectiveID.getLoc());
2558 if (IDVal == ".ent") {
2559 // Ignore this directive for now.
2564 if (IDVal == ".end") {
2565 // Ignore this directive for now.
2570 if (IDVal == ".frame") {
2571 // Ignore this directive for now.
2572 Parser.eatToEndOfStatement();
2576 if (IDVal == ".set") {
2577 return parseDirectiveSet();
2580 if (IDVal == ".fmask") {
2581 // Ignore this directive for now.
2582 Parser.eatToEndOfStatement();
2586 if (IDVal == ".mask") {
2587 // Ignore this directive for now.
2588 Parser.eatToEndOfStatement();
2592 if (IDVal == ".nan")
2593 return parseDirectiveNaN();
2595 if (IDVal == ".gpword") {
2596 parseDirectiveGpWord();
2600 if (IDVal == ".gpdword") {
2601 parseDirectiveGpDWord();
2605 if (IDVal == ".word") {
2606 parseDataDirective(4, DirectiveID.getLoc());
2610 if (IDVal == ".option")
2611 return parseDirectiveOption();
2613 if (IDVal == ".abicalls") {
2614 getTargetStreamer().emitDirectiveAbiCalls();
2615 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2616 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2618 Parser.eatToEndOfStatement();
2623 if (IDVal == ".cpsetup")
2624 return parseDirectiveCPSetup();
2629 extern "C" void LLVMInitializeMipsAsmParser() {
2630 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2631 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2632 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2633 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2636 #define GET_REGISTER_MATCHER
2637 #define GET_MATCHER_IMPLEMENTATION
2638 #include "MipsGenAsmMatcher.inc"