1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/MipsMCExpr.h"
11 #include "MCTargetDesc/MipsMCTargetDesc.h"
12 #include "MipsRegisterInfo.h"
13 #include "MipsTargetStreamer.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/StringSwitch.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstBuilder.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/MC/MCTargetAsmParser.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Support/TargetRegistry.h"
37 class MipsAssemblerOptions {
39 MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {}
41 unsigned getATRegNum() { return aTReg; }
42 bool setATReg(unsigned Reg);
44 bool isReorder() { return reorder; }
45 void setReorder() { reorder = true; }
46 void setNoreorder() { reorder = false; }
48 bool isMacro() { return macro; }
49 void setMacro() { macro = true; }
50 void setNomacro() { macro = false; }
60 class MipsAsmParser : public MCTargetAsmParser {
61 MipsTargetStreamer &getTargetStreamer() {
62 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
63 return static_cast<MipsTargetStreamer &>(TS);
68 MipsAssemblerOptions Options;
70 #define GET_ASSEMBLER_HEADER
71 #include "MipsGenAsmMatcher.inc"
73 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
74 SmallVectorImpl<MCParsedAsmOperand *> &Operands,
75 MCStreamer &Out, unsigned &ErrorInfo,
76 bool MatchingInlineAsm);
78 /// Parse a register as used in CFI directives
79 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
81 bool ParseParenSuffix(StringRef Name,
82 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
84 bool ParseBracketSuffix(StringRef Name,
85 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
87 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
89 SmallVectorImpl<MCParsedAsmOperand *> &Operands);
91 bool ParseDirective(AsmToken DirectiveID);
93 MipsAsmParser::OperandMatchResultTy
94 parseMemOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
96 MipsAsmParser::OperandMatchResultTy MatchAnyRegisterNameWithoutDollar(
97 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
100 MipsAsmParser::OperandMatchResultTy
101 MatchAnyRegisterWithoutDollar(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
104 MipsAsmParser::OperandMatchResultTy
105 ParseAnyRegister(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
107 MipsAsmParser::OperandMatchResultTy
108 ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
110 MipsAsmParser::OperandMatchResultTy
111 ParseJumpTarget(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
113 MipsAsmParser::OperandMatchResultTy
114 parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
116 MipsAsmParser::OperandMatchResultTy
117 ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
119 bool searchSymbolAlias(SmallVectorImpl<MCParsedAsmOperand *> &Operands);
121 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &,
124 bool needsExpansion(MCInst &Inst);
126 void expandInstruction(MCInst &Inst, SMLoc IDLoc,
127 SmallVectorImpl<MCInst> &Instructions);
128 void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
129 SmallVectorImpl<MCInst> &Instructions);
130 void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
131 SmallVectorImpl<MCInst> &Instructions);
132 void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
133 SmallVectorImpl<MCInst> &Instructions);
134 void expandMemInst(MCInst &Inst, SMLoc IDLoc,
135 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
137 bool reportParseError(StringRef ErrorMsg);
139 bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);
140 bool parseRelocOperand(const MCExpr *&Res);
142 const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr);
144 bool isEvaluated(const MCExpr *Expr);
145 bool parseSetFeature(uint64_t Feature);
146 bool parseDirectiveCPSetup();
147 bool parseDirectiveSet();
148 bool parseDirectiveOption();
150 bool parseSetAtDirective();
151 bool parseSetNoAtDirective();
152 bool parseSetMacroDirective();
153 bool parseSetNoMacroDirective();
154 bool parseSetReorderDirective();
155 bool parseSetNoReorderDirective();
156 bool parseSetNoMips16Directive();
158 bool parseSetAssignment();
160 bool parseDataDirective(unsigned Size, SMLoc L);
161 bool parseDirectiveGpWord();
162 bool parseDirectiveGpDWord();
164 MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
166 bool isGP64() const {
167 return (STI.getFeatureBits() & Mips::FeatureGP64Bit) != 0;
170 bool isFP64() const {
171 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
174 bool isN32() const { return STI.getFeatureBits() & Mips::FeatureN32; }
175 bool isN64() const { return STI.getFeatureBits() & Mips::FeatureN64; }
177 bool isMicroMips() const {
178 return STI.getFeatureBits() & Mips::FeatureMicroMips;
181 bool parseRegister(unsigned &RegNum);
183 bool eatComma(StringRef ErrorStr);
185 int matchCPURegisterName(StringRef Symbol);
187 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
189 int matchFPURegisterName(StringRef Name);
191 int matchFCCRegisterName(StringRef Name);
193 int matchACRegisterName(StringRef Name);
195 int matchMSA128RegisterName(StringRef Name);
197 int matchMSA128CtrlRegisterName(StringRef Name);
199 unsigned getReg(int RC, int RegNo);
201 unsigned getGPR(int RegNo);
205 bool processInstruction(MCInst &Inst, SMLoc IDLoc,
206 SmallVectorImpl<MCInst> &Instructions);
208 // Helper function that checks if the value of a vector index is within the
209 // boundaries of accepted values for each RegisterKind
210 // Example: INSERT.B $w0[n], $1 => 16 > n >= 0
211 bool validateMSAIndex(int Val, int RegKind);
213 void setFeatureBits(unsigned Feature, StringRef FeatureString) {
214 if (!(STI.getFeatureBits() & Feature)) {
215 setAvailableFeatures(ComputeAvailableFeatures(
216 STI.ToggleFeature(FeatureString)));
220 void clearFeatureBits(unsigned Feature, StringRef FeatureString) {
221 if (STI.getFeatureBits() & Feature) {
222 setAvailableFeatures(ComputeAvailableFeatures(
223 STI.ToggleFeature(FeatureString)));
228 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
229 const MCInstrInfo &MII)
230 : MCTargetAsmParser(), STI(sti), Parser(parser) {
231 // Initialize the set of available features.
232 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
234 // Assert exactly one ABI was chosen.
235 assert((((STI.getFeatureBits() & Mips::FeatureO32) != 0) +
236 ((STI.getFeatureBits() & Mips::FeatureEABI) != 0) +
237 ((STI.getFeatureBits() & Mips::FeatureN32) != 0) +
238 ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
241 MCAsmParser &getParser() const { return Parser; }
242 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
244 /// Warn if RegNo is the current assembler temporary.
245 void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc);
251 /// MipsOperand - Instances of this class represent a parsed Mips machine
253 class MipsOperand : public MCParsedAsmOperand {
255 /// Broad categories of register classes
256 /// The exact class is finalized by the render method.
258 RegKind_GPR = 1, /// GPR32 and GPR64 (depending on isGP64())
259 RegKind_FGR = 2, /// FGR32, FGR64, AFGR64 (depending on context and
261 RegKind_FCC = 4, /// FCC
262 RegKind_MSA128 = 8, /// MSA128[BHWD] (makes no difference which)
263 RegKind_MSACtrl = 16, /// MSA control registers
264 RegKind_COP2 = 32, /// COP2
265 RegKind_ACC = 64, /// HI32DSP, LO32DSP, and ACC64DSP (depending on
267 RegKind_CCR = 128, /// CCR
268 RegKind_HWRegs = 256, /// HWRegs
270 /// Potentially any (e.g. $1)
271 RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
272 RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
273 RegKind_CCR | RegKind_HWRegs
278 k_Immediate, /// An immediate (possibly involving symbol references)
279 k_Memory, /// Base + Offset Memory Address
280 k_PhysRegister, /// A physical register from the Mips namespace
281 k_RegisterIndex, /// A register index in one or more RegKind.
282 k_Token /// A simple token
285 MipsOperand(KindTy K, MipsAsmParser &Parser)
286 : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
288 /// For diagnostics, and checking the assembler temporary
289 MipsAsmParser &AsmParser;
297 unsigned Num; /// Register Number
301 unsigned Index; /// Index into the register class
302 RegKind Kind; /// Bitfield of the kinds it could possibly be
303 const MCRegisterInfo *RegInfo;
317 struct PhysRegOp PhysReg;
318 struct RegIdxOp RegIdx;
323 SMLoc StartLoc, EndLoc;
325 /// Internal constructor for register kinds
326 static MipsOperand *CreateReg(unsigned Index, RegKind RegKind,
327 const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E,
328 MipsAsmParser &Parser) {
329 MipsOperand *Op = new MipsOperand(k_RegisterIndex, Parser);
330 Op->RegIdx.Index = Index;
331 Op->RegIdx.RegInfo = RegInfo;
332 Op->RegIdx.Kind = RegKind;
339 /// Coerce the register to GPR32 and return the real register for the current
341 unsigned getGPR32Reg() const {
342 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
343 AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc);
344 unsigned ClassID = Mips::GPR32RegClassID;
345 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
348 /// Coerce the register to GPR64 and return the real register for the current
350 unsigned getGPR64Reg() const {
351 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
352 unsigned ClassID = Mips::GPR64RegClassID;
353 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
357 /// Coerce the register to AFGR64 and return the real register for the current
359 unsigned getAFGR64Reg() const {
360 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
361 if (RegIdx.Index % 2 != 0)
362 AsmParser.Warning(StartLoc, "Float register should be even.");
363 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
364 .getRegister(RegIdx.Index / 2);
367 /// Coerce the register to FGR64 and return the real register for the current
369 unsigned getFGR64Reg() const {
370 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
371 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
372 .getRegister(RegIdx.Index);
375 /// Coerce the register to FGR32 and return the real register for the current
377 unsigned getFGR32Reg() const {
378 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
379 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
380 .getRegister(RegIdx.Index);
383 /// Coerce the register to FGRH32 and return the real register for the current
385 unsigned getFGRH32Reg() const {
386 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
387 return RegIdx.RegInfo->getRegClass(Mips::FGRH32RegClassID)
388 .getRegister(RegIdx.Index);
391 /// Coerce the register to FCC and return the real register for the current
393 unsigned getFCCReg() const {
394 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
395 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
396 .getRegister(RegIdx.Index);
399 /// Coerce the register to MSA128 and return the real register for the current
401 unsigned getMSA128Reg() const {
402 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
403 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
405 unsigned ClassID = Mips::MSA128BRegClassID;
406 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
409 /// Coerce the register to MSACtrl and return the real register for the
411 unsigned getMSACtrlReg() const {
412 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
413 unsigned ClassID = Mips::MSACtrlRegClassID;
414 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
417 /// Coerce the register to COP2 and return the real register for the
419 unsigned getCOP2Reg() const {
420 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
421 unsigned ClassID = Mips::COP2RegClassID;
422 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
425 /// Coerce the register to ACC64DSP and return the real register for the
427 unsigned getACC64DSPReg() const {
428 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
429 unsigned ClassID = Mips::ACC64DSPRegClassID;
430 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
433 /// Coerce the register to HI32DSP and return the real register for the
435 unsigned getHI32DSPReg() const {
436 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
437 unsigned ClassID = Mips::HI32DSPRegClassID;
438 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
441 /// Coerce the register to LO32DSP and return the real register for the
443 unsigned getLO32DSPReg() const {
444 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
445 unsigned ClassID = Mips::LO32DSPRegClassID;
446 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
449 /// Coerce the register to CCR and return the real register for the
451 unsigned getCCRReg() const {
452 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
453 unsigned ClassID = Mips::CCRRegClassID;
454 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
457 /// Coerce the register to HWRegs and return the real register for the
459 unsigned getHWRegsReg() const {
460 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
461 unsigned ClassID = Mips::HWRegsRegClassID;
462 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
466 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
467 // Add as immediate when possible. Null MCExpr = 0.
469 Inst.addOperand(MCOperand::CreateImm(0));
470 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
471 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
473 Inst.addOperand(MCOperand::CreateExpr(Expr));
476 void addRegOperands(MCInst &Inst, unsigned N) const {
477 llvm_unreachable("Use a custom parser instead");
480 /// Render the operand to an MCInst as a GPR32
481 /// Asserts if the wrong number of operands are requested, or the operand
482 /// is not a k_RegisterIndex compatible with RegKind_GPR
483 void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
484 assert(N == 1 && "Invalid number of operands!");
485 Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
488 /// Render the operand to an MCInst as a GPR64
489 /// Asserts if the wrong number of operands are requested, or the operand
490 /// is not a k_RegisterIndex compatible with RegKind_GPR
491 void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
492 assert(N == 1 && "Invalid number of operands!");
493 Inst.addOperand(MCOperand::CreateReg(getGPR64Reg()));
496 void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
497 assert(N == 1 && "Invalid number of operands!");
498 Inst.addOperand(MCOperand::CreateReg(getAFGR64Reg()));
501 void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
502 assert(N == 1 && "Invalid number of operands!");
503 Inst.addOperand(MCOperand::CreateReg(getFGR64Reg()));
506 void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
507 assert(N == 1 && "Invalid number of operands!");
508 Inst.addOperand(MCOperand::CreateReg(getFGR32Reg()));
511 void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const {
512 assert(N == 1 && "Invalid number of operands!");
513 Inst.addOperand(MCOperand::CreateReg(getFGRH32Reg()));
516 void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
517 assert(N == 1 && "Invalid number of operands!");
518 Inst.addOperand(MCOperand::CreateReg(getFCCReg()));
521 void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
522 assert(N == 1 && "Invalid number of operands!");
523 Inst.addOperand(MCOperand::CreateReg(getMSA128Reg()));
526 void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
527 assert(N == 1 && "Invalid number of operands!");
528 Inst.addOperand(MCOperand::CreateReg(getMSACtrlReg()));
531 void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
532 assert(N == 1 && "Invalid number of operands!");
533 Inst.addOperand(MCOperand::CreateReg(getCOP2Reg()));
536 void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
537 assert(N == 1 && "Invalid number of operands!");
538 Inst.addOperand(MCOperand::CreateReg(getACC64DSPReg()));
541 void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
542 assert(N == 1 && "Invalid number of operands!");
543 Inst.addOperand(MCOperand::CreateReg(getHI32DSPReg()));
546 void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
547 assert(N == 1 && "Invalid number of operands!");
548 Inst.addOperand(MCOperand::CreateReg(getLO32DSPReg()));
551 void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
552 assert(N == 1 && "Invalid number of operands!");
553 Inst.addOperand(MCOperand::CreateReg(getCCRReg()));
556 void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
557 assert(N == 1 && "Invalid number of operands!");
558 Inst.addOperand(MCOperand::CreateReg(getHWRegsReg()));
561 void addImmOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 1 && "Invalid number of operands!");
563 const MCExpr *Expr = getImm();
567 void addMemOperands(MCInst &Inst, unsigned N) const {
568 assert(N == 2 && "Invalid number of operands!");
570 Inst.addOperand(MCOperand::CreateReg(getMemBase()->getGPR32Reg()));
572 const MCExpr *Expr = getMemOff();
577 // As a special case until we sort out the definition of div/divu, pretend
578 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
579 if (isGPRAsmReg() && RegIdx.Index == 0)
582 return Kind == k_PhysRegister;
584 bool isRegIdx() const { return Kind == k_RegisterIndex; }
585 bool isImm() const { return Kind == k_Immediate; }
586 bool isConstantImm() const {
587 return isImm() && dyn_cast<MCConstantExpr>(getImm());
589 bool isToken() const {
590 // Note: It's not possible to pretend that other operand kinds are tokens.
591 // The matcher emitter checks tokens first.
592 return Kind == k_Token;
594 bool isMem() const { return Kind == k_Memory; }
595 bool isInvNum() const { return Kind == k_Immediate; }
596 bool isLSAImm() const {
597 if (!isConstantImm())
599 int64_t Val = getConstantImm();
600 return 1 <= Val && Val <= 4;
603 StringRef getToken() const {
604 assert(Kind == k_Token && "Invalid access!");
605 return StringRef(Tok.Data, Tok.Length);
608 unsigned getReg() const {
609 // As a special case until we sort out the definition of div/divu, pretend
610 // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly.
611 if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
612 RegIdx.Kind & RegKind_GPR)
613 return getGPR32Reg(); // FIXME: GPR64 too
615 assert(Kind == k_PhysRegister && "Invalid access!");
619 const MCExpr *getImm() const {
620 assert((Kind == k_Immediate) && "Invalid access!");
624 int64_t getConstantImm() const {
625 const MCExpr *Val = getImm();
626 return static_cast<const MCConstantExpr *>(Val)->getValue();
629 MipsOperand *getMemBase() const {
630 assert((Kind == k_Memory) && "Invalid access!");
634 const MCExpr *getMemOff() const {
635 assert((Kind == k_Memory) && "Invalid access!");
639 static MipsOperand *CreateToken(StringRef Str, SMLoc S,
640 MipsAsmParser &Parser) {
641 MipsOperand *Op = new MipsOperand(k_Token, Parser);
642 Op->Tok.Data = Str.data();
643 Op->Tok.Length = Str.size();
649 /// Create a numeric register (e.g. $1). The exact register remains
650 /// unresolved until an instruction successfully matches
651 static MipsOperand *CreateNumericReg(unsigned Index,
652 const MCRegisterInfo *RegInfo, SMLoc S,
653 SMLoc E, MipsAsmParser &Parser) {
654 DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n");
655 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser);
658 /// Create a register that is definitely a GPR.
659 /// This is typically only used for named registers such as $gp.
660 static MipsOperand *CreateGPRReg(unsigned Index,
661 const MCRegisterInfo *RegInfo, SMLoc S,
662 SMLoc E, MipsAsmParser &Parser) {
663 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser);
666 /// Create a register that is definitely a FGR.
667 /// This is typically only used for named registers such as $f0.
668 static MipsOperand *CreateFGRReg(unsigned Index,
669 const MCRegisterInfo *RegInfo, SMLoc S,
670 SMLoc E, MipsAsmParser &Parser) {
671 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser);
674 /// Create a register that is definitely an FCC.
675 /// This is typically only used for named registers such as $fcc0.
676 static MipsOperand *CreateFCCReg(unsigned Index,
677 const MCRegisterInfo *RegInfo, SMLoc S,
678 SMLoc E, MipsAsmParser &Parser) {
679 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser);
682 /// Create a register that is definitely an ACC.
683 /// This is typically only used for named registers such as $ac0.
684 static MipsOperand *CreateACCReg(unsigned Index,
685 const MCRegisterInfo *RegInfo, SMLoc S,
686 SMLoc E, MipsAsmParser &Parser) {
687 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser);
690 /// Create a register that is definitely an MSA128.
691 /// This is typically only used for named registers such as $w0.
692 static MipsOperand *CreateMSA128Reg(unsigned Index,
693 const MCRegisterInfo *RegInfo, SMLoc S,
694 SMLoc E, MipsAsmParser &Parser) {
695 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser);
698 /// Create a register that is definitely an MSACtrl.
699 /// This is typically only used for named registers such as $msaaccess.
700 static MipsOperand *CreateMSACtrlReg(unsigned Index,
701 const MCRegisterInfo *RegInfo, SMLoc S,
702 SMLoc E, MipsAsmParser &Parser) {
703 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
706 static MipsOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E,
707 MipsAsmParser &Parser) {
708 MipsOperand *Op = new MipsOperand(k_Immediate, Parser);
715 static MipsOperand *CreateMem(MipsOperand *Base, const MCExpr *Off, SMLoc S,
716 SMLoc E, MipsAsmParser &Parser) {
717 MipsOperand *Op = new MipsOperand(k_Memory, Parser);
725 bool isGPRAsmReg() const {
726 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
728 bool isFGRAsmReg() const {
729 // AFGR64 is $0-$15 but we handle this in getAFGR64()
730 return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
732 bool isHWRegsAsmReg() const {
733 return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
735 bool isCCRAsmReg() const {
736 return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
738 bool isFCCAsmReg() const {
739 return isRegIdx() && RegIdx.Kind & RegKind_FCC && RegIdx.Index <= 7;
741 bool isACCAsmReg() const {
742 return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
744 bool isCOP2AsmReg() const {
745 return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
747 bool isMSA128AsmReg() const {
748 return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
750 bool isMSACtrlAsmReg() const {
751 return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
754 /// getStartLoc - Get the location of the first token of this operand.
755 SMLoc getStartLoc() const { return StartLoc; }
756 /// getEndLoc - Get the location of the last token of this operand.
757 SMLoc getEndLoc() const { return EndLoc; }
759 virtual void print(raw_ostream &OS) const {
774 OS << "PhysReg<" << PhysReg.Num << ">";
776 case k_RegisterIndex:
777 OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">";
784 }; // class MipsOperand
788 extern const MCInstrDesc MipsInsts[];
790 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
791 return MipsInsts[Opcode];
794 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
795 SmallVectorImpl<MCInst> &Instructions) {
796 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
800 if (MCID.isBranch() || MCID.isCall()) {
801 const unsigned Opcode = Inst.getOpcode();
811 assert(MCID.getNumOperands() == 3 && "unexpected number of operands");
812 Offset = Inst.getOperand(2);
814 break; // We'll deal with this situation later on when applying fixups.
815 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
816 return Error(IDLoc, "branch target out of range");
817 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
818 return Error(IDLoc, "branch to misaligned address");
832 case Mips::BGEZAL_MM:
833 case Mips::BLTZAL_MM:
836 assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
837 Offset = Inst.getOperand(1);
839 break; // We'll deal with this situation later on when applying fixups.
840 if (!isIntN(isMicroMips() ? 17 : 18, Offset.getImm()))
841 return Error(IDLoc, "branch target out of range");
842 if (OffsetToAlignment(Offset.getImm(), 1LL << (isMicroMips() ? 1 : 2)))
843 return Error(IDLoc, "branch to misaligned address");
848 if (MCID.hasDelaySlot() && Options.isReorder()) {
849 // If this instruction has a delay slot and .set reorder is active,
850 // emit a NOP after it.
851 Instructions.push_back(Inst);
853 NopInst.setOpcode(Mips::SLL);
854 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
855 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
856 NopInst.addOperand(MCOperand::CreateImm(0));
857 Instructions.push_back(NopInst);
861 if (MCID.mayLoad() || MCID.mayStore()) {
862 // Check the offset of memory operand, if it is a symbol
863 // reference or immediate we may have to expand instructions.
864 for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
865 const MCOperandInfo &OpInfo = MCID.OpInfo[i];
866 if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
867 (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
868 MCOperand &Op = Inst.getOperand(i);
870 int MemOffset = Op.getImm();
871 if (MemOffset < -32768 || MemOffset > 32767) {
872 // Offset can't exceed 16bit value.
873 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), true);
876 } else if (Op.isExpr()) {
877 const MCExpr *Expr = Op.getExpr();
878 if (Expr->getKind() == MCExpr::SymbolRef) {
879 const MCSymbolRefExpr *SR =
880 static_cast<const MCSymbolRefExpr *>(Expr);
881 if (SR->getKind() == MCSymbolRefExpr::VK_None) {
883 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
886 } else if (!isEvaluated(Expr)) {
887 expandMemInst(Inst, IDLoc, Instructions, MCID.mayLoad(), false);
895 if (needsExpansion(Inst))
896 expandInstruction(Inst, IDLoc, Instructions);
898 Instructions.push_back(Inst);
903 bool MipsAsmParser::needsExpansion(MCInst &Inst) {
905 switch (Inst.getOpcode()) {
906 case Mips::LoadImm32Reg:
907 case Mips::LoadAddr32Imm:
908 case Mips::LoadAddr32Reg:
919 void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
920 SmallVectorImpl<MCInst> &Instructions) {
921 switch (Inst.getOpcode()) {
922 case Mips::LoadImm32Reg:
923 return expandLoadImm(Inst, IDLoc, Instructions);
924 case Mips::LoadAddr32Imm:
925 return expandLoadAddressImm(Inst, IDLoc, Instructions);
926 case Mips::LoadAddr32Reg:
927 return expandLoadAddressReg(Inst, IDLoc, Instructions);
929 Instructions.push_back(MCInstBuilder(Mips::ADDi)
930 .addReg(Inst.getOperand(0).getReg())
931 .addReg(Inst.getOperand(1).getReg())
932 .addImm(-Inst.getOperand(2).getImm()));
935 Instructions.push_back(MCInstBuilder(Mips::ADDiu)
936 .addReg(Inst.getOperand(0).getReg())
937 .addReg(Inst.getOperand(1).getReg())
938 .addImm(-Inst.getOperand(2).getImm()));
941 Instructions.push_back(MCInstBuilder(Mips::DADDi)
942 .addReg(Inst.getOperand(0).getReg())
943 .addReg(Inst.getOperand(1).getReg())
944 .addImm(-Inst.getOperand(2).getImm()));
947 Instructions.push_back(MCInstBuilder(Mips::DADDiu)
948 .addReg(Inst.getOperand(0).getReg())
949 .addReg(Inst.getOperand(1).getReg())
950 .addImm(-Inst.getOperand(2).getImm()));
955 void MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
956 SmallVectorImpl<MCInst> &Instructions) {
958 const MCOperand &ImmOp = Inst.getOperand(1);
959 assert(ImmOp.isImm() && "expected immediate operand kind");
960 const MCOperand &RegOp = Inst.getOperand(0);
961 assert(RegOp.isReg() && "expected register operand kind");
963 int ImmValue = ImmOp.getImm();
964 tmpInst.setLoc(IDLoc);
965 if (0 <= ImmValue && ImmValue <= 65535) {
966 // For 0 <= j <= 65535.
967 // li d,j => ori d,$zero,j
968 tmpInst.setOpcode(Mips::ORi);
969 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
970 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
971 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
972 Instructions.push_back(tmpInst);
973 } else if (ImmValue < 0 && ImmValue >= -32768) {
974 // For -32768 <= j < 0.
975 // li d,j => addiu d,$zero,j
976 tmpInst.setOpcode(Mips::ADDiu);
977 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
978 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
979 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
980 Instructions.push_back(tmpInst);
982 // For any other value of j that is representable as a 32-bit integer.
983 // li d,j => lui d,hi16(j)
985 tmpInst.setOpcode(Mips::LUi);
986 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
987 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
988 Instructions.push_back(tmpInst);
990 tmpInst.setOpcode(Mips::ORi);
991 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
992 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
993 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
994 tmpInst.setLoc(IDLoc);
995 Instructions.push_back(tmpInst);
1000 MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
1001 SmallVectorImpl<MCInst> &Instructions) {
1003 const MCOperand &ImmOp = Inst.getOperand(2);
1004 assert(ImmOp.isImm() && "expected immediate operand kind");
1005 const MCOperand &SrcRegOp = Inst.getOperand(1);
1006 assert(SrcRegOp.isReg() && "expected register operand kind");
1007 const MCOperand &DstRegOp = Inst.getOperand(0);
1008 assert(DstRegOp.isReg() && "expected register operand kind");
1009 int ImmValue = ImmOp.getImm();
1010 if (-32768 <= ImmValue && ImmValue <= 65535) {
1011 // For -32768 <= j <= 65535.
1012 // la d,j(s) => addiu d,s,j
1013 tmpInst.setOpcode(Mips::ADDiu);
1014 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1015 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1016 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1017 Instructions.push_back(tmpInst);
1019 // For any other value of j that is representable as a 32-bit integer.
1020 // la d,j(s) => lui d,hi16(j)
1023 tmpInst.setOpcode(Mips::LUi);
1024 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1025 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1026 Instructions.push_back(tmpInst);
1028 tmpInst.setOpcode(Mips::ORi);
1029 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1030 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1031 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1032 Instructions.push_back(tmpInst);
1034 tmpInst.setOpcode(Mips::ADDu);
1035 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1036 tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
1037 tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
1038 Instructions.push_back(tmpInst);
1043 MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
1044 SmallVectorImpl<MCInst> &Instructions) {
1046 const MCOperand &ImmOp = Inst.getOperand(1);
1047 assert(ImmOp.isImm() && "expected immediate operand kind");
1048 const MCOperand &RegOp = Inst.getOperand(0);
1049 assert(RegOp.isReg() && "expected register operand kind");
1050 int ImmValue = ImmOp.getImm();
1051 if (-32768 <= ImmValue && ImmValue <= 65535) {
1052 // For -32768 <= j <= 65535.
1053 // la d,j => addiu d,$zero,j
1054 tmpInst.setOpcode(Mips::ADDiu);
1055 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1056 tmpInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
1057 tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
1058 Instructions.push_back(tmpInst);
1060 // For any other value of j that is representable as a 32-bit integer.
1061 // la d,j => lui d,hi16(j)
1063 tmpInst.setOpcode(Mips::LUi);
1064 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1065 tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
1066 Instructions.push_back(tmpInst);
1068 tmpInst.setOpcode(Mips::ORi);
1069 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1070 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
1071 tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0xffff));
1072 Instructions.push_back(tmpInst);
1076 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
1077 SmallVectorImpl<MCInst> &Instructions,
1078 bool isLoad, bool isImmOpnd) {
1079 const MCSymbolRefExpr *SR;
1081 unsigned ImmOffset, HiOffset, LoOffset;
1082 const MCExpr *ExprOffset;
1084 unsigned AtRegNum = getReg(
1085 (isGP64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, getATReg());
1086 // 1st operand is either the source or destination register.
1087 assert(Inst.getOperand(0).isReg() && "expected register operand kind");
1088 unsigned RegOpNum = Inst.getOperand(0).getReg();
1089 // 2nd operand is the base register.
1090 assert(Inst.getOperand(1).isReg() && "expected register operand kind");
1091 unsigned BaseRegNum = Inst.getOperand(1).getReg();
1092 // 3rd operand is either an immediate or expression.
1094 assert(Inst.getOperand(2).isImm() && "expected immediate operand kind");
1095 ImmOffset = Inst.getOperand(2).getImm();
1096 LoOffset = ImmOffset & 0x0000ffff;
1097 HiOffset = (ImmOffset & 0xffff0000) >> 16;
1098 // If msb of LoOffset is 1(negative number) we must increment HiOffset.
1099 if (LoOffset & 0x8000)
1102 ExprOffset = Inst.getOperand(2).getExpr();
1103 // All instructions will have the same location.
1104 TempInst.setLoc(IDLoc);
1105 // 1st instruction in expansion is LUi. For load instruction we can use
1106 // the dst register as a temporary if base and dst are different,
1107 // but for stores we must use $at.
1108 TmpRegNum = (isLoad && (BaseRegNum != RegOpNum)) ? RegOpNum : AtRegNum;
1109 TempInst.setOpcode(Mips::LUi);
1110 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1112 TempInst.addOperand(MCOperand::CreateImm(HiOffset));
1114 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1115 SR = static_cast<const MCSymbolRefExpr *>(ExprOffset);
1116 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
1117 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_HI,
1119 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1121 const MCExpr *HiExpr = evaluateRelocExpr(ExprOffset, "hi");
1122 TempInst.addOperand(MCOperand::CreateExpr(HiExpr));
1125 // Add the instruction to the list.
1126 Instructions.push_back(TempInst);
1127 // Prepare TempInst for next instruction.
1129 // Add temp register to base.
1130 TempInst.setOpcode(Mips::ADDu);
1131 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1132 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1133 TempInst.addOperand(MCOperand::CreateReg(BaseRegNum));
1134 Instructions.push_back(TempInst);
1136 // And finally, create original instruction with low part
1137 // of offset and new base.
1138 TempInst.setOpcode(Inst.getOpcode());
1139 TempInst.addOperand(MCOperand::CreateReg(RegOpNum));
1140 TempInst.addOperand(MCOperand::CreateReg(TmpRegNum));
1142 TempInst.addOperand(MCOperand::CreateImm(LoOffset));
1144 if (ExprOffset->getKind() == MCExpr::SymbolRef) {
1145 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
1146 SR->getSymbol().getName(), MCSymbolRefExpr::VK_Mips_ABS_LO,
1148 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1150 const MCExpr *LoExpr = evaluateRelocExpr(ExprOffset, "lo");
1151 TempInst.addOperand(MCOperand::CreateExpr(LoExpr));
1154 Instructions.push_back(TempInst);
1158 bool MipsAsmParser::MatchAndEmitInstruction(
1159 SMLoc IDLoc, unsigned &Opcode,
1160 SmallVectorImpl<MCParsedAsmOperand *> &Operands, MCStreamer &Out,
1161 unsigned &ErrorInfo, bool MatchingInlineAsm) {
1163 SmallVector<MCInst, 8> Instructions;
1164 unsigned MatchResult =
1165 MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
1167 switch (MatchResult) {
1170 case Match_Success: {
1171 if (processInstruction(Inst, IDLoc, Instructions))
1173 for (unsigned i = 0; i < Instructions.size(); i++)
1174 Out.EmitInstruction(Instructions[i], STI);
1177 case Match_MissingFeature:
1178 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1180 case Match_InvalidOperand: {
1181 SMLoc ErrorLoc = IDLoc;
1182 if (ErrorInfo != ~0U) {
1183 if (ErrorInfo >= Operands.size())
1184 return Error(IDLoc, "too few operands for instruction");
1186 ErrorLoc = ((MipsOperand *)Operands[ErrorInfo])->getStartLoc();
1187 if (ErrorLoc == SMLoc())
1191 return Error(ErrorLoc, "invalid operand for instruction");
1193 case Match_MnemonicFail:
1194 return Error(IDLoc, "invalid instruction");
1199 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) {
1200 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) {
1202 Warning(Loc, "Used $at without \".set noat\"");
1204 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" +
1205 Twine(RegIndex) + "\"");
1209 int MipsAsmParser::matchCPURegisterName(StringRef Name) {
1212 CC = StringSwitch<unsigned>(Name)
1248 if (isN32() || isN64()) {
1249 // Although SGI documentation just cuts out t0-t3 for n32/n64,
1250 // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7
1251 // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7.
1252 if (8 <= CC && CC <= 11)
1256 CC = StringSwitch<unsigned>(Name)
1269 int MipsAsmParser::matchFPURegisterName(StringRef Name) {
1271 if (Name[0] == 'f') {
1272 StringRef NumString = Name.substr(1);
1274 if (NumString.getAsInteger(10, IntVal))
1275 return -1; // This is not an integer.
1276 if (IntVal > 31) // Maximum index for fpu register.
1283 int MipsAsmParser::matchFCCRegisterName(StringRef Name) {
1285 if (Name.startswith("fcc")) {
1286 StringRef NumString = Name.substr(3);
1288 if (NumString.getAsInteger(10, IntVal))
1289 return -1; // This is not an integer.
1290 if (IntVal > 7) // There are only 8 fcc registers.
1297 int MipsAsmParser::matchACRegisterName(StringRef Name) {
1299 if (Name.startswith("ac")) {
1300 StringRef NumString = Name.substr(2);
1302 if (NumString.getAsInteger(10, IntVal))
1303 return -1; // This is not an integer.
1304 if (IntVal > 3) // There are only 3 acc registers.
1311 int MipsAsmParser::matchMSA128RegisterName(StringRef Name) {
1314 if (Name.front() != 'w' || Name.drop_front(1).getAsInteger(10, IntVal))
1323 int MipsAsmParser::matchMSA128CtrlRegisterName(StringRef Name) {
1326 CC = StringSwitch<unsigned>(Name)
1329 .Case("msaaccess", 2)
1331 .Case("msamodify", 4)
1332 .Case("msarequest", 5)
1334 .Case("msaunmap", 7)
1340 bool MipsAssemblerOptions::setATReg(unsigned Reg) {
1348 int MipsAsmParser::getATReg() {
1349 int AT = Options.getATRegNum();
1351 TokError("Pseudo instruction requires $at, which is not available");
1355 unsigned MipsAsmParser::getReg(int RC, int RegNo) {
1356 return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
1359 unsigned MipsAsmParser::getGPR(int RegNo) {
1360 return getReg(isGP64() ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
1364 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
1366 getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs() - 1)
1369 return getReg(RegClass, RegNum);
1373 MipsAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand *> &Operands,
1374 StringRef Mnemonic) {
1375 DEBUG(dbgs() << "ParseOperand\n");
1377 // Check if the current operand has a custom associated parser, if so, try to
1378 // custom parse the operand, or fallback to the general approach.
1379 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1380 if (ResTy == MatchOperand_Success)
1382 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1383 // there was a match, but an error occurred, in which case, just return that
1384 // the operand parsing failed.
1385 if (ResTy == MatchOperand_ParseFail)
1388 DEBUG(dbgs() << ".. Generic Parser\n");
1390 switch (getLexer().getKind()) {
1392 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1394 case AsmToken::Dollar: {
1395 // Parse the register.
1396 SMLoc S = Parser.getTok().getLoc();
1398 // Almost all registers have been parsed by custom parsers. There is only
1399 // one exception to this. $zero (and it's alias $0) will reach this point
1400 // for div, divu, and similar instructions because it is not an operand
1401 // to the instruction definition but an explicit register. Special case
1402 // this situation for now.
1403 if (ParseAnyRegister(Operands) != MatchOperand_NoMatch)
1406 // Maybe it is a symbol reference.
1407 StringRef Identifier;
1408 if (Parser.parseIdentifier(Identifier))
1411 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1412 MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
1413 // Otherwise create a symbol reference.
1415 MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext());
1417 Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this));
1420 // Else drop to expression parsing.
1421 case AsmToken::LParen:
1422 case AsmToken::Minus:
1423 case AsmToken::Plus:
1424 case AsmToken::Integer:
1425 case AsmToken::String: {
1426 DEBUG(dbgs() << ".. generic integer\n");
1427 OperandMatchResultTy ResTy = ParseImm(Operands);
1428 return ResTy != MatchOperand_Success;
1430 case AsmToken::Percent: {
1431 // It is a symbol reference or constant expression.
1432 const MCExpr *IdVal;
1433 SMLoc S = Parser.getTok().getLoc(); // Start location of the operand.
1434 if (parseRelocOperand(IdVal))
1437 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1439 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1441 } // case AsmToken::Percent
1442 } // switch(getLexer().getKind())
1446 const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr,
1447 StringRef RelocStr) {
1449 // Check the type of the expression.
1450 if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Expr)) {
1451 // It's a constant, evaluate reloc value.
1453 switch (getVariantKind(RelocStr)) {
1454 case MCSymbolRefExpr::VK_Mips_ABS_LO:
1455 // Get the 1st 16-bits.
1456 Val = MCE->getValue() & 0xffff;
1458 case MCSymbolRefExpr::VK_Mips_ABS_HI:
1459 // Get the 2nd 16-bits. Also add 1 if bit 15 is 1, to compensate for low
1460 // 16 bits being negative.
1461 Val = ((MCE->getValue() + 0x8000) >> 16) & 0xffff;
1463 case MCSymbolRefExpr::VK_Mips_HIGHER:
1464 // Get the 3rd 16-bits.
1465 Val = ((MCE->getValue() + 0x80008000LL) >> 32) & 0xffff;
1467 case MCSymbolRefExpr::VK_Mips_HIGHEST:
1468 // Get the 4th 16-bits.
1469 Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff;
1472 report_fatal_error("Unsupported reloc value!");
1474 return MCConstantExpr::Create(Val, getContext());
1477 if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(Expr)) {
1478 // It's a symbol, create a symbolic expression from the symbol.
1479 StringRef Symbol = MSRE->getSymbol().getName();
1480 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1481 Res = MCSymbolRefExpr::Create(Symbol, VK, getContext());
1485 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1486 MCSymbolRefExpr::VariantKind VK = getVariantKind(RelocStr);
1488 // Try to create target expression.
1489 if (MipsMCExpr::isSupportedBinaryExpr(VK, BE))
1490 return MipsMCExpr::Create(VK, Expr, getContext());
1492 const MCExpr *LExp = evaluateRelocExpr(BE->getLHS(), RelocStr);
1493 const MCExpr *RExp = evaluateRelocExpr(BE->getRHS(), RelocStr);
1494 Res = MCBinaryExpr::Create(BE->getOpcode(), LExp, RExp, getContext());
1498 if (const MCUnaryExpr *UN = dyn_cast<MCUnaryExpr>(Expr)) {
1499 const MCExpr *UnExp = evaluateRelocExpr(UN->getSubExpr(), RelocStr);
1500 Res = MCUnaryExpr::Create(UN->getOpcode(), UnExp, getContext());
1503 // Just return the original expression.
1507 bool MipsAsmParser::isEvaluated(const MCExpr *Expr) {
1509 switch (Expr->getKind()) {
1510 case MCExpr::Constant:
1512 case MCExpr::SymbolRef:
1513 return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
1514 case MCExpr::Binary:
1515 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr)) {
1516 if (!isEvaluated(BE->getLHS()))
1518 return isEvaluated(BE->getRHS());
1521 return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
1522 case MCExpr::Target:
1528 bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) {
1529 Parser.Lex(); // Eat the % token.
1530 const AsmToken &Tok = Parser.getTok(); // Get next token, operation.
1531 if (Tok.isNot(AsmToken::Identifier))
1534 std::string Str = Tok.getIdentifier().str();
1536 Parser.Lex(); // Eat the identifier.
1537 // Now make an expression from the rest of the operand.
1538 const MCExpr *IdVal;
1541 if (getLexer().getKind() == AsmToken::LParen) {
1543 Parser.Lex(); // Eat the '(' token.
1544 if (getLexer().getKind() == AsmToken::Percent) {
1545 Parser.Lex(); // Eat the % token.
1546 const AsmToken &nextTok = Parser.getTok();
1547 if (nextTok.isNot(AsmToken::Identifier))
1550 Str += nextTok.getIdentifier();
1551 Parser.Lex(); // Eat the identifier.
1552 if (getLexer().getKind() != AsmToken::LParen)
1557 if (getParser().parseParenExpression(IdVal, EndLoc))
1560 while (getLexer().getKind() == AsmToken::RParen)
1561 Parser.Lex(); // Eat the ')' token.
1564 return true; // Parenthesis must follow the relocation operand.
1566 Res = evaluateRelocExpr(IdVal, Str);
1570 bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1572 SmallVector<MCParsedAsmOperand *, 1> Operands;
1573 OperandMatchResultTy ResTy = ParseAnyRegister(Operands);
1574 if (ResTy == MatchOperand_Success) {
1575 assert(Operands.size() == 1);
1576 MipsOperand &Operand = *static_cast<MipsOperand *>(Operands.front());
1577 StartLoc = Operand.getStartLoc();
1578 EndLoc = Operand.getEndLoc();
1580 // AFAIK, we only support numeric registers and named GPR's in CFI
1582 // Don't worry about eating tokens before failing. Using an unrecognised
1583 // register is a parse error.
1584 if (Operand.isGPRAsmReg()) {
1585 // Resolve to GPR32 or GPR64 appropriately.
1586 RegNo = isGP64() ? Operand.getGPR64Reg() : Operand.getGPR32Reg();
1589 return (RegNo == (unsigned)-1);
1592 assert(Operands.size() == 0);
1593 return (RegNo == (unsigned)-1);
1596 bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) {
1600 while (getLexer().getKind() == AsmToken::LParen)
1603 switch (getLexer().getKind()) {
1606 case AsmToken::Identifier:
1607 case AsmToken::LParen:
1608 case AsmToken::Integer:
1609 case AsmToken::Minus:
1610 case AsmToken::Plus:
1612 Result = getParser().parseParenExpression(Res, S);
1614 Result = (getParser().parseExpression(Res));
1615 while (getLexer().getKind() == AsmToken::RParen)
1618 case AsmToken::Percent:
1619 Result = parseRelocOperand(Res);
1624 MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(
1625 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1626 DEBUG(dbgs() << "parseMemOperand\n");
1627 const MCExpr *IdVal = 0;
1629 bool isParenExpr = false;
1630 MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch;
1631 // First operand is the offset.
1632 S = Parser.getTok().getLoc();
1634 if (getLexer().getKind() == AsmToken::LParen) {
1639 if (getLexer().getKind() != AsmToken::Dollar) {
1640 if (parseMemOffset(IdVal, isParenExpr))
1641 return MatchOperand_ParseFail;
1643 const AsmToken &Tok = Parser.getTok(); // Get the next token.
1644 if (Tok.isNot(AsmToken::LParen)) {
1645 MipsOperand *Mnemonic = static_cast<MipsOperand *>(Operands[0]);
1646 if (Mnemonic->getToken() == "la") {
1648 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1649 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1650 return MatchOperand_Success;
1652 if (Tok.is(AsmToken::EndOfStatement)) {
1654 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1656 // Zero register assumed, add a memory operand with ZERO as its base.
1657 MipsOperand *Base = MipsOperand::CreateGPRReg(
1658 0, getContext().getRegisterInfo(), S, E, *this);
1659 Operands.push_back(MipsOperand::CreateMem(Base, IdVal, S, E, *this));
1660 return MatchOperand_Success;
1662 Error(Parser.getTok().getLoc(), "'(' expected");
1663 return MatchOperand_ParseFail;
1666 Parser.Lex(); // Eat the '(' token.
1669 Res = ParseAnyRegister(Operands);
1670 if (Res != MatchOperand_Success)
1673 if (Parser.getTok().isNot(AsmToken::RParen)) {
1674 Error(Parser.getTok().getLoc(), "')' expected");
1675 return MatchOperand_ParseFail;
1678 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1680 Parser.Lex(); // Eat the ')' token.
1683 IdVal = MCConstantExpr::Create(0, getContext());
1685 // Replace the register operand with the memory operand.
1686 MipsOperand *op = static_cast<MipsOperand *>(Operands.back());
1687 // Remove the register from the operands.
1688 Operands.pop_back();
1689 // Add the memory operand.
1690 if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(IdVal)) {
1692 if (IdVal->EvaluateAsAbsolute(Imm))
1693 IdVal = MCConstantExpr::Create(Imm, getContext());
1694 else if (BE->getLHS()->getKind() != MCExpr::SymbolRef)
1695 IdVal = MCBinaryExpr::Create(BE->getOpcode(), BE->getRHS(), BE->getLHS(),
1699 Operands.push_back(MipsOperand::CreateMem(op, IdVal, S, E, *this));
1700 return MatchOperand_Success;
1703 bool MipsAsmParser::searchSymbolAlias(
1704 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1706 MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier());
1708 SMLoc S = Parser.getTok().getLoc();
1710 if (Sym->isVariable())
1711 Expr = Sym->getVariableValue();
1714 if (Expr->getKind() == MCExpr::SymbolRef) {
1715 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
1716 const StringRef DefSymbol = Ref->getSymbol().getName();
1717 if (DefSymbol.startswith("$")) {
1718 OperandMatchResultTy ResTy =
1719 MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S);
1720 if (ResTy == MatchOperand_Success) {
1723 } else if (ResTy == MatchOperand_ParseFail)
1724 llvm_unreachable("Should never ParseFail");
1727 } else if (Expr->getKind() == MCExpr::Constant) {
1729 const MCConstantExpr *Const = static_cast<const MCConstantExpr *>(Expr);
1731 MipsOperand::CreateImm(Const, S, Parser.getTok().getLoc(), *this);
1732 Operands.push_back(op);
1739 MipsAsmParser::OperandMatchResultTy
1740 MipsAsmParser::MatchAnyRegisterNameWithoutDollar(
1741 SmallVectorImpl<MCParsedAsmOperand *> &Operands, StringRef Identifier,
1743 int Index = matchCPURegisterName(Identifier);
1745 Operands.push_back(MipsOperand::CreateGPRReg(
1746 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1747 return MatchOperand_Success;
1750 Index = matchFPURegisterName(Identifier);
1752 Operands.push_back(MipsOperand::CreateFGRReg(
1753 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1754 return MatchOperand_Success;
1757 Index = matchFCCRegisterName(Identifier);
1759 Operands.push_back(MipsOperand::CreateFCCReg(
1760 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1761 return MatchOperand_Success;
1764 Index = matchACRegisterName(Identifier);
1766 Operands.push_back(MipsOperand::CreateACCReg(
1767 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1768 return MatchOperand_Success;
1771 Index = matchMSA128RegisterName(Identifier);
1773 Operands.push_back(MipsOperand::CreateMSA128Reg(
1774 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1775 return MatchOperand_Success;
1778 Index = matchMSA128CtrlRegisterName(Identifier);
1780 Operands.push_back(MipsOperand::CreateMSACtrlReg(
1781 Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this));
1782 return MatchOperand_Success;
1785 return MatchOperand_NoMatch;
1788 MipsAsmParser::OperandMatchResultTy
1789 MipsAsmParser::MatchAnyRegisterWithoutDollar(
1790 SmallVectorImpl<MCParsedAsmOperand *> &Operands, SMLoc S) {
1791 auto Token = Parser.getLexer().peekTok(false);
1793 if (Token.is(AsmToken::Identifier)) {
1794 DEBUG(dbgs() << ".. identifier\n");
1795 StringRef Identifier = Token.getIdentifier();
1796 OperandMatchResultTy ResTy =
1797 MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S);
1799 } else if (Token.is(AsmToken::Integer)) {
1800 DEBUG(dbgs() << ".. integer\n");
1801 Operands.push_back(MipsOperand::CreateNumericReg(
1802 Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(),
1804 return MatchOperand_Success;
1807 DEBUG(dbgs() << Parser.getTok().getKind() << "\n");
1809 return MatchOperand_NoMatch;
1812 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseAnyRegister(
1813 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1814 DEBUG(dbgs() << "ParseAnyRegister\n");
1816 auto Token = Parser.getTok();
1818 SMLoc S = Token.getLoc();
1820 if (Token.isNot(AsmToken::Dollar)) {
1821 DEBUG(dbgs() << ".. !$ -> try sym aliasing\n");
1822 if (Token.is(AsmToken::Identifier)) {
1823 if (searchSymbolAlias(Operands))
1824 return MatchOperand_Success;
1826 DEBUG(dbgs() << ".. !symalias -> NoMatch\n");
1827 return MatchOperand_NoMatch;
1829 DEBUG(dbgs() << ".. $\n");
1831 OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S);
1832 if (ResTy == MatchOperand_Success) {
1834 Parser.Lex(); // identifier
1839 MipsAsmParser::OperandMatchResultTy
1840 MipsAsmParser::ParseImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1841 switch (getLexer().getKind()) {
1843 return MatchOperand_NoMatch;
1844 case AsmToken::LParen:
1845 case AsmToken::Minus:
1846 case AsmToken::Plus:
1847 case AsmToken::Integer:
1848 case AsmToken::String:
1852 const MCExpr *IdVal;
1853 SMLoc S = Parser.getTok().getLoc();
1854 if (getParser().parseExpression(IdVal))
1855 return MatchOperand_ParseFail;
1857 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1858 Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this));
1859 return MatchOperand_Success;
1862 MipsAsmParser::OperandMatchResultTy MipsAsmParser::ParseJumpTarget(
1863 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1864 DEBUG(dbgs() << "ParseJumpTarget\n");
1866 SMLoc S = getLexer().getLoc();
1868 // Integers and expressions are acceptable
1869 OperandMatchResultTy ResTy = ParseImm(Operands);
1870 if (ResTy != MatchOperand_NoMatch)
1873 // Registers are a valid target and have priority over symbols.
1874 ResTy = ParseAnyRegister(Operands);
1875 if (ResTy != MatchOperand_NoMatch)
1878 const MCExpr *Expr = nullptr;
1879 if (Parser.parseExpression(Expr)) {
1880 // We have no way of knowing if a symbol was consumed so we must ParseFail
1881 return MatchOperand_ParseFail;
1884 MipsOperand::CreateImm(Expr, S, getLexer().getLoc(), *this));
1885 return MatchOperand_Success;
1888 MipsAsmParser::OperandMatchResultTy
1889 MipsAsmParser::parseInvNum(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1890 const MCExpr *IdVal;
1891 // If the first token is '$' we may have register operand.
1892 if (Parser.getTok().is(AsmToken::Dollar))
1893 return MatchOperand_NoMatch;
1894 SMLoc S = Parser.getTok().getLoc();
1895 if (getParser().parseExpression(IdVal))
1896 return MatchOperand_ParseFail;
1897 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
1898 assert(MCE && "Unexpected MCExpr type.");
1899 int64_t Val = MCE->getValue();
1900 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1901 Operands.push_back(MipsOperand::CreateImm(
1902 MCConstantExpr::Create(0 - Val, getContext()), S, E, *this));
1903 return MatchOperand_Success;
1906 MipsAsmParser::OperandMatchResultTy
1907 MipsAsmParser::ParseLSAImm(SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1908 switch (getLexer().getKind()) {
1910 return MatchOperand_NoMatch;
1911 case AsmToken::LParen:
1912 case AsmToken::Plus:
1913 case AsmToken::Minus:
1914 case AsmToken::Integer:
1919 SMLoc S = Parser.getTok().getLoc();
1921 if (getParser().parseExpression(Expr))
1922 return MatchOperand_ParseFail;
1925 if (!Expr->EvaluateAsAbsolute(Val)) {
1926 Error(S, "expected immediate value");
1927 return MatchOperand_ParseFail;
1930 // The LSA instruction allows a 2-bit unsigned immediate. For this reason
1931 // and because the CPU always adds one to the immediate field, the allowed
1932 // range becomes 1..4. We'll only check the range here and will deal
1933 // with the addition/subtraction when actually decoding/encoding
1935 if (Val < 1 || Val > 4) {
1936 Error(S, "immediate not in range (1..4)");
1937 return MatchOperand_ParseFail;
1941 MipsOperand::CreateImm(Expr, S, Parser.getTok().getLoc(), *this));
1942 return MatchOperand_Success;
1945 MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) {
1947 MCSymbolRefExpr::VariantKind VK =
1948 StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
1949 .Case("hi", MCSymbolRefExpr::VK_Mips_ABS_HI)
1950 .Case("lo", MCSymbolRefExpr::VK_Mips_ABS_LO)
1951 .Case("gp_rel", MCSymbolRefExpr::VK_Mips_GPREL)
1952 .Case("call16", MCSymbolRefExpr::VK_Mips_GOT_CALL)
1953 .Case("got", MCSymbolRefExpr::VK_Mips_GOT)
1954 .Case("tlsgd", MCSymbolRefExpr::VK_Mips_TLSGD)
1955 .Case("tlsldm", MCSymbolRefExpr::VK_Mips_TLSLDM)
1956 .Case("dtprel_hi", MCSymbolRefExpr::VK_Mips_DTPREL_HI)
1957 .Case("dtprel_lo", MCSymbolRefExpr::VK_Mips_DTPREL_LO)
1958 .Case("gottprel", MCSymbolRefExpr::VK_Mips_GOTTPREL)
1959 .Case("tprel_hi", MCSymbolRefExpr::VK_Mips_TPREL_HI)
1960 .Case("tprel_lo", MCSymbolRefExpr::VK_Mips_TPREL_LO)
1961 .Case("got_disp", MCSymbolRefExpr::VK_Mips_GOT_DISP)
1962 .Case("got_page", MCSymbolRefExpr::VK_Mips_GOT_PAGE)
1963 .Case("got_ofst", MCSymbolRefExpr::VK_Mips_GOT_OFST)
1964 .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_HI)
1965 .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Mips_GPOFF_LO)
1966 .Case("got_hi", MCSymbolRefExpr::VK_Mips_GOT_HI16)
1967 .Case("got_lo", MCSymbolRefExpr::VK_Mips_GOT_LO16)
1968 .Case("call_hi", MCSymbolRefExpr::VK_Mips_CALL_HI16)
1969 .Case("call_lo", MCSymbolRefExpr::VK_Mips_CALL_LO16)
1970 .Case("higher", MCSymbolRefExpr::VK_Mips_HIGHER)
1971 .Case("highest", MCSymbolRefExpr::VK_Mips_HIGHEST)
1972 .Default(MCSymbolRefExpr::VK_None);
1974 assert (VK != MCSymbolRefExpr::VK_None);
1979 /// Sometimes (i.e. load/stores) the operand may be followed immediately by
1981 /// ::= '(', register, ')'
1982 /// handle it before we iterate so we don't get tripped up by the lack of
1984 bool MipsAsmParser::ParseParenSuffix(
1985 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1986 if (getLexer().is(AsmToken::LParen)) {
1988 MipsOperand::CreateToken("(", getLexer().getLoc(), *this));
1990 if (ParseOperand(Operands, Name)) {
1991 SMLoc Loc = getLexer().getLoc();
1992 Parser.eatToEndOfStatement();
1993 return Error(Loc, "unexpected token in argument list");
1995 if (Parser.getTok().isNot(AsmToken::RParen)) {
1996 SMLoc Loc = getLexer().getLoc();
1997 Parser.eatToEndOfStatement();
1998 return Error(Loc, "unexpected token, expected ')'");
2001 MipsOperand::CreateToken(")", getLexer().getLoc(), *this));
2007 /// Sometimes (i.e. in MSA) the operand may be followed immediately by
2008 /// either one of these.
2009 /// ::= '[', register, ']'
2010 /// ::= '[', integer, ']'
2011 /// handle it before we iterate so we don't get tripped up by the lack of
2013 bool MipsAsmParser::ParseBracketSuffix(
2014 StringRef Name, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2015 if (getLexer().is(AsmToken::LBrac)) {
2017 MipsOperand::CreateToken("[", getLexer().getLoc(), *this));
2019 if (ParseOperand(Operands, Name)) {
2020 SMLoc Loc = getLexer().getLoc();
2021 Parser.eatToEndOfStatement();
2022 return Error(Loc, "unexpected token in argument list");
2024 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2025 SMLoc Loc = getLexer().getLoc();
2026 Parser.eatToEndOfStatement();
2027 return Error(Loc, "unexpected token, expected ']'");
2030 MipsOperand::CreateToken("]", getLexer().getLoc(), *this));
2036 bool MipsAsmParser::ParseInstruction(
2037 ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
2038 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
2039 DEBUG(dbgs() << "ParseInstruction\n");
2040 // Check if we have valid mnemonic
2041 if (!mnemonicIsValid(Name, 0)) {
2042 Parser.eatToEndOfStatement();
2043 return Error(NameLoc, "Unknown instruction");
2045 // First operand in MCInst is instruction mnemonic.
2046 Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this));
2048 // Read the remaining operands.
2049 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2050 // Read the first operand.
2051 if (ParseOperand(Operands, Name)) {
2052 SMLoc Loc = getLexer().getLoc();
2053 Parser.eatToEndOfStatement();
2054 return Error(Loc, "unexpected token in argument list");
2056 if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands))
2058 // AFAIK, parenthesis suffixes are never on the first operand
2060 while (getLexer().is(AsmToken::Comma)) {
2061 Parser.Lex(); // Eat the comma.
2062 // Parse and remember the operand.
2063 if (ParseOperand(Operands, Name)) {
2064 SMLoc Loc = getLexer().getLoc();
2065 Parser.eatToEndOfStatement();
2066 return Error(Loc, "unexpected token in argument list");
2068 // Parse bracket and parenthesis suffixes before we iterate
2069 if (getLexer().is(AsmToken::LBrac)) {
2070 if (ParseBracketSuffix(Name, Operands))
2072 } else if (getLexer().is(AsmToken::LParen) &&
2073 ParseParenSuffix(Name, Operands))
2077 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2078 SMLoc Loc = getLexer().getLoc();
2079 Parser.eatToEndOfStatement();
2080 return Error(Loc, "unexpected token in argument list");
2082 Parser.Lex(); // Consume the EndOfStatement.
2086 bool MipsAsmParser::reportParseError(StringRef ErrorMsg) {
2087 SMLoc Loc = getLexer().getLoc();
2088 Parser.eatToEndOfStatement();
2089 return Error(Loc, ErrorMsg);
2092 bool MipsAsmParser::parseSetNoAtDirective() {
2093 // Line should look like: ".set noat".
2095 Options.setATReg(0);
2098 // If this is not the end of the statement, report an error.
2099 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2100 reportParseError("unexpected token in statement");
2103 Parser.Lex(); // Consume the EndOfStatement.
2107 bool MipsAsmParser::parseSetAtDirective() {
2108 // Line can be .set at - defaults to $1
2112 if (getLexer().is(AsmToken::EndOfStatement)) {
2113 Options.setATReg(1);
2114 Parser.Lex(); // Consume the EndOfStatement.
2116 } else if (getLexer().is(AsmToken::Equal)) {
2117 getParser().Lex(); // Eat the '='.
2118 if (getLexer().isNot(AsmToken::Dollar)) {
2119 reportParseError("unexpected token in statement");
2122 Parser.Lex(); // Eat the '$'.
2123 const AsmToken &Reg = Parser.getTok();
2124 if (Reg.is(AsmToken::Identifier)) {
2125 AtRegNo = matchCPURegisterName(Reg.getIdentifier());
2126 } else if (Reg.is(AsmToken::Integer)) {
2127 AtRegNo = Reg.getIntVal();
2129 reportParseError("unexpected token in statement");
2133 if (AtRegNo < 0 || AtRegNo > 31) {
2134 reportParseError("unexpected token in statement");
2138 if (!Options.setATReg(AtRegNo)) {
2139 reportParseError("unexpected token in statement");
2142 getParser().Lex(); // Eat the register.
2144 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2145 reportParseError("unexpected token in statement");
2148 Parser.Lex(); // Consume the EndOfStatement.
2151 reportParseError("unexpected token in statement");
2156 bool MipsAsmParser::parseSetReorderDirective() {
2158 // If this is not the end of the statement, report an error.
2159 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2160 reportParseError("unexpected token in statement");
2163 Options.setReorder();
2164 getTargetStreamer().emitDirectiveSetReorder();
2165 Parser.Lex(); // Consume the EndOfStatement.
2169 bool MipsAsmParser::parseSetNoReorderDirective() {
2171 // If this is not the end of the statement, report an error.
2172 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2173 reportParseError("unexpected token in statement");
2176 Options.setNoreorder();
2177 getTargetStreamer().emitDirectiveSetNoReorder();
2178 Parser.Lex(); // Consume the EndOfStatement.
2182 bool MipsAsmParser::parseSetMacroDirective() {
2184 // If this is not the end of the statement, report an error.
2185 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2186 reportParseError("unexpected token in statement");
2190 Parser.Lex(); // Consume the EndOfStatement.
2194 bool MipsAsmParser::parseSetNoMacroDirective() {
2196 // If this is not the end of the statement, report an error.
2197 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2198 reportParseError("`noreorder' must be set before `nomacro'");
2201 if (Options.isReorder()) {
2202 reportParseError("`noreorder' must be set before `nomacro'");
2205 Options.setNomacro();
2206 Parser.Lex(); // Consume the EndOfStatement.
2210 bool MipsAsmParser::parseSetNoMips16Directive() {
2212 // If this is not the end of the statement, report an error.
2213 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2214 reportParseError("unexpected token in statement");
2217 // For now do nothing.
2218 Parser.Lex(); // Consume the EndOfStatement.
2222 bool MipsAsmParser::parseSetAssignment() {
2224 const MCExpr *Value;
2226 if (Parser.parseIdentifier(Name))
2227 reportParseError("expected identifier after .set");
2229 if (getLexer().isNot(AsmToken::Comma))
2230 return reportParseError("unexpected token in .set directive");
2233 if (Parser.parseExpression(Value))
2234 return reportParseError("expected valid expression after comma");
2236 // Check if the Name already exists as a symbol.
2237 MCSymbol *Sym = getContext().LookupSymbol(Name);
2239 return reportParseError("symbol already defined");
2240 Sym = getContext().GetOrCreateSymbol(Name);
2241 Sym->setVariableValue(Value);
2246 bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
2248 if (getLexer().isNot(AsmToken::EndOfStatement))
2249 return reportParseError("unexpected token in .set directive");
2252 default: llvm_unreachable("Unimplemented feature");
2253 case Mips::FeatureDSP:
2254 setFeatureBits(Mips::FeatureDSP, "dsp");
2255 getTargetStreamer().emitDirectiveSetDsp();
2257 case Mips::FeatureMicroMips:
2258 getTargetStreamer().emitDirectiveSetMicroMips();
2260 case Mips::FeatureMips16:
2261 getTargetStreamer().emitDirectiveSetMips16();
2263 case Mips::FeatureMips32r2:
2264 setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
2265 getTargetStreamer().emitDirectiveSetMips32R2();
2267 case Mips::FeatureMips64:
2268 setFeatureBits(Mips::FeatureMips64, "mips64");
2269 getTargetStreamer().emitDirectiveSetMips64();
2271 case Mips::FeatureMips64r2:
2272 setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
2273 getTargetStreamer().emitDirectiveSetMips64R2();
2279 bool MipsAsmParser::parseRegister(unsigned &RegNum) {
2280 if (!getLexer().is(AsmToken::Dollar))
2285 const AsmToken &Reg = Parser.getTok();
2286 if (Reg.is(AsmToken::Identifier)) {
2287 RegNum = matchCPURegisterName(Reg.getIdentifier());
2288 } else if (Reg.is(AsmToken::Integer)) {
2289 RegNum = Reg.getIntVal();
2298 bool MipsAsmParser::eatComma(StringRef ErrorStr) {
2299 if (getLexer().isNot(AsmToken::Comma)) {
2300 SMLoc Loc = getLexer().getLoc();
2301 Parser.eatToEndOfStatement();
2302 return Error(Loc, ErrorStr);
2305 Parser.Lex(); // Eat the comma.
2309 bool MipsAsmParser::parseDirectiveCPSetup() {
2312 bool SaveIsReg = true;
2314 if (!parseRegister(FuncReg))
2315 return reportParseError("expected register containing function address");
2316 FuncReg = getGPR(FuncReg);
2318 if (!eatComma("expected comma parsing directive"))
2321 if (!parseRegister(Save)) {
2322 const AsmToken &Tok = Parser.getTok();
2323 if (Tok.is(AsmToken::Integer)) {
2324 Save = Tok.getIntVal();
2328 return reportParseError("expected save register or stack offset");
2330 Save = getGPR(Save);
2332 if (!eatComma("expected comma parsing directive"))
2336 if (Parser.parseIdentifier(Name))
2337 reportParseError("expected identifier");
2338 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2339 unsigned GPReg = getGPR(matchCPURegisterName("gp"));
2341 // FIXME: The code below this point should be in the TargetStreamers.
2342 // Only N32 and N64 emit anything for .cpsetup
2343 // FIXME: We should only emit something for PIC mode too.
2344 if (!isN32() && !isN64())
2347 MCStreamer &TS = getStreamer();
2349 // Either store the old $gp in a register or on the stack
2351 // move $save, $gpreg
2352 Inst.setOpcode(Mips::DADDu);
2353 Inst.addOperand(MCOperand::CreateReg(Save));
2354 Inst.addOperand(MCOperand::CreateReg(GPReg));
2355 Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
2357 // sd $gpreg, offset($sp)
2358 Inst.setOpcode(Mips::SD);
2359 Inst.addOperand(MCOperand::CreateReg(GPReg));
2360 Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
2361 Inst.addOperand(MCOperand::CreateImm(Save));
2363 TS.EmitInstruction(Inst, STI);
2366 const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
2367 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI,
2369 const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
2370 Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO,
2372 // lui $gp, %hi(%neg(%gp_rel(funcSym)))
2373 Inst.setOpcode(Mips::LUi);
2374 Inst.addOperand(MCOperand::CreateReg(GPReg));
2375 Inst.addOperand(MCOperand::CreateExpr(HiExpr));
2376 TS.EmitInstruction(Inst, STI);
2379 // addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
2380 Inst.setOpcode(Mips::ADDiu);
2381 Inst.addOperand(MCOperand::CreateReg(GPReg));
2382 Inst.addOperand(MCOperand::CreateReg(GPReg));
2383 Inst.addOperand(MCOperand::CreateExpr(LoExpr));
2384 TS.EmitInstruction(Inst, STI);
2387 // daddu $gp, $gp, $funcreg
2388 Inst.setOpcode(Mips::DADDu);
2389 Inst.addOperand(MCOperand::CreateReg(GPReg));
2390 Inst.addOperand(MCOperand::CreateReg(GPReg));
2391 Inst.addOperand(MCOperand::CreateReg(FuncReg));
2392 TS.EmitInstruction(Inst, STI);
2396 bool MipsAsmParser::parseDirectiveSet() {
2398 // Get the next token.
2399 const AsmToken &Tok = Parser.getTok();
2401 if (Tok.getString() == "noat") {
2402 return parseSetNoAtDirective();
2403 } else if (Tok.getString() == "at") {
2404 return parseSetAtDirective();
2405 } else if (Tok.getString() == "reorder") {
2406 return parseSetReorderDirective();
2407 } else if (Tok.getString() == "noreorder") {
2408 return parseSetNoReorderDirective();
2409 } else if (Tok.getString() == "macro") {
2410 return parseSetMacroDirective();
2411 } else if (Tok.getString() == "nomacro") {
2412 return parseSetNoMacroDirective();
2413 } else if (Tok.getString() == "mips16") {
2414 return parseSetFeature(Mips::FeatureMips16);
2415 } else if (Tok.getString() == "nomips16") {
2416 return parseSetNoMips16Directive();
2417 } else if (Tok.getString() == "nomicromips") {
2418 getTargetStreamer().emitDirectiveSetNoMicroMips();
2419 Parser.eatToEndOfStatement();
2421 } else if (Tok.getString() == "micromips") {
2422 return parseSetFeature(Mips::FeatureMicroMips);
2423 } else if (Tok.getString() == "mips32r2") {
2424 return parseSetFeature(Mips::FeatureMips32r2);
2425 } else if (Tok.getString() == "mips64") {
2426 return parseSetFeature(Mips::FeatureMips64);
2427 } else if (Tok.getString() == "mips64r2") {
2428 return parseSetFeature(Mips::FeatureMips64r2);
2429 } else if (Tok.getString() == "dsp") {
2430 return parseSetFeature(Mips::FeatureDSP);
2432 // It is just an identifier, look for an assignment.
2433 parseSetAssignment();
2440 /// parseDataDirective
2441 /// ::= .word [ expression (, expression)* ]
2442 bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) {
2443 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2445 const MCExpr *Value;
2446 if (getParser().parseExpression(Value))
2449 getParser().getStreamer().EmitValue(Value, Size);
2451 if (getLexer().is(AsmToken::EndOfStatement))
2454 // FIXME: Improve diagnostic.
2455 if (getLexer().isNot(AsmToken::Comma))
2456 return Error(L, "unexpected token in directive");
2465 /// parseDirectiveGpWord
2466 /// ::= .gpword local_sym
2467 bool MipsAsmParser::parseDirectiveGpWord() {
2468 const MCExpr *Value;
2469 // EmitGPRel32Value requires an expression, so we are using base class
2470 // method to evaluate the expression.
2471 if (getParser().parseExpression(Value))
2473 getParser().getStreamer().EmitGPRel32Value(Value);
2475 if (getLexer().isNot(AsmToken::EndOfStatement))
2476 return Error(getLexer().getLoc(), "unexpected token in directive");
2477 Parser.Lex(); // Eat EndOfStatement token.
2481 /// parseDirectiveGpDWord
2482 /// ::= .gpdword local_sym
2483 bool MipsAsmParser::parseDirectiveGpDWord() {
2484 const MCExpr *Value;
2485 // EmitGPRel64Value requires an expression, so we are using base class
2486 // method to evaluate the expression.
2487 if (getParser().parseExpression(Value))
2489 getParser().getStreamer().EmitGPRel64Value(Value);
2491 if (getLexer().isNot(AsmToken::EndOfStatement))
2492 return Error(getLexer().getLoc(), "unexpected token in directive");
2493 Parser.Lex(); // Eat EndOfStatement token.
2497 bool MipsAsmParser::parseDirectiveOption() {
2498 // Get the option token.
2499 AsmToken Tok = Parser.getTok();
2500 // At the moment only identifiers are supported.
2501 if (Tok.isNot(AsmToken::Identifier)) {
2502 Error(Parser.getTok().getLoc(), "unexpected token in .option directive");
2503 Parser.eatToEndOfStatement();
2507 StringRef Option = Tok.getIdentifier();
2509 if (Option == "pic0") {
2510 getTargetStreamer().emitDirectiveOptionPic0();
2512 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2513 Error(Parser.getTok().getLoc(),
2514 "unexpected token in .option pic0 directive");
2515 Parser.eatToEndOfStatement();
2520 if (Option == "pic2") {
2521 getTargetStreamer().emitDirectiveOptionPic2();
2523 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2524 Error(Parser.getTok().getLoc(),
2525 "unexpected token in .option pic2 directive");
2526 Parser.eatToEndOfStatement();
2532 Warning(Parser.getTok().getLoc(), "unknown option in .option directive");
2533 Parser.eatToEndOfStatement();
2537 bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
2538 StringRef IDVal = DirectiveID.getString();
2540 if (IDVal == ".dword") {
2541 parseDataDirective(8, DirectiveID.getLoc());
2545 if (IDVal == ".ent") {
2546 // Ignore this directive for now.
2551 if (IDVal == ".end") {
2552 // Ignore this directive for now.
2557 if (IDVal == ".frame") {
2558 // Ignore this directive for now.
2559 Parser.eatToEndOfStatement();
2563 if (IDVal == ".set") {
2564 return parseDirectiveSet();
2567 if (IDVal == ".fmask") {
2568 // Ignore this directive for now.
2569 Parser.eatToEndOfStatement();
2573 if (IDVal == ".mask") {
2574 // Ignore this directive for now.
2575 Parser.eatToEndOfStatement();
2579 if (IDVal == ".gpword") {
2580 parseDirectiveGpWord();
2584 if (IDVal == ".gpdword") {
2585 parseDirectiveGpDWord();
2589 if (IDVal == ".word") {
2590 parseDataDirective(4, DirectiveID.getLoc());
2594 if (IDVal == ".option")
2595 return parseDirectiveOption();
2597 if (IDVal == ".abicalls") {
2598 getTargetStreamer().emitDirectiveAbiCalls();
2599 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
2600 Error(Parser.getTok().getLoc(), "unexpected token in directive");
2602 Parser.eatToEndOfStatement();
2607 if (IDVal == ".cpsetup")
2608 return parseDirectiveCPSetup();
2613 extern "C" void LLVMInitializeMipsAsmParser() {
2614 RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget);
2615 RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget);
2616 RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target);
2617 RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget);
2620 #define GET_REGISTER_MATCHER
2621 #define GET_MATCHER_IMPLEMENTATION
2622 #include "MipsGenAsmMatcher.inc"