1 //===- MSP430RegisterInfo.td - MSP430 Register defs ----------*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the MSP430 register file
12 //===----------------------------------------------------------------------===//
14 class MSP430Reg<bits<4> num, string n> : Register<n> {
15 field bits<4> Num = num;
16 let Namespace = "MSP430";
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 def PC : MSP430Reg<0, "PC">;
24 def SP : MSP430Reg<1, "SP">;
25 def SR : MSP430Reg<2, "SR">;
26 def CG : MSP430Reg<3, "CG">;
27 def R4 : MSP430Reg<4, "R4">;
28 def R5 : MSP430Reg<5, "R5">;
29 def R6 : MSP430Reg<6, "R6">;
30 def R7 : MSP430Reg<7, "R7">;
31 def R8 : MSP430Reg<8, "R8">;
32 def R9 : MSP430Reg<9, "R9">;
33 def R10 : MSP430Reg<10, "R10">;
34 def R11 : MSP430Reg<11, "R11">;
35 def R12 : MSP430Reg<12, "R12">;
36 def R13 : MSP430Reg<13, "R13">;
37 def R14 : MSP430Reg<14, "R14">;
38 def R15 : MSP430Reg<15, "R15">;
40 def MSP430Regs : RegisterClass<"MSP430", [i16], 16,
42 [R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15,
43 // Volatile, but not allocable
47 iterator allocation_order_end(const MachineFunction &MF) const;
50 MSP430RegsClass::iterator
51 MSP430RegsClass::allocation_order_end(const MachineFunction &MF) const {
52 // The last 4 registers on the list above are reserved