1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/VectorExtras.h"
41 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
42 TargetLowering(tm, new TargetLoweringObjectFileELF()),
43 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
45 // Set up the register classes.
46 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
47 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
49 // Compute derived properties from the register classes
50 computeRegisterProperties();
52 // Provide all sorts of operation actions
54 // Division is expensive
55 setIntDivIsCheap(false);
57 // Even if we have only 1 bit shift here, we can perform
58 // shifts of the whole bitwidth 1 bit per step.
59 setShiftAmountType(MVT::i8);
61 setStackPointerRegisterToSaveRestore(MSP430::SPW);
62 setBooleanContents(ZeroOrOneBooleanContent);
63 setSchedulingPreference(SchedulingForLatency);
65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
66 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
71 // We don't have any truncstores
72 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
74 setOperationAction(ISD::SRA, MVT::i8, Custom);
75 setOperationAction(ISD::SHL, MVT::i8, Custom);
76 setOperationAction(ISD::SRL, MVT::i8, Custom);
77 setOperationAction(ISD::SRA, MVT::i16, Custom);
78 setOperationAction(ISD::SHL, MVT::i16, Custom);
79 setOperationAction(ISD::SRL, MVT::i16, Custom);
80 setOperationAction(ISD::ROTL, MVT::i8, Expand);
81 setOperationAction(ISD::ROTR, MVT::i8, Expand);
82 setOperationAction(ISD::ROTL, MVT::i16, Expand);
83 setOperationAction(ISD::ROTR, MVT::i16, Expand);
84 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
85 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRIND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
90 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
91 setOperationAction(ISD::SETCC, MVT::i8, Expand);
92 setOperationAction(ISD::SETCC, MVT::i16, Expand);
93 setOperationAction(ISD::SELECT, MVT::i8, Expand);
94 setOperationAction(ISD::SELECT, MVT::i16, Expand);
95 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
96 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
97 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
99 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
100 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
101 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
102 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
103 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
104 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
106 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
107 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
108 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
109 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
110 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
111 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
113 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
115 // FIXME: Implement efficiently multiplication by a constant
116 setOperationAction(ISD::MUL, MVT::i16, Expand);
117 setOperationAction(ISD::MULHS, MVT::i16, Expand);
118 setOperationAction(ISD::MULHU, MVT::i16, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
120 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
122 setOperationAction(ISD::UDIV, MVT::i16, Expand);
123 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
124 setOperationAction(ISD::UREM, MVT::i16, Expand);
125 setOperationAction(ISD::SDIV, MVT::i16, Expand);
126 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
127 setOperationAction(ISD::SREM, MVT::i16, Expand);
130 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
131 switch (Op.getOpcode()) {
132 case ISD::SHL: // FALLTHROUGH
134 case ISD::SRA: return LowerShifts(Op, DAG);
135 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
136 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
137 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
138 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
139 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
141 llvm_unreachable("unimplemented operand");
146 /// getFunctionAlignment - Return the Log2 alignment of this function.
147 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
148 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
151 //===----------------------------------------------------------------------===//
152 // Calling Convention Implementation
153 //===----------------------------------------------------------------------===//
155 #include "MSP430GenCallingConv.inc"
158 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
161 const SmallVectorImpl<ISD::InputArg>
165 SmallVectorImpl<SDValue> &InVals) {
169 llvm_unreachable("Unsupported calling convention");
171 case CallingConv::Fast:
172 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
177 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
178 unsigned CallConv, bool isVarArg,
180 const SmallVectorImpl<ISD::OutputArg> &Outs,
181 const SmallVectorImpl<ISD::InputArg> &Ins,
182 DebugLoc dl, SelectionDAG &DAG,
183 SmallVectorImpl<SDValue> &InVals) {
187 llvm_unreachable("Unsupported calling convention");
188 case CallingConv::Fast:
190 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
191 Outs, Ins, dl, DAG, InVals);
195 /// LowerCCCArguments - transform physical registers into virtual registers and
196 /// generate load operations for arguments places on the stack.
197 // FIXME: struct return stuff
200 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
203 const SmallVectorImpl<ISD::InputArg>
207 SmallVectorImpl<SDValue> &InVals) {
208 MachineFunction &MF = DAG.getMachineFunction();
209 MachineFrameInfo *MFI = MF.getFrameInfo();
210 MachineRegisterInfo &RegInfo = MF.getRegInfo();
212 // Assign locations to all of the incoming arguments.
213 SmallVector<CCValAssign, 16> ArgLocs;
214 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
215 ArgLocs, *DAG.getContext());
216 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
218 assert(!isVarArg && "Varargs not supported yet");
220 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
221 CCValAssign &VA = ArgLocs[i];
223 // Arguments passed in registers
224 EVT RegVT = VA.getLocVT();
225 switch (RegVT.getSimpleVT().SimpleTy) {
229 errs() << "LowerFormalArguments Unhandled argument type: "
230 << RegVT.getSimpleVT().SimpleTy << "\n";
236 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
237 RegInfo.addLiveIn(VA.getLocReg(), VReg);
238 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
240 // If this is an 8-bit value, it is really passed promoted to 16
241 // bits. Insert an assert[sz]ext to capture this, then truncate to the
243 if (VA.getLocInfo() == CCValAssign::SExt)
244 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
245 DAG.getValueType(VA.getValVT()));
246 else if (VA.getLocInfo() == CCValAssign::ZExt)
247 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
248 DAG.getValueType(VA.getValVT()));
250 if (VA.getLocInfo() != CCValAssign::Full)
251 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
253 InVals.push_back(ArgValue);
257 assert(VA.isMemLoc());
258 // Load the argument to a virtual register
259 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
261 errs() << "LowerFormalArguments Unhandled argument type: "
262 << VA.getLocVT().getSimpleVT().SimpleTy
265 // Create the frame index object for this incoming parameter...
266 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
268 // Create the SelectionDAG nodes corresponding to a load
269 //from this parameter
270 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
271 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
272 PseudoSourceValue::getFixedStack(FI), 0));
280 MSP430TargetLowering::LowerReturn(SDValue Chain,
281 unsigned CallConv, bool isVarArg,
282 const SmallVectorImpl<ISD::OutputArg> &Outs,
283 DebugLoc dl, SelectionDAG &DAG) {
285 // CCValAssign - represent the assignment of the return value to a location
286 SmallVector<CCValAssign, 16> RVLocs;
288 // CCState - Info about the registers and stack slot.
289 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
290 RVLocs, *DAG.getContext());
292 // Analize return values.
293 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
295 // If this is the first return lowered for this function, add the regs to the
296 // liveout set for the function.
297 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
298 for (unsigned i = 0; i != RVLocs.size(); ++i)
299 if (RVLocs[i].isRegLoc())
300 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
305 // Copy the result values into the output registers.
306 for (unsigned i = 0; i != RVLocs.size(); ++i) {
307 CCValAssign &VA = RVLocs[i];
308 assert(VA.isRegLoc() && "Can only return in registers!");
310 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
313 // Guarantee that all emitted copies are stuck together,
314 // avoiding something bad.
315 Flag = Chain.getValue(1);
319 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
322 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
325 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
326 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
329 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
330 unsigned CallConv, bool isVarArg,
332 const SmallVectorImpl<ISD::OutputArg>
334 const SmallVectorImpl<ISD::InputArg> &Ins,
335 DebugLoc dl, SelectionDAG &DAG,
336 SmallVectorImpl<SDValue> &InVals) {
337 // Analyze operands of the call, assigning locations to each operand.
338 SmallVector<CCValAssign, 16> ArgLocs;
339 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
340 ArgLocs, *DAG.getContext());
342 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
344 // Get a count of how many bytes are to be pushed on the stack.
345 unsigned NumBytes = CCInfo.getNextStackOffset();
347 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
348 getPointerTy(), true));
350 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
351 SmallVector<SDValue, 12> MemOpChains;
354 // Walk the register/memloc assignments, inserting copies/loads.
355 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
356 CCValAssign &VA = ArgLocs[i];
358 SDValue Arg = Outs[i].Val;
360 // Promote the value if needed.
361 switch (VA.getLocInfo()) {
362 default: llvm_unreachable("Unknown loc info!");
363 case CCValAssign::Full: break;
364 case CCValAssign::SExt:
365 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
367 case CCValAssign::ZExt:
368 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
370 case CCValAssign::AExt:
371 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
375 // Arguments that can be passed on register must be kept at RegsToPass
378 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
380 assert(VA.isMemLoc());
382 if (StackPtr.getNode() == 0)
383 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
385 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
387 DAG.getIntPtrConstant(VA.getLocMemOffset()));
390 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
391 PseudoSourceValue::getStack(),
392 VA.getLocMemOffset()));
396 // Transform all store nodes into one single node because all store nodes are
397 // independent of each other.
398 if (!MemOpChains.empty())
399 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
400 &MemOpChains[0], MemOpChains.size());
402 // Build a sequence of copy-to-reg nodes chained together with token chain and
403 // flag operands which copy the outgoing args into registers. The InFlag in
404 // necessary since all emited instructions must be stuck together.
406 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
407 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
408 RegsToPass[i].second, InFlag);
409 InFlag = Chain.getValue(1);
412 // If the callee is a GlobalAddress node (quite common, every direct call is)
413 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
414 // Likewise ExternalSymbol -> TargetExternalSymbol.
415 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
416 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
417 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
418 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
420 // Returns a chain & a flag for retval copy to use.
421 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
422 SmallVector<SDValue, 8> Ops;
423 Ops.push_back(Chain);
424 Ops.push_back(Callee);
426 // Add argument registers to the end of the list so that they are
427 // known live into the call.
428 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
429 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
430 RegsToPass[i].second.getValueType()));
432 if (InFlag.getNode())
433 Ops.push_back(InFlag);
435 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
436 InFlag = Chain.getValue(1);
438 // Create the CALLSEQ_END node.
439 Chain = DAG.getCALLSEQ_END(Chain,
440 DAG.getConstant(NumBytes, getPointerTy(), true),
441 DAG.getConstant(0, getPointerTy(), true),
443 InFlag = Chain.getValue(1);
445 // Handle result values, copying them out of physregs into vregs that we
447 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
451 /// LowerCallResult - Lower the result values of a call into the
452 /// appropriate copies out of appropriate physical registers.
455 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
456 unsigned CallConv, bool isVarArg,
457 const SmallVectorImpl<ISD::InputArg> &Ins,
458 DebugLoc dl, SelectionDAG &DAG,
459 SmallVectorImpl<SDValue> &InVals) {
461 // Assign locations to each value returned by this call.
462 SmallVector<CCValAssign, 16> RVLocs;
463 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
464 RVLocs, *DAG.getContext());
466 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
468 // Copy all of the result registers out of their specified physreg.
469 for (unsigned i = 0; i != RVLocs.size(); ++i) {
470 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
471 RVLocs[i].getValVT(), InFlag).getValue(1);
472 InFlag = Chain.getValue(2);
473 InVals.push_back(Chain.getValue(0));
479 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
481 unsigned Opc = Op.getOpcode();
482 SDNode* N = Op.getNode();
483 EVT VT = Op.getValueType();
484 DebugLoc dl = N->getDebugLoc();
486 // We currently only lower shifts of constant argument.
487 if (!isa<ConstantSDNode>(N->getOperand(1)))
490 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
492 // Expand the stuff into sequence of shifts.
493 // FIXME: for some shift amounts this might be done better!
494 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
495 SDValue Victim = N->getOperand(0);
497 if (Opc == ISD::SRL && ShiftAmount) {
498 // Emit a special goodness here:
499 // srl A, 1 => clrc; rrc A
500 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
504 while (ShiftAmount--)
505 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
511 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
512 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
513 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
515 // Create the TargetGlobalAddress node, folding in the constant offset.
516 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
517 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
518 getPointerTy(), Result);
521 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
523 DebugLoc dl = Op.getDebugLoc();
524 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
525 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
527 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
530 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC,
532 DebugLoc dl, SelectionDAG &DAG) {
533 // FIXME: Handle bittests someday
534 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
536 // FIXME: Handle jump negative someday
537 TargetCC = MSP430::COND_INVALID;
539 default: llvm_unreachable("Invalid integer condition!");
541 TargetCC = MSP430::COND_E; // aka COND_Z
544 TargetCC = MSP430::COND_NE; // aka COND_NZ
547 std::swap(LHS, RHS); // FALLTHROUGH
549 TargetCC = MSP430::COND_HS; // aka COND_C
552 std::swap(LHS, RHS); // FALLTHROUGH
554 TargetCC = MSP430::COND_LO; // aka COND_NC
557 std::swap(LHS, RHS); // FALLTHROUGH
559 TargetCC = MSP430::COND_GE;
562 std::swap(LHS, RHS); // FALLTHROUGH
564 TargetCC = MSP430::COND_L;
568 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
572 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
573 SDValue Chain = Op.getOperand(0);
574 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
575 SDValue LHS = Op.getOperand(2);
576 SDValue RHS = Op.getOperand(3);
577 SDValue Dest = Op.getOperand(4);
578 DebugLoc dl = Op.getDebugLoc();
580 unsigned TargetCC = MSP430::COND_INVALID;
581 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
583 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
585 Dest, DAG.getConstant(TargetCC, MVT::i8),
589 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
590 SDValue LHS = Op.getOperand(0);
591 SDValue RHS = Op.getOperand(1);
592 SDValue TrueV = Op.getOperand(2);
593 SDValue FalseV = Op.getOperand(3);
594 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
595 DebugLoc dl = Op.getDebugLoc();
597 unsigned TargetCC = MSP430::COND_INVALID;
598 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
600 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
601 SmallVector<SDValue, 4> Ops;
602 Ops.push_back(TrueV);
603 Ops.push_back(FalseV);
604 Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
607 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
610 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
612 SDValue Val = Op.getOperand(0);
613 EVT VT = Op.getValueType();
614 DebugLoc dl = Op.getDebugLoc();
616 assert(VT == MVT::i16 && "Only support i16 for now!");
618 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
619 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
620 DAG.getValueType(Val.getValueType()));
623 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
625 default: return NULL;
626 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
627 case MSP430ISD::RRA: return "MSP430ISD::RRA";
628 case MSP430ISD::RLA: return "MSP430ISD::RLA";
629 case MSP430ISD::RRC: return "MSP430ISD::RRC";
630 case MSP430ISD::CALL: return "MSP430ISD::CALL";
631 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
632 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
633 case MSP430ISD::CMP: return "MSP430ISD::CMP";
634 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
638 //===----------------------------------------------------------------------===//
639 // Other Lowering Code
640 //===----------------------------------------------------------------------===//
643 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
644 MachineBasicBlock *BB) const {
645 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
646 DebugLoc dl = MI->getDebugLoc();
647 assert((MI->getOpcode() == MSP430::Select16 ||
648 MI->getOpcode() == MSP430::Select8) &&
649 "Unexpected instr type to insert");
651 // To "insert" a SELECT instruction, we actually have to insert the diamond
652 // control-flow pattern. The incoming instruction knows the destination vreg
653 // to set, the condition code register to branch on, the true/false values to
654 // select between, and a branch opcode to use.
655 const BasicBlock *LLVM_BB = BB->getBasicBlock();
656 MachineFunction::iterator I = BB;
664 // fallthrough --> copy0MBB
665 MachineBasicBlock *thisMBB = BB;
666 MachineFunction *F = BB->getParent();
667 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
668 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
669 BuildMI(BB, dl, TII.get(MSP430::JCC))
671 .addImm(MI->getOperand(3).getImm());
672 F->insert(I, copy0MBB);
673 F->insert(I, copy1MBB);
674 // Update machine-CFG edges by transferring all successors of the current
675 // block to the new block which will contain the Phi node for the select.
676 copy1MBB->transferSuccessors(BB);
677 // Next, add the true and fallthrough blocks as its successors.
678 BB->addSuccessor(copy0MBB);
679 BB->addSuccessor(copy1MBB);
683 // # fallthrough to copy1MBB
686 // Update machine-CFG edges
687 BB->addSuccessor(copy1MBB);
690 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
693 BuildMI(BB, dl, TII.get(MSP430::PHI),
694 MI->getOperand(0).getReg())
695 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
696 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
698 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.