1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the MSP430TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "msp430-lower"
16 #include "MSP430ISelLowering.h"
18 #include "MSP430TargetMachine.h"
19 #include "MSP430Subtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/VectorExtras.h"
41 MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
42 TargetLowering(tm, new TargetLoweringObjectFileELF()),
43 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
45 // Set up the register classes.
46 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
47 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
49 // Compute derived properties from the register classes
50 computeRegisterProperties();
52 // Provide all sorts of operation actions
54 // Division is expensive
55 setIntDivIsCheap(false);
57 // Even if we have only 1 bit shift here, we can perform
58 // shifts of the whole bitwidth 1 bit per step.
59 setShiftAmountType(MVT::i8);
61 setStackPointerRegisterToSaveRestore(MSP430::SPW);
62 setBooleanContents(ZeroOrOneBooleanContent);
63 setSchedulingPreference(SchedulingForLatency);
65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
66 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
67 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
71 // We don't have any truncstores
72 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
74 setOperationAction(ISD::SRA, MVT::i8, Custom);
75 setOperationAction(ISD::SHL, MVT::i8, Custom);
76 setOperationAction(ISD::SRL, MVT::i8, Custom);
77 setOperationAction(ISD::SRA, MVT::i16, Custom);
78 setOperationAction(ISD::SHL, MVT::i16, Custom);
79 setOperationAction(ISD::SRL, MVT::i16, Custom);
80 setOperationAction(ISD::ROTL, MVT::i8, Expand);
81 setOperationAction(ISD::ROTR, MVT::i8, Expand);
82 setOperationAction(ISD::ROTL, MVT::i16, Expand);
83 setOperationAction(ISD::ROTR, MVT::i16, Expand);
84 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
85 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
87 setOperationAction(ISD::BRIND, MVT::Other, Expand);
88 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
89 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
90 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
91 setOperationAction(ISD::SETCC, MVT::i8, Expand);
92 setOperationAction(ISD::SETCC, MVT::i16, Expand);
93 setOperationAction(ISD::SELECT, MVT::i8, Expand);
94 setOperationAction(ISD::SELECT, MVT::i16, Expand);
95 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
96 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
97 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
98 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
99 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
101 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
102 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
103 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
104 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
105 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
106 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
108 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
109 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
110 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
111 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
112 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
113 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
115 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
117 // FIXME: Implement efficiently multiplication by a constant
118 setOperationAction(ISD::MUL, MVT::i16, Expand);
119 setOperationAction(ISD::MULHS, MVT::i16, Expand);
120 setOperationAction(ISD::MULHU, MVT::i16, Expand);
121 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
122 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
124 setOperationAction(ISD::UDIV, MVT::i16, Expand);
125 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
126 setOperationAction(ISD::UREM, MVT::i16, Expand);
127 setOperationAction(ISD::SDIV, MVT::i16, Expand);
128 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
129 setOperationAction(ISD::SREM, MVT::i16, Expand);
132 SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
133 switch (Op.getOpcode()) {
134 case ISD::SHL: // FALLTHROUGH
136 case ISD::SRA: return LowerShifts(Op, DAG);
137 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
138 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
139 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
140 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
141 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
143 llvm_unreachable("unimplemented operand");
148 /// getFunctionAlignment - Return the Log2 alignment of this function.
149 unsigned MSP430TargetLowering::getFunctionAlignment(const Function *F) const {
150 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
153 //===----------------------------------------------------------------------===//
154 // Calling Convention Implementation
155 //===----------------------------------------------------------------------===//
157 #include "MSP430GenCallingConv.inc"
160 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
163 const SmallVectorImpl<ISD::InputArg>
167 SmallVectorImpl<SDValue> &InVals) {
171 llvm_unreachable("Unsupported calling convention");
173 case CallingConv::Fast:
174 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
179 MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
180 unsigned CallConv, bool isVarArg,
182 const SmallVectorImpl<ISD::OutputArg> &Outs,
183 const SmallVectorImpl<ISD::InputArg> &Ins,
184 DebugLoc dl, SelectionDAG &DAG,
185 SmallVectorImpl<SDValue> &InVals) {
189 llvm_unreachable("Unsupported calling convention");
190 case CallingConv::Fast:
192 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
193 Outs, Ins, dl, DAG, InVals);
197 /// LowerCCCArguments - transform physical registers into virtual registers and
198 /// generate load operations for arguments places on the stack.
199 // FIXME: struct return stuff
202 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
205 const SmallVectorImpl<ISD::InputArg>
209 SmallVectorImpl<SDValue> &InVals) {
210 MachineFunction &MF = DAG.getMachineFunction();
211 MachineFrameInfo *MFI = MF.getFrameInfo();
212 MachineRegisterInfo &RegInfo = MF.getRegInfo();
214 // Assign locations to all of the incoming arguments.
215 SmallVector<CCValAssign, 16> ArgLocs;
216 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
217 ArgLocs, *DAG.getContext());
218 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
220 assert(!isVarArg && "Varargs not supported yet");
222 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
223 CCValAssign &VA = ArgLocs[i];
225 // Arguments passed in registers
226 EVT RegVT = VA.getLocVT();
227 switch (RegVT.getSimpleVT().SimpleTy) {
231 errs() << "LowerFormalArguments Unhandled argument type: "
232 << RegVT.getSimpleVT().SimpleTy << "\n";
238 RegInfo.createVirtualRegister(MSP430::GR16RegisterClass);
239 RegInfo.addLiveIn(VA.getLocReg(), VReg);
240 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
242 // If this is an 8-bit value, it is really passed promoted to 16
243 // bits. Insert an assert[sz]ext to capture this, then truncate to the
245 if (VA.getLocInfo() == CCValAssign::SExt)
246 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
247 DAG.getValueType(VA.getValVT()));
248 else if (VA.getLocInfo() == CCValAssign::ZExt)
249 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
250 DAG.getValueType(VA.getValVT()));
252 if (VA.getLocInfo() != CCValAssign::Full)
253 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
255 InVals.push_back(ArgValue);
259 assert(VA.isMemLoc());
260 // Load the argument to a virtual register
261 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
263 errs() << "LowerFormalArguments Unhandled argument type: "
264 << VA.getLocVT().getSimpleVT().SimpleTy
267 // Create the frame index object for this incoming parameter...
268 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
270 // Create the SelectionDAG nodes corresponding to a load
271 //from this parameter
272 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
273 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
274 PseudoSourceValue::getFixedStack(FI), 0));
282 MSP430TargetLowering::LowerReturn(SDValue Chain,
283 unsigned CallConv, bool isVarArg,
284 const SmallVectorImpl<ISD::OutputArg> &Outs,
285 DebugLoc dl, SelectionDAG &DAG) {
287 // CCValAssign - represent the assignment of the return value to a location
288 SmallVector<CCValAssign, 16> RVLocs;
290 // CCState - Info about the registers and stack slot.
291 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
292 RVLocs, *DAG.getContext());
294 // Analize return values.
295 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
297 // If this is the first return lowered for this function, add the regs to the
298 // liveout set for the function.
299 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
300 for (unsigned i = 0; i != RVLocs.size(); ++i)
301 if (RVLocs[i].isRegLoc())
302 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
307 // Copy the result values into the output registers.
308 for (unsigned i = 0; i != RVLocs.size(); ++i) {
309 CCValAssign &VA = RVLocs[i];
310 assert(VA.isRegLoc() && "Can only return in registers!");
312 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
315 // Guarantee that all emitted copies are stuck together,
316 // avoiding something bad.
317 Flag = Chain.getValue(1);
321 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
324 return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain);
327 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
328 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
331 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
332 unsigned CallConv, bool isVarArg,
334 const SmallVectorImpl<ISD::OutputArg>
336 const SmallVectorImpl<ISD::InputArg> &Ins,
337 DebugLoc dl, SelectionDAG &DAG,
338 SmallVectorImpl<SDValue> &InVals) {
339 // Analyze operands of the call, assigning locations to each operand.
340 SmallVector<CCValAssign, 16> ArgLocs;
341 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
342 ArgLocs, *DAG.getContext());
344 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
346 // Get a count of how many bytes are to be pushed on the stack.
347 unsigned NumBytes = CCInfo.getNextStackOffset();
349 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
350 getPointerTy(), true));
352 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
353 SmallVector<SDValue, 12> MemOpChains;
356 // Walk the register/memloc assignments, inserting copies/loads.
357 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
358 CCValAssign &VA = ArgLocs[i];
360 SDValue Arg = Outs[i].Val;
362 // Promote the value if needed.
363 switch (VA.getLocInfo()) {
364 default: llvm_unreachable("Unknown loc info!");
365 case CCValAssign::Full: break;
366 case CCValAssign::SExt:
367 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
369 case CCValAssign::ZExt:
370 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
372 case CCValAssign::AExt:
373 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
377 // Arguments that can be passed on register must be kept at RegsToPass
380 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
382 assert(VA.isMemLoc());
384 if (StackPtr.getNode() == 0)
385 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SPW, getPointerTy());
387 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
389 DAG.getIntPtrConstant(VA.getLocMemOffset()));
392 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
393 PseudoSourceValue::getStack(),
394 VA.getLocMemOffset()));
398 // Transform all store nodes into one single node because all store nodes are
399 // independent of each other.
400 if (!MemOpChains.empty())
401 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
402 &MemOpChains[0], MemOpChains.size());
404 // Build a sequence of copy-to-reg nodes chained together with token chain and
405 // flag operands which copy the outgoing args into registers. The InFlag in
406 // necessary since all emited instructions must be stuck together.
408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
409 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
410 RegsToPass[i].second, InFlag);
411 InFlag = Chain.getValue(1);
414 // If the callee is a GlobalAddress node (quite common, every direct call is)
415 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
416 // Likewise ExternalSymbol -> TargetExternalSymbol.
417 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
418 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16);
419 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
420 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
422 // Returns a chain & a flag for retval copy to use.
423 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
424 SmallVector<SDValue, 8> Ops;
425 Ops.push_back(Chain);
426 Ops.push_back(Callee);
428 // Add argument registers to the end of the list so that they are
429 // known live into the call.
430 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
431 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
432 RegsToPass[i].second.getValueType()));
434 if (InFlag.getNode())
435 Ops.push_back(InFlag);
437 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
438 InFlag = Chain.getValue(1);
440 // Create the CALLSEQ_END node.
441 Chain = DAG.getCALLSEQ_END(Chain,
442 DAG.getConstant(NumBytes, getPointerTy(), true),
443 DAG.getConstant(0, getPointerTy(), true),
445 InFlag = Chain.getValue(1);
447 // Handle result values, copying them out of physregs into vregs that we
449 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
453 /// LowerCallResult - Lower the result values of a call into the
454 /// appropriate copies out of appropriate physical registers.
457 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
458 unsigned CallConv, bool isVarArg,
459 const SmallVectorImpl<ISD::InputArg> &Ins,
460 DebugLoc dl, SelectionDAG &DAG,
461 SmallVectorImpl<SDValue> &InVals) {
463 // Assign locations to each value returned by this call.
464 SmallVector<CCValAssign, 16> RVLocs;
465 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
466 RVLocs, *DAG.getContext());
468 CCInfo.AnalyzeCallResult(Ins, RetCC_MSP430);
470 // Copy all of the result registers out of their specified physreg.
471 for (unsigned i = 0; i != RVLocs.size(); ++i) {
472 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
473 RVLocs[i].getValVT(), InFlag).getValue(1);
474 InFlag = Chain.getValue(2);
475 InVals.push_back(Chain.getValue(0));
481 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
483 unsigned Opc = Op.getOpcode();
484 SDNode* N = Op.getNode();
485 EVT VT = Op.getValueType();
486 DebugLoc dl = N->getDebugLoc();
488 // We currently only lower shifts of constant argument.
489 if (!isa<ConstantSDNode>(N->getOperand(1)))
492 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
494 // Expand the stuff into sequence of shifts.
495 // FIXME: for some shift amounts this might be done better!
496 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
497 SDValue Victim = N->getOperand(0);
499 if (Opc == ISD::SRL && ShiftAmount) {
500 // Emit a special goodness here:
501 // srl A, 1 => clrc; rrc A
502 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
506 while (ShiftAmount--)
507 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
513 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
514 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
515 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
517 // Create the TargetGlobalAddress node, folding in the constant offset.
518 SDValue Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
519 return DAG.getNode(MSP430ISD::Wrapper, Op.getDebugLoc(),
520 getPointerTy(), Result);
523 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
525 DebugLoc dl = Op.getDebugLoc();
526 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
527 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
529 return DAG.getNode(MSP430ISD::Wrapper, dl, getPointerTy(), Result);;
532 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC,
534 DebugLoc dl, SelectionDAG &DAG) {
535 // FIXME: Handle bittests someday
536 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
538 // FIXME: Handle jump negative someday
539 TargetCC = MSP430::COND_INVALID;
541 default: llvm_unreachable("Invalid integer condition!");
543 TargetCC = MSP430::COND_E; // aka COND_Z
546 TargetCC = MSP430::COND_NE; // aka COND_NZ
549 std::swap(LHS, RHS); // FALLTHROUGH
551 TargetCC = MSP430::COND_HS; // aka COND_C
554 std::swap(LHS, RHS); // FALLTHROUGH
556 TargetCC = MSP430::COND_LO; // aka COND_NC
559 std::swap(LHS, RHS); // FALLTHROUGH
561 TargetCC = MSP430::COND_GE;
564 std::swap(LHS, RHS); // FALLTHROUGH
566 TargetCC = MSP430::COND_L;
570 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS);
574 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
575 SDValue Chain = Op.getOperand(0);
576 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
577 SDValue LHS = Op.getOperand(2);
578 SDValue RHS = Op.getOperand(3);
579 SDValue Dest = Op.getOperand(4);
580 DebugLoc dl = Op.getDebugLoc();
582 unsigned TargetCC = MSP430::COND_INVALID;
583 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
585 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
587 Dest, DAG.getConstant(TargetCC, MVT::i8),
591 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
592 SDValue LHS = Op.getOperand(0);
593 SDValue RHS = Op.getOperand(1);
594 SDValue TrueV = Op.getOperand(2);
595 SDValue FalseV = Op.getOperand(3);
596 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
597 DebugLoc dl = Op.getDebugLoc();
599 unsigned TargetCC = MSP430::COND_INVALID;
600 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
602 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
603 SmallVector<SDValue, 4> Ops;
604 Ops.push_back(TrueV);
605 Ops.push_back(FalseV);
606 Ops.push_back(DAG.getConstant(TargetCC, MVT::i8));
609 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size());
612 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
614 SDValue Val = Op.getOperand(0);
615 EVT VT = Op.getValueType();
616 DebugLoc dl = Op.getDebugLoc();
618 assert(VT == MVT::i16 && "Only support i16 for now!");
620 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
621 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
622 DAG.getValueType(Val.getValueType()));
625 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
627 default: return NULL;
628 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
629 case MSP430ISD::RRA: return "MSP430ISD::RRA";
630 case MSP430ISD::RLA: return "MSP430ISD::RLA";
631 case MSP430ISD::RRC: return "MSP430ISD::RRC";
632 case MSP430ISD::CALL: return "MSP430ISD::CALL";
633 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
634 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
635 case MSP430ISD::CMP: return "MSP430ISD::CMP";
636 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
640 //===----------------------------------------------------------------------===//
641 // Other Lowering Code
642 //===----------------------------------------------------------------------===//
645 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
646 MachineBasicBlock *BB) const {
647 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
648 DebugLoc dl = MI->getDebugLoc();
649 assert((MI->getOpcode() == MSP430::Select16 ||
650 MI->getOpcode() == MSP430::Select8) &&
651 "Unexpected instr type to insert");
653 // To "insert" a SELECT instruction, we actually have to insert the diamond
654 // control-flow pattern. The incoming instruction knows the destination vreg
655 // to set, the condition code register to branch on, the true/false values to
656 // select between, and a branch opcode to use.
657 const BasicBlock *LLVM_BB = BB->getBasicBlock();
658 MachineFunction::iterator I = BB;
666 // fallthrough --> copy0MBB
667 MachineBasicBlock *thisMBB = BB;
668 MachineFunction *F = BB->getParent();
669 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
670 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
671 BuildMI(BB, dl, TII.get(MSP430::JCC))
673 .addImm(MI->getOperand(3).getImm());
674 F->insert(I, copy0MBB);
675 F->insert(I, copy1MBB);
676 // Update machine-CFG edges by transferring all successors of the current
677 // block to the new block which will contain the Phi node for the select.
678 copy1MBB->transferSuccessors(BB);
679 // Next, add the true and fallthrough blocks as its successors.
680 BB->addSuccessor(copy0MBB);
681 BB->addSuccessor(copy1MBB);
685 // # fallthrough to copy1MBB
688 // Update machine-CFG edges
689 BB->addSuccessor(copy1MBB);
692 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
695 BuildMI(BB, dl, TII.get(MSP430::PHI),
696 MI->getOperand(0).getReg())
697 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
698 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
700 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.