1 //===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the MSP430 target.
12 //===----------------------------------------------------------------------===//
15 #include "MSP430ISelLowering.h"
16 #include "MSP430TargetMachine.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/Statistic.h"
40 ViewRMWDAGs("view-msp430-rmw-dags", cl::Hidden,
41 cl::desc("Pop up a window to show isel dags after RMW preprocess"));
43 static const bool ViewRMWDAGs = false;
46 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
50 struct MSP430ISelAddressMode {
56 struct { // This is really a union, discriminated by BaseType!
64 BlockAddress *BlockAddr;
67 unsigned Align; // CP alignment.
69 MSP430ISelAddressMode()
70 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
71 ES(0), JT(-1), Align(0) {
74 bool hasSymbolicDisplacement() const {
75 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
78 bool hasBaseReg() const {
79 return Base.Reg.getNode() != 0;
82 void setBaseReg(SDValue Reg) {
88 errs() << "MSP430ISelAddressMode " << this << '\n';
89 if (BaseType == RegBase && Base.Reg.getNode() != 0) {
90 errs() << "Base.Reg ";
91 Base.Reg.getNode()->dump();
92 } else if (BaseType == FrameIndexBase) {
93 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
95 errs() << " Disp " << Disp << '\n';
102 errs() << " Align" << Align << '\n';
105 errs() << ES << '\n';
107 errs() << " JT" << JT << " Align" << Align << '\n';
112 /// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
113 /// instructions for SelectionDAG operations.
116 class MSP430DAGToDAGISel : public SelectionDAGISel {
117 MSP430TargetLowering &Lowering;
118 const MSP430Subtarget &Subtarget;
121 MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
122 : SelectionDAGISel(TM, OptLevel),
123 Lowering(*TM.getTargetLowering()),
124 Subtarget(*TM.getSubtargetImpl()) { }
126 virtual void InstructionSelect();
128 virtual const char *getPassName() const {
129 return "MSP430 DAG->DAG Pattern Instruction Selection";
132 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
133 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
134 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
136 bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
139 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
140 std::vector<SDValue> &OutOps);
142 // Include the pieces autogenerated from the target description.
143 #include "MSP430GenDAGISel.inc"
146 DenseMap<SDNode*, SDNode*> RMWStores;
147 void PreprocessForRMW();
148 SDNode *Select(SDNode *N);
149 SDNode *SelectIndexedLoad(SDNode *Op);
150 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
151 unsigned Opc8, unsigned Opc16);
153 bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Disp);
159 } // end anonymous namespace
161 /// createMSP430ISelDag - This pass converts a legalized DAG into a
162 /// MSP430-specific DAG, ready for instruction scheduling.
164 FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
165 CodeGenOpt::Level OptLevel) {
166 return new MSP430DAGToDAGISel(TM, OptLevel);
170 /// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
171 /// These wrap things that will resolve down into a symbol reference. If no
172 /// match is possible, this returns true, otherwise it returns false.
173 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
174 // If the addressing mode already has a symbol as the displacement, we can
175 // never match another symbol.
176 if (AM.hasSymbolicDisplacement())
179 SDValue N0 = N.getOperand(0);
181 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
182 AM.GV = G->getGlobal();
183 AM.Disp += G->getOffset();
184 //AM.SymbolFlags = G->getTargetFlags();
185 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
186 AM.CP = CP->getConstVal();
187 AM.Align = CP->getAlignment();
188 AM.Disp += CP->getOffset();
189 //AM.SymbolFlags = CP->getTargetFlags();
190 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
191 AM.ES = S->getSymbol();
192 //AM.SymbolFlags = S->getTargetFlags();
193 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
194 AM.JT = J->getIndex();
195 //AM.SymbolFlags = J->getTargetFlags();
197 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
198 //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
203 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
204 /// specified addressing mode without any further recursion.
205 bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
206 // Is the base register already occupied?
207 if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
208 // If so, we cannot select it.
212 // Default, generate it as a register.
213 AM.BaseType = MSP430ISelAddressMode::RegBase;
218 bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
220 errs() << "MatchAddress: ";
224 switch (N.getOpcode()) {
226 case ISD::Constant: {
227 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
232 case MSP430ISD::Wrapper:
233 if (!MatchWrapper(N, AM))
237 case ISD::FrameIndex:
238 if (AM.BaseType == MSP430ISelAddressMode::RegBase
239 && AM.Base.Reg.getNode() == 0) {
240 AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
241 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
247 MSP430ISelAddressMode Backup = AM;
248 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
249 !MatchAddress(N.getNode()->getOperand(1), AM))
252 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
253 !MatchAddress(N.getNode()->getOperand(0), AM))
261 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
262 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
263 MSP430ISelAddressMode Backup = AM;
264 uint64_t Offset = CN->getSExtValue();
265 // Start with the LHS as an addr mode.
266 if (!MatchAddress(N.getOperand(0), AM) &&
267 // Address could not have picked a GV address for the displacement.
269 // Check to see if the LHS & C is zero.
270 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
279 return MatchAddressBase(N, AM);
282 /// SelectAddr - returns true if it is able pattern match an addressing mode.
283 /// It returns the operands which make up the maximal addressing mode it can
284 /// match by reference.
285 bool MSP430DAGToDAGISel::SelectAddr(SDNode *Op, SDValue N,
286 SDValue &Base, SDValue &Disp) {
287 MSP430ISelAddressMode AM;
289 if (MatchAddress(N, AM))
292 EVT VT = N.getValueType();
293 if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
294 if (!AM.Base.Reg.getNode())
295 AM.Base.Reg = CurDAG->getRegister(0, VT);
298 Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) ?
299 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
303 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i16, AM.Disp,
304 0/*AM.SymbolFlags*/);
306 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
307 AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
309 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
310 else if (AM.JT != -1)
311 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
312 else if (AM.BlockAddr)
313 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
314 true, 0/*AM.SymbolFlags*/);
316 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i16);
321 bool MSP430DAGToDAGISel::
322 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
323 std::vector<SDValue> &OutOps) {
325 switch (ConstraintCode) {
326 default: return true;
328 if (!SelectAddr(Op.getNode(), Op, Op0, Op1))
333 OutOps.push_back(Op0);
334 OutOps.push_back(Op1);
338 bool MSP430DAGToDAGISel::IsLegalToFold(SDValue N, SDNode *U,
339 SDNode *Root) const {
340 if (OptLevel == CodeGenOpt::None) return false;
342 /// RMW preprocessing creates the following code:
359 /// The path Store => Load2 => Load1 is via chain. Note that in general it is
360 /// not allowed to fold Load1 into Op (and Store) since it will creates a
361 /// cycle. However, this is perfectly legal for the loads moved below the
362 /// TokenFactor by PreprocessForRMW. Query the map Store => Load1 (created
363 /// during preprocessing) to determine whether it's legal to introduce such
364 /// "cycle" for a moment.
365 DenseMap<SDNode*, SDNode*>::const_iterator I = RMWStores.find(Root);
366 if (I != RMWStores.end() && I->second == N.getNode())
369 // Proceed to 'generic' cycle finder code
370 return SelectionDAGISel::IsLegalToFold(N, U, Root);
374 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
375 /// and move load below the TokenFactor. Replace store's chain operand with
376 /// load's chain result.
377 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
378 SDValue Store, SDValue TF) {
379 SmallVector<SDValue, 4> Ops;
380 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
381 if (Load.getNode() == TF.getOperand(i).getNode())
382 Ops.push_back(Load.getOperand(0));
384 Ops.push_back(TF.getOperand(i));
385 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
386 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
389 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
390 Store.getOperand(2), Store.getOperand(3));
393 /// MoveBelowTokenFactor2 - Replace TokenFactor operand with load's chain operand
394 /// and move load below the TokenFactor. Replace store's chain operand with
395 /// load's chain result. This a version which sinks two loads below token factor.
396 /// Look into PreprocessForRMW comments for explanation of transform.
397 static void MoveBelowTokenFactor2(SelectionDAG *CurDAG,
398 SDValue Load1, SDValue Load2,
399 SDValue Store, SDValue TF) {
400 SmallVector<SDValue, 4> Ops;
401 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i) {
402 SDNode* N = TF.getOperand(i).getNode();
403 if (Load2.getNode() == N)
404 Ops.push_back(Load2.getOperand(0));
405 else if (Load1.getNode() != N)
406 Ops.push_back(TF.getOperand(i));
409 SDValue NewTF = SDValue(CurDAG->MorphNodeTo(TF.getNode(),
411 TF.getNode()->getVTList(),
412 &Ops[0], Ops.size()), TF.getResNo());
413 SDValue NewLoad2 = CurDAG->UpdateNodeOperands(Load2, NewTF,
415 Load2.getOperand(2));
417 SDValue NewLoad1 = CurDAG->UpdateNodeOperands(Load1, NewLoad2.getValue(1),
419 Load1.getOperand(2));
421 CurDAG->UpdateNodeOperands(Store,
422 NewLoad1.getValue(1),
424 Store.getOperand(2), Store.getOperand(3));
427 /// isAllowedToSink - return true if N a load which can be moved below token
428 /// factor. Basically, the load should be non-volatile and has single use.
429 static bool isLoadAllowedToSink(SDValue N, SDValue Chain) {
430 if (N.getOpcode() == ISD::BIT_CONVERT)
433 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
434 if (!LD || LD->isVolatile())
436 if (LD->getAddressingMode() != ISD::UNINDEXED)
439 ISD::LoadExtType ExtType = LD->getExtensionType();
440 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
443 return (N.hasOneUse() &&
444 LD->hasNUsesOfValue(1, 1) &&
445 LD->isOperandOf(Chain.getNode()));
449 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
450 /// The chain produced by the load must only be used by the store's chain
451 /// operand, otherwise this may produce a cycle in the DAG.
452 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
454 if (isLoadAllowedToSink(N, Chain) &&
455 N.getOperand(1) == Address) {
462 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
463 /// This is only run if not in -O0 mode.
464 /// This allows the instruction selector to pick more read-modify-write
465 /// instructions. This is a common case:
475 /// [TokenFactor] [Op]
482 /// The fact the store's chain operand != load's chain will prevent the
483 /// (store (op (load))) instruction from being selected. We can transform it to:
503 /// We also recognize the case where second operand of Op is load as well and
504 /// move it below token factor as well creating DAG as follows:
528 /// This allows selection of mem-mem instructions. Yay!
530 void MSP430DAGToDAGISel::PreprocessForRMW() {
531 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
532 E = CurDAG->allnodes_end(); I != E; ++I) {
533 if (!ISD::isNON_TRUNCStore(I))
535 SDValue Chain = I->getOperand(0);
537 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
540 SDValue N1 = I->getOperand(1);
541 SDValue N2 = I->getOperand(2);
542 if ((N1.getValueType().isFloatingPoint() &&
543 !N1.getValueType().isVector()) ||
548 SDValue Load1, Load2;
549 unsigned Opcode = N1.getNode()->getOpcode();
557 SDValue N10 = N1.getOperand(0);
558 SDValue N11 = N1.getOperand(1);
559 if (isRMWLoad(N10, Chain, N2, Load1)) {
560 if (isLoadAllowedToSink(N11, Chain)) {
565 } else if (isRMWLoad(N11, Chain, N2, Load1)) {
566 if (isLoadAllowedToSink(N10, Chain)) {
577 SDValue N10 = N1.getOperand(0);
578 SDValue N11 = N1.getOperand(1);
579 if (isRMWLoad(N10, Chain, N2, Load1)) {
580 if (isLoadAllowedToSink(N11, Chain)) {
590 NumLoadMoved += RModW;
592 MoveBelowTokenFactor(CurDAG, Load1, SDValue(I, 0), Chain);
593 else if (RModW == 2) {
594 MoveBelowTokenFactor2(CurDAG, Load1, Load2, SDValue(I, 0), Chain);
596 RMWStores[Store] = Load2.getNode();
602 static bool isValidIndexedLoad(const LoadSDNode *LD) {
603 ISD::MemIndexedMode AM = LD->getAddressingMode();
604 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
607 EVT VT = LD->getMemoryVT();
609 switch (VT.getSimpleVT().SimpleTy) {
612 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
618 if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
629 SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
630 LoadSDNode *LD = cast<LoadSDNode>(N);
631 if (!isValidIndexedLoad(LD))
634 MVT VT = LD->getMemoryVT().getSimpleVT();
637 switch (VT.SimpleTy) {
639 Opcode = MSP430::MOV8rm_POST;
642 Opcode = MSP430::MOV16rm_POST;
648 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
649 VT, MVT::i16, MVT::Other,
650 LD->getBasePtr(), LD->getChain());
653 SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
654 SDValue N1, SDValue N2,
655 unsigned Opc8, unsigned Opc16) {
656 if (N1.getOpcode() == ISD::LOAD &&
658 IsLegalToFold(N1, Op, Op)) {
659 LoadSDNode *LD = cast<LoadSDNode>(N1);
660 if (!isValidIndexedLoad(LD))
663 MVT VT = LD->getMemoryVT().getSimpleVT();
664 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
665 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
666 MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
667 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
669 CurDAG->SelectNodeTo(Op, Opc,
670 VT, MVT::i16, MVT::Other,
672 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
674 ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
675 // Transfer writeback.
676 ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
684 /// InstructionSelect - This callback is invoked by
685 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
686 void MSP430DAGToDAGISel::InstructionSelect() {
687 std::string BlockName;
689 BlockName = MF->getFunction()->getNameStr() + ":" +
690 BB->getBasicBlock()->getNameStr();
694 if (ViewRMWDAGs) CurDAG->viewGraph("RMW preprocessed:" + BlockName);
696 DEBUG(errs() << "Selection DAG after RMW preprocessing:\n");
697 DEBUG(CurDAG->dump());
699 // Codegen the basic block.
700 DEBUG(errs() << "===== Instruction selection begins:\n");
703 DEBUG(errs() << "===== Instruction selection ends:\n");
705 CurDAG->RemoveDeadNodes();
709 SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
710 DebugLoc dl = Node->getDebugLoc();
712 // Dump information about the Node being selected
713 DEBUG(errs().indent(Indent) << "Selecting: ");
714 DEBUG(Node->dump(CurDAG));
715 DEBUG(errs() << "\n");
718 // If we have a custom node, we already have selected!
719 if (Node->isMachineOpcode()) {
720 DEBUG(errs().indent(Indent-2) << "== ";
727 // Few custom selection stuff.
728 switch (Node->getOpcode()) {
730 case ISD::FrameIndex: {
731 assert(Node->getValueType(0) == MVT::i16);
732 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
733 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
734 if (Node->hasOneUse())
735 return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16,
736 TFI, CurDAG->getTargetConstant(0, MVT::i16));
737 return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16,
738 TFI, CurDAG->getTargetConstant(0, MVT::i16));
741 if (SDNode *ResNode = SelectIndexedLoad(Node))
743 // Other cases are autogenerated.
746 if (SDNode *ResNode =
747 SelectIndexedBinOp(Node,
748 Node->getOperand(0), Node->getOperand(1),
749 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
751 else if (SDNode *ResNode =
752 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
753 MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
756 // Other cases are autogenerated.
759 if (SDNode *ResNode =
760 SelectIndexedBinOp(Node,
761 Node->getOperand(0), Node->getOperand(1),
762 MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
765 // Other cases are autogenerated.
768 if (SDNode *ResNode =
769 SelectIndexedBinOp(Node,
770 Node->getOperand(0), Node->getOperand(1),
771 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
773 else if (SDNode *ResNode =
774 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
775 MSP430::AND8rm_POST, MSP430::AND16rm_POST))
778 // Other cases are autogenerated.
781 if (SDNode *ResNode =
782 SelectIndexedBinOp(Node,
783 Node->getOperand(0), Node->getOperand(1),
784 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
786 else if (SDNode *ResNode =
787 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
788 MSP430::OR8rm_POST, MSP430::OR16rm_POST))
791 // Other cases are autogenerated.
794 if (SDNode *ResNode =
795 SelectIndexedBinOp(Node,
796 Node->getOperand(0), Node->getOperand(1),
797 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
799 else if (SDNode *ResNode =
800 SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
801 MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
804 // Other cases are autogenerated.
808 // Select the default instruction
809 SDNode *ResNode = SelectCode(Node);
811 DEBUG(errs() << std::string(Indent-2, ' ') << "=> ");
812 if (ResNode == NULL || ResNode == Node)
813 DEBUG(Node->dump(CurDAG));
815 DEBUG(ResNode->dump(CurDAG));
816 DEBUG(errs() << "\n");