lib/Target/IA64/IA64RegisterInfo.h

   1 //===- IA64RegisterInfo.h - IA64 Register Information Impl ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by Duraid Madina and is distributed under the
   6 // University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the IA64 implementation of the MRegisterInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef IA64REGISTERINFO_H
  15 #define IA64REGISTERINFO_H
  16
  17 #include "llvm/Target/MRegisterInfo.h"
  18 #include "IA64GenRegisterInfo.h.inc"
  19
  20 namespace llvm { class llvm::Type; }
  21
  22 namespace llvm {
  23
  24 class TargetInstrInfo;
  25
  26 struct IA64RegisterInfo : public IA64GenRegisterInfo {
  27   const TargetInstrInfo &TII;
  28
  29   IA64RegisterInfo(const TargetInstrInfo &tii);
  30
  31   /// Code Generation virtual methods...
  32   void storeRegToStackSlot(MachineBasicBlock &MBB,
  33                            MachineBasicBlock::iterator MI,
  34                            unsigned SrcReg, int FrameIndex,
  35                            const TargetRegisterClass *RC) const;
  36
  37   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
  38                       SmallVectorImpl<MachineOperand> &Addr,
  39                       const TargetRegisterClass *RC,
  40                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
  41
  42   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  43                             MachineBasicBlock::iterator MI,
  44                             unsigned DestReg, int FrameIndex,
  45                             const TargetRegisterClass *RC) const;
  46
  47   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
  48                        SmallVectorImpl<MachineOperand> &Addr,
  49                        const TargetRegisterClass *RC,
  50                        SmallVectorImpl<MachineInstr*> &NewMIs) const;
  51
  52   void copyRegToReg(MachineBasicBlock &MBB,
  53                     MachineBasicBlock::iterator MI,
  54                     unsigned DestReg, unsigned SrcReg,
  55                     const TargetRegisterClass *DestRC,
  56                     const TargetRegisterClass *SrcRC) const;
  57
  58   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
  59                      unsigned DestReg, const MachineInstr *Orig) const;
  60
  61   const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
  62
  63   const TargetRegisterClass* const* getCalleeSavedRegClasses(
  64                                      const MachineFunction *MF = 0) const;
  65
  66   BitVector getReservedRegs(const MachineFunction &MF) const;
  67
  68   bool hasFP(const MachineFunction &MF) const;
  69
  70   void eliminateCallFramePseudoInstr(MachineFunction &MF,
  71                                      MachineBasicBlock &MBB,
  72                                      MachineBasicBlock::iterator MI) const;
  73
  74   void eliminateFrameIndex(MachineBasicBlock::iterator MI,
  75                            int SPAdj, RegScavenger *RS = NULL) const;
  76
  77   void emitPrologue(MachineFunction &MF) const;
  78   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
  79
  80   // Debug information queries.
  81   unsigned getRARegister() const;
  82   unsigned getFrameRegister(MachineFunction &MF) const;
  83
  84   // Exception handling queries.
  85   unsigned getEHExceptionRegister() const;
  86   unsigned getEHHandlerRegister() const;
  87
  88   int getDwarfRegNum(unsigned RegNum, bool isEH) const;
  89 };
  90
  91 } // End llvm namespace
  92
  93 #endif
  94