1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 IA64DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
88 virtual const char *getPassName() const {
89 return "IA64 (Itanium) DAG->DAG Instruction Selector";
92 // Include the pieces autogenerated from the target description.
93 #include "IA64GenDAGISel.inc"
96 SDOperand SelectCALL(SDOperand Op);
100 /// InstructionSelectBasicBlock - This callback is invoked by
101 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
105 // The selection process is inherently a bottom-up recursive process (users
106 // select their uses before themselves). Given infinite stack space, we
107 // could just start selecting on the root and traverse the whole graph. In
108 // practice however, this causes us to run out of stack space on large basic
109 // blocks. To avoid this problem, select the entry node, then all its uses,
110 // iteratively instead of recursively.
111 std::vector<SDOperand> Worklist;
112 Worklist.push_back(DAG.getEntryNode());
114 // Note that we can do this in the IA64 target (scanning forward across token
115 // chain edges) because no nodes ever get folded across these edges. On a
116 // target like X86 which supports load/modify/store operations, this would
117 // have to be more careful.
118 while (!Worklist.empty()) {
119 SDOperand Node = Worklist.back();
122 // Chose from the least deep of the top two nodes.
123 if (!Worklist.empty() &&
124 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
125 std::swap(Worklist.back(), Node);
127 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
128 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
129 CodeGenMap.count(Node)) continue;
131 for (SDNode::use_iterator UI = Node.Val->use_begin(),
132 E = Node.Val->use_end(); UI != E; ++UI) {
133 // Scan the values. If this use has a value that is a token chain, add it
136 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
137 if (User->getValueType(i) == MVT::Other) {
138 Worklist.push_back(SDOperand(User, i));
143 // Finally, legalize this node.
147 // Select target instructions for the DAG.
148 DAG.setRoot(Select(DAG.getRoot()));
150 DAG.RemoveDeadNodes();
152 // Emit machine code to BB.
153 ScheduleAndEmitDAG(DAG);
157 SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
159 SDOperand Chain = Select(N->getOperand(0));
162 std::vector<SDOperand> CallOperands;
164 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
165 SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
166 Chain = GPBeforeCall.getValue(1);
167 SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
168 Chain = SPBeforeCall.getValue(1);
169 SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
170 Chain = RPBeforeCall.getValue(1);
172 // if we can call directly, do so
173 if (GlobalAddressSDNode *GASD =
174 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
175 CallOpcode = IA64::BRCALL_IPREL;
176 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
178 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
179 // case for correctness, to avoid
180 // "non-pic code with imm reloc.n
181 // against dynamic symbol" errors
182 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
183 CallOpcode = IA64::BRCALL_IPREL;
184 CallOperands.push_back(N->getOperand(1));
186 // otherwise we need to load the function descriptor,
187 // load the branch target (function)'s entry point and GP,
188 // branch (call) then restore the
191 SDOperand FnDescriptor = Select(N->getOperand(1));
193 // load the branch target's entry point [mem] and
195 SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
196 CurDAG->getSrcValue(0));
197 SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
198 CurDAG->getConstant(8, MVT::i64));
199 SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
200 CurDAG->getSrcValue(0));
202 // Copy the callee address into the b6 branch register
203 SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
204 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, B6,
207 CallOperands.push_back(B6);
208 CallOpcode = IA64::BRCALL_INDIRECT;
211 // TODO: support in-memory arguments
212 unsigned used_FPArgs=0; // how many FP args have been used so far?
214 unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
215 IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
216 unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
217 IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
219 SDOperand InFlag; // Null incoming flag value.
221 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
222 unsigned DestReg = 0;
223 MVT::ValueType RegTy = N->getOperand(i).getValueType();
224 if (RegTy == MVT::i64) {
225 assert((i-2) < 8 && "Too many int args");
226 DestReg = intArgs[i-2];
228 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
229 "Unpromoted integer arg?");
230 assert(used_FPArgs < 8 && "Too many fp args");
231 DestReg = FPArgs[used_FPArgs++];
234 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
235 SDOperand Val = Select(N->getOperand(i));
236 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
237 InFlag = Chain.getValue(1);
238 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
242 // Finally, once everything is in registers to pass to the call, emit the
245 CallOperands.push_back(InFlag); // Strong dep on register copies.
247 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
248 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
251 // return Chain; // HACK: err, this means that functions never return anything. need to intergrate this with the code immediately below FIXME XXX
253 std::vector<SDOperand> CallResults;
255 // If the call has results, copy the values out of the ret val registers.
256 switch (N->getValueType(0)) {
257 default: assert(0 && "Unexpected ret value!");
258 case MVT::Other: break;
260 Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
261 Chain.getValue(1)).getValue(1);
262 CallResults.push_back(Chain.getValue(0));
265 Chain = CurDAG->getCopyFromReg(Chain, IA64::F8, N->getValueType(0),
266 Chain.getValue(1)).getValue(1);
267 CallResults.push_back(Chain.getValue(0));
270 // restore GP, SP and RP
271 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
272 Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
273 Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
275 CallResults.push_back(Chain);
277 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
278 CodeGenMap[Op.getValue(i)] = CallResults[i];
280 return CallResults[Op.ResNo];
283 // Select - Convert the specified operand from a target-independent to a
284 // target-specific node if it hasn't already been changed.
285 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
287 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
288 N->getOpcode() < IA64ISD::FIRST_NUMBER)
289 return Op; // Already selected.
291 // If this has already been converted, use it.
292 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
293 if (CGMI != CodeGenMap.end()) return CGMI->second;
295 switch (N->getOpcode()) {
299 case ISD::TAILCALL: return SelectCALL(Op);
302 * case ISD::DYNAMIC_STACKALLOC:
305 case ISD::FrameIndex: { // TODO: reduce creepyness
306 int FI = cast<FrameIndexSDNode>(N)->getIndex();
307 if (N->hasOneUse()) {
308 CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
309 CurDAG->getTargetFrameIndex(FI, MVT::i64));
310 return SDOperand(N, 0);
312 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
313 CurDAG->getTargetFrameIndex(FI, MVT::i64));
316 case ISD::TokenFactor: {
318 if (N->getNumOperands() == 2) {
319 SDOperand Op0 = Select(N->getOperand(0));
320 SDOperand Op1 = Select(N->getOperand(1));
321 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
323 std::vector<SDOperand> Ops;
324 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
325 Ops.push_back(Select(N->getOperand(i)));
326 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
329 CodeGenMap[Op] = New;
332 case ISD::CopyFromReg: {
333 SDOperand Chain = Select(N->getOperand(0));
334 if (Chain == N->getOperand(0)) return Op; // No change
335 SDOperand New = CurDAG->getCopyFromReg(Chain,
336 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
337 return New.getValue(Op.ResNo);
339 case ISD::CopyToReg: {
340 SDOperand Chain = Select(N->getOperand(0));
341 SDOperand Reg = N->getOperand(1);
342 SDOperand Val = Select(N->getOperand(2));
343 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
345 CodeGenMap[Op] = New;
349 case ISD::GlobalAddress: {
350 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
351 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
352 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
353 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
354 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
359 case ISD::ZEXTLOAD: {
360 SDOperand Chain = Select(N->getOperand(0));
361 SDOperand Address = Select(N->getOperand(1));
363 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
364 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
366 switch (TypeBeingLoaded) {
367 default: N->dump(); assert(0 && "Cannot load this type!");
368 // FIXME: bools? case MVT::i1:
369 case MVT::i8: Opc = IA64::LD1; break;
370 case MVT::i16: Opc = IA64::LD2; break;
371 case MVT::i32: Opc = IA64::LD4; break;
372 case MVT::i64: Opc = IA64::LD8; break;
374 case MVT::f32: Opc = IA64::LDF4; break;
375 case MVT::f64: Opc = IA64::LDF8; break;
378 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
379 Address, Chain); // TODO: comment this
381 return SDOperand(N, Op.ResNo);
384 case ISD::TRUNCSTORE:
386 SDOperand Address = Select(N->getOperand(2));
389 if (N->getOpcode() == ISD::STORE) {
390 switch (N->getOperand(1).getValueType()) {
391 default: assert(0 && "unknown Type in store");
392 case MVT::i64: Opc = IA64::ST8; break;
393 case MVT::f64: Opc = IA64::STF8; break;
395 } else { //ISD::TRUNCSTORE
396 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
397 default: assert(0 && "unknown Type in store");
398 case MVT::i8: Opc = IA64::ST1; break;
399 case MVT::i16: Opc = IA64::ST2; break;
400 case MVT::i32: Opc = IA64::ST4; break;
401 case MVT::f32: Opc = IA64::STF4; break;
405 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
406 Select(N->getOperand(1)), Select(N->getOperand(0)));
407 return SDOperand(N, 0);
411 SDOperand Chain = Select(N->getOperand(0));
412 SDOperand CC = Select(N->getOperand(1));
413 MachineBasicBlock *Dest =
414 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
415 //FIXME - we do NOT need long branches all the time
416 CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
417 return SDOperand(N, 0);
420 case ISD::CALLSEQ_START:
421 case ISD::CALLSEQ_END: {
422 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
423 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
424 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
425 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
426 getI64Imm(Amt), Select(N->getOperand(0)));
427 return SDOperand(N, 0);
431 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
433 switch (N->getNumOperands()) {
435 assert(0 && "Unknown return instruction!");
437 SDOperand RetVal = Select(N->getOperand(1));
438 switch (RetVal.getValueType()) {
439 default: assert(0 && "I don't know how to return this type! (promote?)");
440 // FIXME: do I need to add support for bools here?
441 // (return '0' or '1' in r8, basically...)
443 // FIXME: need to round floats - 80 bits is bad, the tester
446 // we mark r8 as live on exit up above in LowerArguments()
447 // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
448 Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
451 // we mark F8 as live on exit up above in LowerArguments()
452 // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
453 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
462 // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
463 // the output of this function's alloc instruction back into ar.pfs
464 // before we return. this copy must not float up above the last
465 // outgoing call in this function!!!
466 SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
468 Chain = AR_PFSVal.getValue(1);
469 Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
471 CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
473 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
474 // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
476 return SDOperand(N, 0);
480 // FIXME: we don't need long branches all the time!
481 CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
482 Select(N->getOperand(0)));
483 return SDOperand(N, 0);
487 return SelectCode(Op);
491 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
492 /// into an IA64-specific DAG, ready for instruction scheduling.
494 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
495 return new IA64DAGToDAGISel(TM);