1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
34 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
35 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
37 //===--------------------------------------------------------------------===//
38 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
39 /// instructions for SelectionDAG operations.
41 class IA64DAGToDAGISel : public SelectionDAGISel {
42 IA64TargetLowering IA64Lowering;
43 unsigned GlobalBaseReg;
45 IA64DAGToDAGISel(IA64TargetMachine &TM)
46 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
48 virtual bool runOnFunction(Function &Fn) {
49 // Make sure we re-emit a set of the global base reg if necessary
51 return SelectionDAGISel::runOnFunction(Fn);
54 /// getI64Imm - Return a target constant with the specified value, of type
56 inline SDOperand getI64Imm(uint64_t Imm) {
57 return CurDAG->getTargetConstant(Imm, MVT::i64);
60 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
61 /// base register. Return the virtual register that holds this value.
62 // SDOperand getGlobalBaseReg(); TODO: hmm
64 // Select - Convert the specified operand from a target-independent to a
65 // target-specific node if it hasn't already been changed.
66 void Select(SDOperand &Result, SDOperand N);
68 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
69 unsigned OCHi, unsigned OCLo,
70 bool IsArithmetic = false,
72 SDNode *SelectBitfieldInsert(SDNode *N);
74 /// SelectCC - Select a comparison of the specified values with the
75 /// specified condition code, returning the CR# of the expression.
76 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
78 /// SelectAddr - Given the specified address, return the two operands for a
79 /// load/store instruction, and return true if it should be an indexed [r+r]
81 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
83 SDOperand BuildSDIVSequence(SDNode *N);
84 SDOperand BuildUDIVSequence(SDNode *N);
86 /// InstructionSelectBasicBlock - This callback is invoked by
87 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
88 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
90 virtual const char *getPassName() const {
91 return "IA64 (Itanium) DAG->DAG Instruction Selector";
94 // Include the pieces autogenerated from the target description.
95 #include "IA64GenDAGISel.inc"
98 SDOperand SelectDIV(SDOperand Op);
102 /// InstructionSelectBasicBlock - This callback is invoked by
103 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
104 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
107 // The selection process is inherently a bottom-up recursive process (users
108 // select their uses before themselves). Given infinite stack space, we
109 // could just start selecting on the root and traverse the whole graph. In
110 // practice however, this causes us to run out of stack space on large basic
111 // blocks. To avoid this problem, select the entry node, then all its uses,
112 // iteratively instead of recursively.
113 std::vector<SDOperand> Worklist;
114 Worklist.push_back(DAG.getEntryNode());
116 // Note that we can do this in the IA64 target (scanning forward across token
117 // chain edges) because no nodes ever get folded across these edges. On a
118 // target like X86 which supports load/modify/store operations, this would
119 // have to be more careful.
120 while (!Worklist.empty()) {
121 SDOperand Node = Worklist.back();
124 // Chose from the least deep of the top two nodes.
125 if (!Worklist.empty() &&
126 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
127 std::swap(Worklist.back(), Node);
129 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
130 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
131 CodeGenMap.count(Node)) continue;
133 for (SDNode::use_iterator UI = Node.Val->use_begin(),
134 E = Node.Val->use_end(); UI != E; ++UI) {
135 // Scan the values. If this use has a value that is a token chain, add it
138 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
139 if (User->getValueType(i) == MVT::Other) {
140 Worklist.push_back(SDOperand(User, i));
145 // Finally, legalize this node.
150 // Select target instructions for the DAG.
151 DAG.setRoot(SelectRoot(DAG.getRoot()));
153 DAG.RemoveDeadNodes();
155 // Emit machine code to BB.
156 ScheduleAndEmitDAG(DAG);
159 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
161 SDOperand Chain, Tmp1, Tmp2;
162 Select(Chain, N->getOperand(0));
164 Select(Tmp1, N->getOperand(0));
165 Select(Tmp2, N->getOperand(1));
169 if(MVT::isFloatingPoint(Tmp1.getValueType()))
172 bool isModulus=false; // is it a division or a modulus?
175 switch(N->getOpcode()) {
177 case ISD::SDIV: isModulus=false; isSigned=true; break;
178 case ISD::UDIV: isModulus=false; isSigned=false; break;
180 case ISD::SREM: isModulus=true; isSigned=true; break;
181 case ISD::UREM: isModulus=true; isSigned=false; break;
184 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
186 SDOperand TmpPR, TmpPR2;
187 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
188 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
191 // we'll need copies of F0 and F1
192 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
193 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
195 // OK, emit some code:
198 // first, load the inputs into FP regs.
200 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
201 Chain = TmpF1.getValue(1);
203 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
204 Chain = TmpF2.getValue(1);
206 // next, convert the inputs to FP
209 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
210 Chain = TmpF3.getValue(1);
212 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
213 Chain = TmpF4.getValue(1);
214 } else { // is unsigned
216 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
217 Chain = TmpF3.getValue(1);
219 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
220 Chain = TmpF4.getValue(1);
223 } else { // this is an FP divide/remainder, so we 'leak' some temp
224 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
229 // we start by computing an approximate reciprocal (good to 9 bits?)
230 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
232 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
235 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
238 TmpPR = TmpF5.getValue(1);
239 Chain = TmpF5.getValue(2);
242 if(isModulus) { // for remainders, it'll be handy to have
243 // copies of -input_b
244 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
245 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
246 Chain = minusB.getValue(1);
249 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
251 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
252 TmpF4, TmpF5, F1, TmpPR), 0);
253 Chain = TmpE0.getValue(1);
254 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
255 TmpF5, TmpE0, TmpF5, TmpPR), 0);
256 Chain = TmpY1.getValue(1);
257 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
258 TmpE0, TmpE0, F0, TmpPR), 0);
259 Chain = TmpE1.getValue(1);
260 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
261 TmpY1, TmpE1, TmpY1, TmpPR), 0);
262 Chain = TmpY2.getValue(1);
264 if(isFP) { // if this is an FP divide, we finish up here and exit early
266 assert(0 && "Sorry, try another FORTRAN compiler.");
268 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
270 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
271 TmpE1, TmpE1, F0, TmpPR), 0);
272 Chain = TmpE2.getValue(1);
273 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
274 TmpY2, TmpE2, TmpY2, TmpPR), 0);
275 Chain = TmpY3.getValue(1);
277 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
278 Tmp1, TmpY3, F0, TmpPR), 0);
279 Chain = TmpQ0.getValue(1);
281 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
282 Tmp2, TmpQ0, Tmp1, TmpPR), 0);
283 Chain = TmpR0.getValue(1);
285 // we want Result to have the same target register as the frcpa, so
286 // we two-address hack it. See the comment "for this to work..." on
287 // page 48 of Intel application note #245415
288 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
289 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
290 Chain = SDOperand(Result, 1);
291 return SDOperand(Result, 0); // XXX: early exit!
292 } else { // this is *not* an FP divide, so there's a bit left to do:
294 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
296 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
297 TmpF3, TmpY2, F0, TmpPR), 0);
298 Chain = TmpQ2.getValue(1);
299 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
300 TmpF4, TmpQ2, TmpF3, TmpPR), 0);
301 Chain = TmpR2.getValue(1);
303 // we want TmpQ3 to have the same target register as the frcpa? maybe we
304 // should two-address hack it. See the comment "for this to work..." on page
305 // 48 of Intel application note #245415
306 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
307 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
308 Chain = TmpQ3.getValue(1);
310 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
311 // the FPSWA won't be able to help out in the case of large/tiny
312 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
315 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
316 MVT::f64, TmpQ3), 0);
318 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
319 MVT::f64, TmpQ3), 0);
321 Chain = TmpQ.getValue(1);
325 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
326 Chain = FPminusB.getValue(1);
327 SDOperand Remainder =
328 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
329 TmpQ, FPminusB, TmpF1), 0);
330 Chain = Remainder.getValue(1);
331 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
332 Chain = SDOperand(Result, 1);
333 } else { // just an integer divide
334 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
335 Chain = SDOperand(Result, 1);
338 return SDOperand(Result, 0);
339 } // wasn't an FP divide
342 // Select - Convert the specified operand from a target-independent to a
343 // target-specific node if it hasn't already been changed.
344 void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
346 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
347 N->getOpcode() < IA64ISD::FIRST_NUMBER) {
349 return; // Already selected.
352 // If this has already been converted, use it.
353 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
354 if (CGMI != CodeGenMap.end()) {
355 Result = CGMI->second;
359 switch (N->getOpcode()) {
362 case IA64ISD::BRCALL: { // XXX: this is also a hack!
364 SDOperand InFlag; // Null incoming flag value.
366 Select(Chain, N->getOperand(0));
367 if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
368 Select(InFlag, N->getOperand(2));
371 SDOperand CallOperand;
373 // if we can call directly, do so
374 if (GlobalAddressSDNode *GASD =
375 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
376 CallOpcode = IA64::BRCALL_IPREL_GA;
377 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
378 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
379 // case for correctness, to avoid
380 // "non-pic code with imm reloc.n
381 // against dynamic symbol" errors
382 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
383 CallOpcode = IA64::BRCALL_IPREL_ES;
384 CallOperand = N->getOperand(1);
386 // otherwise we need to load the function descriptor,
387 // load the branch target (function)'s entry point and GP,
388 // branch (call) then restore the GP
389 SDOperand FnDescriptor;
390 Select(FnDescriptor, N->getOperand(1));
392 // load the branch target's entry point [mem] and
394 SDOperand targetEntryPoint=
395 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
396 Chain = targetEntryPoint.getValue(1);
397 SDOperand targetGPAddr=
398 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
399 FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
400 Chain = targetGPAddr.getValue(1);
402 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
403 Chain = targetGP.getValue(1);
405 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
406 InFlag = Chain.getValue(1);
407 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
408 InFlag = Chain.getValue(1);
410 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
411 CallOpcode = IA64::BRCALL_INDIRECT;
414 // Finally, once everything is setup, emit the call itself
416 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
417 CallOperand, InFlag), 0);
418 else // there might be no arguments
419 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
420 CallOperand, Chain), 0);
421 InFlag = Chain.getValue(1);
423 std::vector<SDOperand> CallResults;
425 CallResults.push_back(Chain);
426 CallResults.push_back(InFlag);
428 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
429 CodeGenMap[Op.getValue(i)] = CallResults[i];
430 Result = CallResults[Op.ResNo];
434 case IA64ISD::GETFD: {
436 Select(Input, N->getOperand(0));
437 Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
438 CodeGenMap[Op] = Result;
447 Result = SelectDIV(Op);
450 case ISD::TargetConstantFP: {
451 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
453 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
454 Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
455 } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
456 Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
458 assert(0 && "Unexpected FP constant!");
462 case ISD::FrameIndex: { // TODO: reduce creepyness
463 int FI = cast<FrameIndexSDNode>(N)->getIndex();
465 Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
466 CurDAG->getTargetFrameIndex(FI, MVT::i64));
468 Result = CodeGenMap[Op] = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
469 CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
473 case ISD::ConstantPool: { // TODO: nuke the constant pool
474 // (ia64 doesn't need one)
475 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
476 Constant *C = CP->get();
477 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
479 Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
480 CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
484 case ISD::GlobalAddress: {
485 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
486 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
487 SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
488 CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
489 Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
493 /* XXX case ISD::ExternalSymbol: {
494 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
496 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
497 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
498 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
503 case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
504 case ISD::ZEXTLOAD: {
505 SDOperand Chain, Address;
506 Select(Chain, N->getOperand(0));
507 Select(Address, N->getOperand(1));
509 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
510 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
512 switch (TypeBeingLoaded) {
513 default: N->dump(); assert(0 && "Cannot load this type!");
514 case MVT::i1: { // this is a bool
515 Opc = IA64::LD1; // first we load a byte, then compare for != 0
516 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
517 Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
518 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
519 CurDAG->getRegister(IA64::r0, MVT::i64),
520 Chain).getValue(Op.ResNo);
523 /* otherwise, we want to load a bool into something bigger: LD1
524 will do that for us, so we just fall through */
526 case MVT::i8: Opc = IA64::LD1; break;
527 case MVT::i16: Opc = IA64::LD2; break;
528 case MVT::i32: Opc = IA64::LD4; break;
529 case MVT::i64: Opc = IA64::LD8; break;
531 case MVT::f32: Opc = IA64::LDF4; break;
532 case MVT::f64: Opc = IA64::LDF8; break;
535 // TODO: comment this
536 Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
537 Address, Chain).getValue(Op.ResNo);
541 case ISD::TRUNCSTORE:
543 SDOperand Address, Chain;
544 Select(Address, N->getOperand(2));
545 Select(Chain, N->getOperand(0));
548 if (N->getOpcode() == ISD::STORE) {
549 switch (N->getOperand(1).getValueType()) {
550 default: assert(0 && "unknown type in store");
551 case MVT::i1: { // this is a bool
552 Opc = IA64::ST1; // we store either 0 or 1 as a byte
554 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
555 Chain = Initial.getValue(1);
556 // then load 1 into the same reg iff the predicate to store is 1
558 Select(Tmp, N->getOperand(1));
559 Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
560 CurDAG->getConstant(1, MVT::i64),
562 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
565 case MVT::i64: Opc = IA64::ST8; break;
566 case MVT::f64: Opc = IA64::STF8; break;
568 } else { //ISD::TRUNCSTORE
569 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
570 default: assert(0 && "unknown type in truncstore");
571 case MVT::i8: Opc = IA64::ST1; break;
572 case MVT::i16: Opc = IA64::ST2; break;
573 case MVT::i32: Opc = IA64::ST4; break;
574 case MVT::f32: Opc = IA64::STF4; break;
579 Select(N1, N->getOperand(1));
580 Select(N2, N->getOperand(2));
581 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
587 Select(Chain, N->getOperand(0));
588 Select(CC, N->getOperand(1));
589 MachineBasicBlock *Dest =
590 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
591 //FIXME - we do NOT need long branches all the time
592 Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
593 CurDAG->getBasicBlock(Dest), Chain);
597 case ISD::CALLSEQ_START:
598 case ISD::CALLSEQ_END: {
599 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
600 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
601 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
603 Select(N0, N->getOperand(0));
604 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
609 // FIXME: we don't need long branches all the time!
611 Select(N0, N->getOperand(0));
612 Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
613 N->getOperand(1), N0);
617 SelectCode(Result, Op);
621 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
622 /// into an IA64-specific DAG, ready for instruction scheduling.
625 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
626 return new IA64DAGToDAGISel(TM);