1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
34 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
35 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
37 //===--------------------------------------------------------------------===//
38 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
39 /// instructions for SelectionDAG operations.
41 class IA64DAGToDAGISel : public SelectionDAGISel {
42 IA64TargetLowering IA64Lowering;
43 unsigned GlobalBaseReg;
45 IA64DAGToDAGISel(TargetMachine &TM)
46 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
48 virtual bool runOnFunction(Function &Fn) {
49 // Make sure we re-emit a set of the global base reg if necessary
51 return SelectionDAGISel::runOnFunction(Fn);
54 /// getI64Imm - Return a target constant with the specified value, of type
56 inline SDOperand getI64Imm(uint64_t Imm) {
57 return CurDAG->getTargetConstant(Imm, MVT::i64);
60 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
61 /// base register. Return the virtual register that holds this value.
62 // SDOperand getGlobalBaseReg(); TODO: hmm
64 // Select - Convert the specified operand from a target-independent to a
65 // target-specific node if it hasn't already been changed.
66 SDOperand Select(SDOperand Op);
68 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
69 unsigned OCHi, unsigned OCLo,
70 bool IsArithmetic = false,
72 SDNode *SelectBitfieldInsert(SDNode *N);
74 /// SelectCC - Select a comparison of the specified values with the
75 /// specified condition code, returning the CR# of the expression.
76 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
78 /// SelectAddr - Given the specified address, return the two operands for a
79 /// load/store instruction, and return true if it should be an indexed [r+r]
81 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
83 SDOperand BuildSDIVSequence(SDNode *N);
84 SDOperand BuildUDIVSequence(SDNode *N);
86 /// InstructionSelectBasicBlock - This callback is invoked by
87 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
88 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
90 virtual const char *getPassName() const {
91 return "IA64 (Itanium) DAG->DAG Instruction Selector";
94 // Include the pieces autogenerated from the target description.
95 #include "IA64GenDAGISel.inc"
98 SDOperand SelectDIV(SDOperand Op);
102 /// InstructionSelectBasicBlock - This callback is invoked by
103 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
104 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
107 // The selection process is inherently a bottom-up recursive process (users
108 // select their uses before themselves). Given infinite stack space, we
109 // could just start selecting on the root and traverse the whole graph. In
110 // practice however, this causes us to run out of stack space on large basic
111 // blocks. To avoid this problem, select the entry node, then all its uses,
112 // iteratively instead of recursively.
113 std::vector<SDOperand> Worklist;
114 Worklist.push_back(DAG.getEntryNode());
116 // Note that we can do this in the IA64 target (scanning forward across token
117 // chain edges) because no nodes ever get folded across these edges. On a
118 // target like X86 which supports load/modify/store operations, this would
119 // have to be more careful.
120 while (!Worklist.empty()) {
121 SDOperand Node = Worklist.back();
124 // Chose from the least deep of the top two nodes.
125 if (!Worklist.empty() &&
126 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
127 std::swap(Worklist.back(), Node);
129 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
130 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
131 CodeGenMap.count(Node)) continue;
133 for (SDNode::use_iterator UI = Node.Val->use_begin(),
134 E = Node.Val->use_end(); UI != E; ++UI) {
135 // Scan the values. If this use has a value that is a token chain, add it
138 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
139 if (User->getValueType(i) == MVT::Other) {
140 Worklist.push_back(SDOperand(User, i));
145 // Finally, legalize this node.
149 // Select target instructions for the DAG.
150 DAG.setRoot(SelectRoot(DAG.getRoot()));
152 DAG.RemoveDeadNodes();
154 // Emit machine code to BB.
155 ScheduleAndEmitDAG(DAG);
158 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
160 SDOperand Chain = Select(N->getOperand(0));
162 SDOperand Tmp1 = Select(N->getOperand(0));
163 SDOperand Tmp2 = Select(N->getOperand(1));
167 if(MVT::isFloatingPoint(Tmp1.getValueType()))
170 bool isModulus=false; // is it a division or a modulus?
173 switch(N->getOpcode()) {
175 case ISD::SDIV: isModulus=false; isSigned=true; break;
176 case ISD::UDIV: isModulus=false; isSigned=false; break;
178 case ISD::SREM: isModulus=true; isSigned=true; break;
179 case ISD::UREM: isModulus=true; isSigned=false; break;
182 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
184 SDOperand TmpPR, TmpPR2;
185 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
186 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
189 // we'll need copies of F0 and F1
190 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
191 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
193 // OK, emit some code:
196 // first, load the inputs into FP regs.
197 TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
198 Chain = TmpF1.getValue(1);
199 TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
200 Chain = TmpF2.getValue(1);
202 // next, convert the inputs to FP
204 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
205 Chain = TmpF3.getValue(1);
206 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
207 Chain = TmpF4.getValue(1);
208 } else { // is unsigned
209 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
210 Chain = TmpF3.getValue(1);
211 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
212 Chain = TmpF4.getValue(1);
215 } else { // this is an FP divide/remainder, so we 'leak' some temp
216 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
221 // we start by computing an approximate reciprocal (good to 9 bits?)
222 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
224 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
227 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
230 TmpPR = TmpF5.getValue(1);
231 Chain = TmpF5.getValue(2);
234 if(isModulus) { // for remainders, it'll be handy to have
235 // copies of -input_b
236 minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
237 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
238 Chain = minusB.getValue(1);
241 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
243 TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
244 TmpF4, TmpF5, F1, TmpPR);
245 Chain = TmpE0.getValue(1);
246 TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
247 TmpF5, TmpE0, TmpF5, TmpPR);
248 Chain = TmpY1.getValue(1);
249 TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
250 TmpE0, TmpE0, F0, TmpPR);
251 Chain = TmpE1.getValue(1);
252 TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
253 TmpY1, TmpE1, TmpY1, TmpPR);
254 Chain = TmpY2.getValue(1);
256 if(isFP) { // if this is an FP divide, we finish up here and exit early
258 assert(0 && "Sorry, try another FORTRAN compiler.");
260 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
262 TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
263 TmpE1, TmpE1, F0, TmpPR);
264 Chain = TmpE2.getValue(1);
265 TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
266 TmpY2, TmpE2, TmpY2, TmpPR);
267 Chain = TmpY3.getValue(1);
268 TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
269 Tmp1, TmpY3, F0, TmpPR);
270 Chain = TmpQ0.getValue(1);
271 TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
272 Tmp2, TmpQ0, Tmp1, TmpPR);
273 Chain = TmpR0.getValue(1);
275 // we want Result to have the same target register as the frcpa, so
276 // we two-address hack it. See the comment "for this to work..." on
277 // page 48 of Intel application note #245415
278 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
279 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
280 Chain = Result.getValue(1);
281 return Result; // XXX: early exit!
282 } else { // this is *not* an FP divide, so there's a bit left to do:
284 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
286 TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
287 TmpF3, TmpY2, F0, TmpPR);
288 Chain = TmpQ2.getValue(1);
289 TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
290 TmpF4, TmpQ2, TmpF3, TmpPR);
291 Chain = TmpR2.getValue(1);
293 // we want TmpQ3 to have the same target register as the frcpa? maybe we
294 // should two-address hack it. See the comment "for this to work..." on page
295 // 48 of Intel application note #245415
296 TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
297 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
298 Chain = TmpQ3.getValue(1);
300 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
301 // the FPSWA won't be able to help out in the case of large/tiny
302 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
305 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
307 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3);
309 Chain = TmpQ.getValue(1);
312 SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64,
314 Chain = FPminusB.getValue(1);
315 SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
316 TmpQ, FPminusB, TmpF1);
317 Chain = Remainder.getValue(1);
318 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
319 Chain = Result.getValue(1);
320 } else { // just an integer divide
321 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
322 Chain = Result.getValue(1);
326 } // wasn't an FP divide
329 // Select - Convert the specified operand from a target-independent to a
330 // target-specific node if it hasn't already been changed.
331 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
333 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
334 N->getOpcode() < IA64ISD::FIRST_NUMBER)
335 return Op; // Already selected.
337 // If this has already been converted, use it.
338 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
339 if (CGMI != CodeGenMap.end()) return CGMI->second;
341 switch (N->getOpcode()) {
344 case IA64ISD::BRCALL: { // XXX: this is also a hack!
345 SDOperand Chain = Select(N->getOperand(0));
346 SDOperand InFlag; // Null incoming flag value.
348 if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
349 InFlag = Select(N->getOperand(2));
352 SDOperand CallOperand;
354 // if we can call directly, do so
355 if (GlobalAddressSDNode *GASD =
356 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
357 CallOpcode = IA64::BRCALL_IPREL_GA;
358 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
359 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
360 // case for correctness, to avoid
361 // "non-pic code with imm reloc.n
362 // against dynamic symbol" errors
363 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
364 CallOpcode = IA64::BRCALL_IPREL_ES;
365 CallOperand = N->getOperand(1);
367 // otherwise we need to load the function descriptor,
368 // load the branch target (function)'s entry point and GP,
369 // branch (call) then restore the GP
370 SDOperand FnDescriptor = Select(N->getOperand(1));
372 // load the branch target's entry point [mem] and
374 SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
376 Chain = targetEntryPoint.getValue(1);
377 SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
378 FnDescriptor, CurDAG->getConstant(8, MVT::i64));
379 Chain = targetGPAddr.getValue(1);
380 SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
382 Chain = targetGP.getValue(1);
384 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
385 InFlag = Chain.getValue(1);
386 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
387 InFlag = Chain.getValue(1);
389 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
390 CallOpcode = IA64::BRCALL_INDIRECT;
393 // Finally, once everything is setup, emit the call itself
395 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag);
396 else // there might be no arguments
397 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain);
398 InFlag = Chain.getValue(1);
400 std::vector<SDOperand> CallResults;
402 CallResults.push_back(Chain);
403 CallResults.push_back(InFlag);
405 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
406 CodeGenMap[Op.getValue(i)] = CallResults[i];
407 return CallResults[Op.ResNo];
410 case IA64ISD::GETFD: {
411 SDOperand Input = Select(N->getOperand(0));
412 SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
413 CodeGenMap[Op] = Result;
421 case ISD::UREM: return SelectDIV(Op);
423 case ISD::TargetConstantFP: {
424 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
426 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
427 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
428 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
429 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
431 assert(0 && "Unexpected FP constant!");
434 case ISD::FrameIndex: { // TODO: reduce creepyness
435 int FI = cast<FrameIndexSDNode>(N)->getIndex();
437 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
438 CurDAG->getTargetFrameIndex(FI, MVT::i64));
440 return CodeGenMap[Op] = CurDAG->getTargetNode(IA64::MOV, MVT::i64,
441 CurDAG->getTargetFrameIndex(FI, MVT::i64));
444 case ISD::ConstantPool: { // TODO: nuke the constant pool
445 // (ia64 doesn't need one)
446 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
447 Constant *C = CP->get();
448 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
450 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
451 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
454 case ISD::GlobalAddress: {
455 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
456 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
457 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
458 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
459 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
462 /* XXX case ISD::ExternalSymbol: {
463 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
465 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
466 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
467 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
472 case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
473 case ISD::ZEXTLOAD: {
474 SDOperand Chain = Select(N->getOperand(0));
475 SDOperand Address = Select(N->getOperand(1));
477 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
478 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
480 switch (TypeBeingLoaded) {
481 default: N->dump(); assert(0 && "Cannot load this type!");
482 case MVT::i1: { // this is a bool
483 Opc = IA64::LD1; // first we load a byte, then compare for != 0
484 if(N->getValueType(0) == MVT::i1) // XXX: early exit!
485 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
486 CurDAG->getTargetNode(Opc, MVT::i64, Address),
487 CurDAG->getRegister(IA64::r0, MVT::i64),
488 Chain).getValue(Op.ResNo);
489 /* otherwise, we want to load a bool into something bigger: LD1
490 will do that for us, so we just fall through */
492 case MVT::i8: Opc = IA64::LD1; break;
493 case MVT::i16: Opc = IA64::LD2; break;
494 case MVT::i32: Opc = IA64::LD4; break;
495 case MVT::i64: Opc = IA64::LD8; break;
497 case MVT::f32: Opc = IA64::LDF4; break;
498 case MVT::f64: Opc = IA64::LDF8; break;
501 // TODO: comment this
502 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
503 Address, Chain).getValue(Op.ResNo);
506 case ISD::TRUNCSTORE:
508 SDOperand Address = Select(N->getOperand(2));
509 SDOperand Chain = Select(N->getOperand(0));
512 if (N->getOpcode() == ISD::STORE) {
513 switch (N->getOperand(1).getValueType()) {
514 default: assert(0 && "unknown type in store");
515 case MVT::i1: { // this is a bool
516 Opc = IA64::ST1; // we store either 0 or 1 as a byte
518 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
519 Chain = Initial.getValue(1);
520 // then load 1 into the same reg iff the predicate to store is 1
522 CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
523 CurDAG->getConstant(1, MVT::i64),
524 Select(N->getOperand(1)));
525 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
527 case MVT::i64: Opc = IA64::ST8; break;
528 case MVT::f64: Opc = IA64::STF8; break;
530 } else { //ISD::TRUNCSTORE
531 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
532 default: assert(0 && "unknown type in truncstore");
533 case MVT::i8: Opc = IA64::ST1; break;
534 case MVT::i16: Opc = IA64::ST2; break;
535 case MVT::i32: Opc = IA64::ST4; break;
536 case MVT::f32: Opc = IA64::STF4; break;
540 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
541 Select(N->getOperand(1)), Chain);
545 SDOperand Chain = Select(N->getOperand(0));
546 SDOperand CC = Select(N->getOperand(1));
547 MachineBasicBlock *Dest =
548 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
549 //FIXME - we do NOT need long branches all the time
550 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
551 CurDAG->getBasicBlock(Dest), Chain);
554 case ISD::CALLSEQ_START:
555 case ISD::CALLSEQ_END: {
556 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
557 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
558 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
559 return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
560 getI64Imm(Amt), Select(N->getOperand(0)));
564 // FIXME: we don't need long branches all the time!
565 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
566 N->getOperand(1), Select(N->getOperand(0)));
569 return SelectCode(Op);
573 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
574 /// into an IA64-specific DAG, ready for instruction scheduling.
576 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
577 return new IA64DAGToDAGISel(TM);