1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Constants.h"
25 #include "llvm/GlobalValue.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
33 //===--------------------------------------------------------------------===//
34 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
35 /// instructions for SelectionDAG operations.
37 class IA64DAGToDAGISel : public SelectionDAGISel {
38 unsigned GlobalBaseReg;
40 explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
41 : SelectionDAGISel(TM) {}
43 virtual bool runOnFunction(Function &Fn) {
44 // Make sure we re-emit a set of the global base reg if necessary
46 return SelectionDAGISel::runOnFunction(Fn);
49 /// getI64Imm - Return a target constant with the specified value, of type
51 inline SDValue getI64Imm(uint64_t Imm) {
52 return CurDAG->getTargetConstant(Imm, MVT::i64);
55 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
56 /// base register. Return the virtual register that holds this value.
57 // SDValue getGlobalBaseReg(); TODO: hmm
59 // Select - Convert the specified operand from a target-independent to a
60 // target-specific node if it hasn't already been changed.
61 SDNode *Select(SDValue N);
63 SDNode *SelectIntImmediateExpr(SDValue LHS, SDValue RHS,
64 unsigned OCHi, unsigned OCLo,
65 bool IsArithmetic = false,
67 SDNode *SelectBitfieldInsert(SDNode *N);
69 /// SelectCC - Select a comparison of the specified values with the
70 /// specified condition code, returning the CR# of the expression.
71 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
73 /// SelectAddr - Given the specified address, return the two operands for a
74 /// load/store instruction, and return true if it should be an indexed [r+r]
76 bool SelectAddr(SDValue Addr, SDValue &Op1, SDValue &Op2);
78 /// InstructionSelect - This callback is invoked by
79 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
80 virtual void InstructionSelect();
82 virtual const char *getPassName() const {
83 return "IA64 (Itanium) DAG->DAG Instruction Selector";
86 // Include the pieces autogenerated from the target description.
87 #include "IA64GenDAGISel.inc"
90 SDNode *SelectDIV(SDValue Op);
94 /// InstructionSelect - This callback is invoked by
95 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
96 void IA64DAGToDAGISel::InstructionSelect() {
99 // Select target instructions for the DAG.
101 CurDAG->RemoveDeadNodes();
104 SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
105 SDNode *N = Op.getNode();
106 SDValue Chain = N->getOperand(0);
107 SDValue Tmp1 = N->getOperand(0);
108 SDValue Tmp2 = N->getOperand(1);
112 if(Tmp1.getValueType().isFloatingPoint())
115 bool isModulus=false; // is it a division or a modulus?
118 switch(N->getOpcode()) {
120 case ISD::SDIV: isModulus=false; isSigned=true; break;
121 case ISD::UDIV: isModulus=false; isSigned=false; break;
123 case ISD::SREM: isModulus=true; isSigned=true; break;
124 case ISD::UREM: isModulus=true; isSigned=false; break;
127 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
129 SDValue TmpPR, TmpPR2;
130 SDValue TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
131 SDValue TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
134 // we'll need copies of F0 and F1
135 SDValue F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
136 SDValue F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
138 // OK, emit some code:
141 // first, load the inputs into FP regs.
143 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
144 Chain = TmpF1.getValue(1);
146 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
147 Chain = TmpF2.getValue(1);
149 // next, convert the inputs to FP
152 SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
153 Chain = TmpF3.getValue(1);
155 SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
156 Chain = TmpF4.getValue(1);
157 } else { // is unsigned
159 SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
160 Chain = TmpF3.getValue(1);
162 SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
163 Chain = TmpF4.getValue(1);
166 } else { // this is an FP divide/remainder, so we 'leak' some temp
167 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
172 // we start by computing an approximate reciprocal (good to 9 bits?)
173 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
175 TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
178 TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
181 TmpPR = TmpF5.getValue(1);
182 Chain = TmpF5.getValue(2);
185 if(isModulus) { // for remainders, it'll be handy to have
186 // copies of -input_b
187 minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
188 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
189 Chain = minusB.getValue(1);
192 SDValue TmpE0, TmpY1, TmpE1, TmpY2;
194 SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
195 TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
197 Chain = TmpE0.getValue(1);
198 SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
199 TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
201 Chain = TmpY1.getValue(1);
202 SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
203 TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
205 Chain = TmpE1.getValue(1);
206 SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
207 TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
209 Chain = TmpY2.getValue(1);
211 if(isFP) { // if this is an FP divide, we finish up here and exit early
213 assert(0 && "Sorry, try another FORTRAN compiler.");
215 SDValue TmpE2, TmpY3, TmpQ0, TmpR0;
217 SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
218 TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
220 Chain = TmpE2.getValue(1);
221 SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
222 TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
224 Chain = TmpY3.getValue(1);
225 SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
227 SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
229 Chain = TmpQ0.getValue(1);
230 SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
232 SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
234 Chain = TmpR0.getValue(1);
236 // we want Result to have the same target register as the frcpa, so
237 // we two-address hack it. See the comment "for this to work..." on
238 // page 48 of Intel application note #245415
239 SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
240 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
242 Chain = SDValue(Result, 1);
243 return Result; // XXX: early exit!
244 } else { // this is *not* an FP divide, so there's a bit left to do:
246 SDValue TmpQ2, TmpR2, TmpQ3, TmpQ;
248 SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
249 TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
251 Chain = TmpQ2.getValue(1);
252 SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
253 TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
255 Chain = TmpR2.getValue(1);
257 // we want TmpQ3 to have the same target register as the frcpa? maybe we
258 // should two-address hack it. See the comment "for this to work..." on page
259 // 48 of Intel application note #245415
260 SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
261 TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
263 Chain = TmpQ3.getValue(1);
265 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
266 // the FPSWA won't be able to help out in the case of large/tiny
267 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
270 TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
271 MVT::f64, TmpQ3), 0);
273 TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
274 MVT::f64, TmpQ3), 0);
276 Chain = TmpQ.getValue(1);
280 SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
281 Chain = FPminusB.getValue(1);
283 SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
284 TmpQ, FPminusB, TmpF1), 0);
285 Chain = Remainder.getValue(1);
286 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
287 Chain = SDValue(Result, 1);
288 } else { // just an integer divide
289 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
290 Chain = SDValue(Result, 1);
294 } // wasn't an FP divide
297 // Select - Convert the specified operand from a target-independent to a
298 // target-specific node if it hasn't already been changed.
299 SDNode *IA64DAGToDAGISel::Select(SDValue Op) {
300 SDNode *N = Op.getNode();
301 if (N->isMachineOpcode())
302 return NULL; // Already selected.
303 DebugLoc dl = Op.getDebugLoc();
305 switch (N->getOpcode()) {
308 case IA64ISD::BRCALL: { // XXX: this is also a hack!
309 SDValue Chain = N->getOperand(0);
310 SDValue InFlag; // Null incoming flag value.
312 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
313 InFlag = N->getOperand(2);
319 // if we can call directly, do so
320 if (GlobalAddressSDNode *GASD =
321 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
322 CallOpcode = IA64::BRCALL_IPREL_GA;
323 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
324 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
325 // FIXME: we currently NEED this case for correctness, to avoid
326 // "non-pic code with imm reloc.n against dynamic symbol" errors
327 CallOpcode = IA64::BRCALL_IPREL_ES;
328 CallOperand = N->getOperand(1);
330 // otherwise we need to load the function descriptor,
331 // load the branch target (function)'s entry point and GP,
332 // branch (call) then restore the GP
333 SDValue FnDescriptor = N->getOperand(1);
335 // load the branch target's entry point [mem] and
337 SDValue targetEntryPoint=
338 SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other,
339 FnDescriptor, CurDAG->getEntryNode()), 0);
340 Chain = targetEntryPoint.getValue(1);
341 SDValue targetGPAddr=
342 SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64,
344 CurDAG->getConstant(8, MVT::i64)), 0);
345 Chain = targetGPAddr.getValue(1);
347 SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other,
348 targetGPAddr, CurDAG->getEntryNode()), 0);
349 Chain = targetGP.getValue(1);
351 Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag);
352 InFlag = Chain.getValue(1);
353 Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6,
354 targetEntryPoint, InFlag); // FLAG these?
355 InFlag = Chain.getValue(1);
357 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
358 CallOpcode = IA64::BRCALL_INDIRECT;
361 // Finally, once everything is setup, emit the call itself
362 if (InFlag.getNode())
363 Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
364 MVT::Flag, CallOperand, InFlag), 0);
365 else // there might be no arguments
366 Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other,
367 MVT::Flag, CallOperand, Chain), 0);
368 InFlag = Chain.getValue(1);
370 std::vector<SDValue> CallResults;
372 CallResults.push_back(Chain);
373 CallResults.push_back(InFlag);
375 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
376 ReplaceUses(Op.getValue(i), CallResults[i]);
380 case IA64ISD::GETFD: {
381 SDValue Input = N->getOperand(0);
382 return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input);
390 return SelectDIV(Op);
392 case ISD::TargetConstantFP: {
393 SDValue Chain = CurDAG->getEntryNode(); // this is a constant, so..
396 ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
397 if (N2->getValueAPF().isPosZero()) {
398 V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64);
399 } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
400 APFloat(+1.0f) : APFloat(+1.0))) {
401 V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64);
403 assert(0 && "Unexpected FP constant!");
405 ReplaceUses(SDValue(N, 0), V);
409 case ISD::FrameIndex: { // TODO: reduce creepyness
410 int FI = cast<FrameIndexSDNode>(N)->getIndex();
412 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
413 CurDAG->getTargetFrameIndex(FI, MVT::i64));
415 return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64,
416 CurDAG->getTargetFrameIndex(FI, MVT::i64));
419 case ISD::ConstantPool: { // TODO: nuke the constant pool
420 // (ia64 doesn't need one)
421 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
422 Constant *C = CP->getConstVal();
423 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
425 return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ?
426 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
429 case ISD::GlobalAddress: {
430 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
431 SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
433 SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64,
434 CurDAG->getRegister(IA64::r1,
436 return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp,
437 CurDAG->getEntryNode());
441 case ISD::ExternalSymbol: {
442 SDValue EA = CurDAG->getTargetExternalSymbol(
443 cast<ExternalSymbolSDNode>(N)->getSymbol(),
445 SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64,
446 CurDAG->getRegister(IA64::r1,
449 return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp);
453 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
454 LoadSDNode *LD = cast<LoadSDNode>(N);
455 SDValue Chain = LD->getChain();
456 SDValue Address = LD->getBasePtr();
458 MVT TypeBeingLoaded = LD->getMemoryVT();
460 switch (TypeBeingLoaded.getSimpleVT()) {
465 assert(0 && "Cannot load this type!");
466 case MVT::i1: { // this is a bool
467 Opc = IA64::LD1; // first we load a byte, then compare for != 0
468 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
469 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
470 SDValue(CurDAG->getTargetNode(Opc, dl,
473 CurDAG->getRegister(IA64::r0, MVT::i64),
476 /* otherwise, we want to load a bool into something bigger: LD1
477 will do that for us, so we just fall through */
479 case MVT::i8: Opc = IA64::LD1; break;
480 case MVT::i16: Opc = IA64::LD2; break;
481 case MVT::i32: Opc = IA64::LD4; break;
482 case MVT::i64: Opc = IA64::LD8; break;
484 case MVT::f32: Opc = IA64::LDF4; break;
485 case MVT::f64: Opc = IA64::LDF8; break;
488 // TODO: comment this
489 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
494 StoreSDNode *ST = cast<StoreSDNode>(N);
495 SDValue Address = ST->getBasePtr();
496 SDValue Chain = ST->getChain();
499 if (ISD::isNON_TRUNCStore(N)) {
500 switch (N->getOperand(1).getValueType().getSimpleVT()) {
501 default: assert(0 && "unknown type in store");
502 case MVT::i1: { // this is a bool
503 Opc = IA64::ST1; // we store either 0 or 1 as a byte
505 SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64);
506 Chain = Initial.getValue(1);
507 // then load 1 into the same reg iff the predicate to store is 1
508 SDValue Tmp = ST->getValue();
510 SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial,
511 CurDAG->getTargetConstant(1,
514 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
516 case MVT::i64: Opc = IA64::ST8; break;
517 case MVT::f64: Opc = IA64::STF8; break;
519 } else { // Truncating store
520 switch(ST->getMemoryVT().getSimpleVT()) {
521 default: assert(0 && "unknown type in truncstore");
522 case MVT::i8: Opc = IA64::ST1; break;
523 case MVT::i16: Opc = IA64::ST2; break;
524 case MVT::i32: Opc = IA64::ST4; break;
525 case MVT::f32: Opc = IA64::STF4; break;
529 SDValue N1 = N->getOperand(1);
530 SDValue N2 = N->getOperand(2);
531 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
535 SDValue Chain = N->getOperand(0);
536 SDValue CC = N->getOperand(1);
537 MachineBasicBlock *Dest =
538 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
539 //FIXME - we do NOT need long branches all the time
540 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
541 CurDAG->getBasicBlock(Dest), Chain);
544 case ISD::CALLSEQ_START:
545 case ISD::CALLSEQ_END: {
546 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
547 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
548 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
549 SDValue N0 = N->getOperand(0);
550 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
554 // FIXME: we don't need long branches all the time!
555 SDValue N0 = N->getOperand(0);
556 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
557 N->getOperand(1), N0);
560 return SelectCode(Op);
564 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
565 /// into an IA64-specific DAG, ready for instruction scheduling.
568 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
569 return new IA64DAGToDAGISel(TM);