1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 IA64DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
88 virtual const char *getPassName() const {
89 return "IA64 (Itanium) DAG->DAG Instruction Selector";
92 // Include the pieces autogenerated from the target description.
93 #include "IA64GenDAGISel.inc"
96 SDOperand SelectDIV(SDOperand Op);
97 SDOperand SelectCALL(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
106 // The selection process is inherently a bottom-up recursive process (users
107 // select their uses before themselves). Given infinite stack space, we
108 // could just start selecting on the root and traverse the whole graph. In
109 // practice however, this causes us to run out of stack space on large basic
110 // blocks. To avoid this problem, select the entry node, then all its uses,
111 // iteratively instead of recursively.
112 std::vector<SDOperand> Worklist;
113 Worklist.push_back(DAG.getEntryNode());
115 // Note that we can do this in the IA64 target (scanning forward across token
116 // chain edges) because no nodes ever get folded across these edges. On a
117 // target like X86 which supports load/modify/store operations, this would
118 // have to be more careful.
119 while (!Worklist.empty()) {
120 SDOperand Node = Worklist.back();
123 // Chose from the least deep of the top two nodes.
124 if (!Worklist.empty() &&
125 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
126 std::swap(Worklist.back(), Node);
128 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
129 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
130 CodeGenMap.count(Node)) continue;
132 for (SDNode::use_iterator UI = Node.Val->use_begin(),
133 E = Node.Val->use_end(); UI != E; ++UI) {
134 // Scan the values. If this use has a value that is a token chain, add it
137 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
138 if (User->getValueType(i) == MVT::Other) {
139 Worklist.push_back(SDOperand(User, i));
144 // Finally, legalize this node.
148 // Select target instructions for the DAG.
149 DAG.setRoot(Select(DAG.getRoot()));
151 DAG.RemoveDeadNodes();
153 // Emit machine code to BB.
154 ScheduleAndEmitDAG(DAG);
157 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
159 SDOperand Chain = Select(N->getOperand(0));
161 SDOperand Tmp1 = Select(N->getOperand(0));
162 SDOperand Tmp2 = Select(N->getOperand(1));
166 if(MVT::isFloatingPoint(Tmp1.getValueType()))
169 bool isModulus=false; // is it a division or a modulus?
172 switch(N->getOpcode()) {
174 case ISD::SDIV: isModulus=false; isSigned=true; break;
175 case ISD::UDIV: isModulus=false; isSigned=false; break;
177 case ISD::SREM: isModulus=true; isSigned=true; break;
178 case ISD::UREM: isModulus=true; isSigned=false; break;
181 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
183 SDOperand TmpPR, TmpPR2;
184 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
185 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
188 // OK, emit some code:
191 // first, load the inputs into FP regs.
192 TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
193 Chain = TmpF1.getValue(1);
194 TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
195 Chain = TmpF2.getValue(1);
197 // next, convert the inputs to FP
199 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
200 Chain = TmpF3.getValue(1);
201 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
202 Chain = TmpF4.getValue(1);
204 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
205 Chain = TmpF3.getValue(1);
206 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
207 Chain = TmpF4.getValue(1);
210 } else { // this is an FP divide/remainder, so we 'leak' some temp
211 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
216 // we start by computing an approximate reciprocal (good to 9 bits?)
217 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
218 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
220 TmpPR = TmpF5.getValue(1);
221 Chain = TmpF5.getValue(2);
223 if(!isModulus) { // if this is a divide, we worry about div-by-zero
224 SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
225 CurDAG->getRegister(IA64::r0, MVT::i64),
226 CurDAG->getRegister(IA64::r0, MVT::i64));
227 Chain = bogusPR.getValue(1);
228 TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
229 CurDAG->getRegister(IA64::r0, MVT::i64),
230 CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
231 Chain = TmpPR2.getValue(1);
234 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
235 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
237 // now we apply newton's method, thrice! (FIXME: this is ~72 bits of
238 // precision, don't need this much for f32/i32)
239 TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
240 TmpF4, TmpF5, F1, TmpPR);
241 Chain = TmpF6.getValue(1);
242 TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
243 TmpF3, TmpF5, F0, TmpPR);
244 Chain = TmpF7.getValue(1);
245 TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
246 TmpF6, TmpF6, F0, TmpPR);
247 Chain = TmpF8.getValue(1);
248 TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
249 TmpF6, TmpF7, TmpF7, TmpPR);
250 Chain = TmpF9.getValue(1);
251 TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
252 TmpF6, TmpF5, TmpF5, TmpPR);
253 Chain = TmpF10.getValue(1);
254 TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
255 TmpF8, TmpF9, TmpF9, TmpPR);
256 Chain = TmpF11.getValue(1);
257 TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
258 TmpF8, TmpF10, TmpF10, TmpPR);
259 Chain = TmpF12.getValue(1);
260 TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
261 TmpF4, TmpF11, TmpF3, TmpPR);
262 Chain = TmpF13.getValue(1);
264 // FIXME: this is unfortunate :(
265 // the story is that the dest reg of the fnma above and the fma below
266 // (and therefore possibly the src of the fcvt.fx[u] as well) cannot
267 // be the same register, or this code breaks if the first argument is
268 // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
269 TmpF14 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
270 TmpF13, TmpF12, TmpF11, TmpPR);
271 Chain = TmpF14.getValue(1);
273 if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
274 SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpF13); // hack :(
275 Chain = bogus.getValue(0); // hmmm
279 // round to an integer
281 TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::i64, TmpF14);
282 Chain = TmpF15.getValue(1);
285 TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::i64, TmpF14);
286 Chain = TmpF15.getValue(1);
290 // EXERCISE: can you see why TmpF15=TmpF14 does not work here, and
291 // we really do need the above FMOV? ;)
295 if(isFP) { // extra worrying about div-by-zero
296 // we do a 'conditional fmov' (of the correct result, depending
297 // on how the frcpa predicate turned out)
298 SDOperand bogoResult = CurDAG->getTargetNode(IA64::PFMOV, MVT::f64,
300 Chain = bogoResult.getValue(1);
301 Result = CurDAG->getTargetNode(IA64::CFMOV, MVT::f64, bogoResult,
303 Chain = Result.getValue(1);
306 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpF15);
307 Chain = Result.getValue(1);
309 } else { // this is a modulus
311 // answer = q * (-b) + a
312 SDOperand TmpI = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
313 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
314 Chain = TmpI.getValue(1);
315 SDOperand TmpF = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, TmpI);
316 Chain = TmpF.getValue(1);
317 SDOperand ModulusResult = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
318 TmpF15, TmpF, TmpF1);
319 Chain = ModulusResult.getValue(1);
320 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, ModulusResult);
321 Chain = Result.getValue(1);
322 } else { // FP modulus! The horror... the horror....
323 assert(0 && "sorry, no FP modulus just yet!\n!\n");
331 SDOperand IA64DAGToDAGISel::SelectCALL(SDOperand Op) {
333 SDOperand Chain = Select(N->getOperand(0));
336 std::vector<SDOperand> CallOperands;
338 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
339 SDOperand GPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r1, MVT::i64);
340 Chain = GPBeforeCall.getValue(1);
341 SDOperand SPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
342 Chain = SPBeforeCall.getValue(1);
343 SDOperand RPBeforeCall = CurDAG->getCopyFromReg(Chain, IA64::rp, MVT::i64);
344 Chain = RPBeforeCall.getValue(1);
346 // if we can call directly, do so
347 if (GlobalAddressSDNode *GASD =
348 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
349 CallOpcode = IA64::BRCALL_IPREL;
350 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(),
352 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
353 // case for correctness, to avoid
354 // "non-pic code with imm reloc.n
355 // against dynamic symbol" errors
356 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
357 CallOpcode = IA64::BRCALL_IPREL;
358 CallOperands.push_back(N->getOperand(1));
360 // otherwise we need to load the function descriptor,
361 // load the branch target (function)'s entry point and GP,
362 // branch (call) then restore the GP
364 SDOperand FnDescriptor = Select(N->getOperand(1));
366 // load the branch target's entry point [mem] and
368 SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
370 Chain = targetEntryPoint.getValue(1);
371 SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
372 FnDescriptor, CurDAG->getConstant(8, MVT::i64));
373 Chain = targetGPAddr.getValue(1);
374 SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
376 Chain = targetGP.getValue(1);
378 /* FIXME? (methcall still fails)
379 SDOperand targetEntryPoint=CurDAG->getLoad(MVT::i64, Chain, FnDescriptor,
380 CurDAG->getSrcValue(0));
381 SDOperand targetGPAddr=CurDAG->getNode(ISD::ADD, MVT::i64, FnDescriptor,
382 CurDAG->getConstant(8, MVT::i64));
383 SDOperand targetGP=CurDAG->getLoad(MVT::i64, Chain, targetGPAddr,
384 CurDAG->getSrcValue(0));
387 /* this is just the long way of writing the two lines below?
388 // Copy the callee GP into r1
389 SDOperand r1 = CurDAG->getRegister(IA64::r1, MVT::i64);
390 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, r1,
394 // Copy the callee address into the b6 branch register
395 SDOperand B6 = CurDAG->getRegister(IA64::B6, MVT::i64);
396 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::i64, Chain, B6,
400 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP);
401 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint);
403 CallOperands.push_back(CurDAG->getRegister(IA64::B6, MVT::i64));
404 CallOpcode = IA64::BRCALL_INDIRECT;
407 // see section 8.5.8 of "Itanium Software Conventions and
408 // Runtime Architecture Guide to see some examples of what's going
409 // on here. (in short: int args get mapped 1:1 'slot-wise' to out0->out7,
410 // while FP args get mapped to F8->F15 as needed)
412 // TODO: support in-memory arguments
414 unsigned used_FPArgs=0; // how many FP args have been used so far?
416 unsigned intArgs[] = {IA64::out0, IA64::out1, IA64::out2, IA64::out3,
417 IA64::out4, IA64::out5, IA64::out6, IA64::out7 };
418 unsigned FPArgs[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
419 IA64::F12, IA64::F13, IA64::F14, IA64::F15 };
421 SDOperand InFlag; // Null incoming flag value.
423 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) {
424 unsigned DestReg = 0;
425 MVT::ValueType RegTy = N->getOperand(i).getValueType();
426 if (RegTy == MVT::i64) {
427 assert((i-2) < 8 && "Too many int args");
428 DestReg = intArgs[i-2];
430 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) &&
431 "Unpromoted integer arg?");
432 assert(used_FPArgs < 8 && "Too many fp args");
433 DestReg = FPArgs[used_FPArgs++];
436 if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
437 SDOperand Val = Select(N->getOperand(i));
438 if(MVT::isInteger(N->getOperand(i).getValueType())) {
439 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag);
440 InFlag = Chain.getValue(1);
441 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy));
443 // some functions (e.g. printf) want floating point arguments
444 // *also* passed as in-memory representations in integer registers
445 // this is FORTRAN legacy junk which we don't _always_ need
446 // to do, but to be on the safe side, we do.
447 else if(MVT::isFloatingPoint(N->getOperand(i).getValueType())) {
448 assert((i-2) < 8 && "FP args alone would fit, but no int regs left");
449 // first copy into the appropriate FP reg
450 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val);
451 // then copy into the appropriate integer reg
452 DestReg = intArgs[i-2];
453 // GETFD takes an FP reg and writes a GP reg
454 Chain = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Val);
455 // FIXME: this next line is a bit unfortunate
456 Chain = CurDAG->getCopyToReg(Chain, DestReg, Chain, InFlag);
457 InFlag = Chain.getValue(1);
458 CallOperands.push_back(CurDAG->getRegister(DestReg, MVT::i64));
463 // Finally, once everything is in registers to pass to the call, emit the
466 CallOperands.push_back(InFlag); // Strong dep on register copies.
468 CallOperands.push_back(Chain); // Weak dep on whatever occurs before
469 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
472 std::vector<SDOperand> CallResults;
474 // If the call has results, copy the values out of the ret val registers.
475 switch (N->getValueType(0)) {
476 default: assert(0 && "Unexpected ret value!");
477 case MVT::Other: break;
479 // bools are returned as bytes 0/1 in r8
480 SDOperand byteval = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
482 Chain = byteval.getValue(1);
483 Chain = CurDAG->getTargetNode(IA64::CMPNE, MVT::i1, MVT::Other,
484 byteval, CurDAG->getRegister(IA64::r0, MVT::i64)).getValue(1);
485 CallResults.push_back(Chain.getValue(0));
489 Chain = CurDAG->getCopyFromReg(Chain, IA64::r8, MVT::i64,
490 Chain.getValue(1)).getValue(1);
491 CallResults.push_back(Chain.getValue(0));
494 Chain = CurDAG->getCopyFromReg(Chain, IA64::F8, N->getValueType(0),
495 Chain.getValue(1)).getValue(1);
496 CallResults.push_back(Chain.getValue(0));
500 // restore GP, SP and RP - FIXME: this doesn't quite work (e.g.
501 // methcall / objinst both segfault on exit) and it *really*
502 // doesn't work unless you have -sched=none
503 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, GPBeforeCall);
504 Chain = CurDAG->getCopyToReg(Chain, IA64::r12, SPBeforeCall);
505 Chain = CurDAG->getCopyToReg(Chain, IA64::rp, RPBeforeCall);
506 CallResults.push_back(Chain); // llc segfaults w/o this,
507 // ary3(e.g.) SIGILLs with 3
509 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
510 CodeGenMap[Op.getValue(i)] = CallResults[i];
512 return CallResults[Op.ResNo];
515 // Select - Convert the specified operand from a target-independent to a
516 // target-specific node if it hasn't already been changed.
517 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
519 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
520 N->getOpcode() < IA64ISD::FIRST_NUMBER)
521 return Op; // Already selected.
523 // If this has already been converted, use it.
524 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
525 if (CGMI != CodeGenMap.end()) return CGMI->second;
527 switch (N->getOpcode()) {
531 case ISD::TAILCALL: return SelectCALL(Op);
537 case ISD::UREM: return SelectDIV(Op);
539 case ISD::DYNAMIC_STACKALLOC: {
540 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
541 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
542 std::cerr << "Cannot allocate stack object with greater alignment than"
543 << " the stack alignment yet!";
547 SDOperand Chain = Select(N->getOperand(0));
548 SDOperand Amt = Select(N->getOperand(1));
549 SDOperand Reg = CurDAG->getRegister(IA64::r12, MVT::i64);
550 SDOperand Val = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
551 Chain = Val.getValue(1);
553 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
554 // from the stack pointer, giving us the result pointer.
555 SDOperand Result = Select(CurDAG->getNode(ISD::SUB, MVT::i64, Val, Amt));
557 // Copy this result back into r12.
558 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
560 // Copy this result back out of r12 to make sure we're not using the stack
561 // space without decrementing the stack pointer.
562 Result = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
564 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
565 CodeGenMap[Op.getValue(0)] = Result;
566 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
567 return SDOperand(Result.Val, Op.ResNo);
570 case ISD::ConstantFP: {
571 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
573 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
574 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
575 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
576 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
578 assert(0 && "Unexpected FP constant!");
581 case ISD::FrameIndex: { // TODO: reduce creepyness
582 int FI = cast<FrameIndexSDNode>(N)->getIndex();
583 if (N->hasOneUse()) {
584 CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
585 CurDAG->getTargetFrameIndex(FI, MVT::i64));
586 return SDOperand(N, 0);
588 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
589 CurDAG->getTargetFrameIndex(FI, MVT::i64));
592 case ISD::ConstantPool: {
593 Constant *C = cast<ConstantPoolSDNode>(N)->get();
594 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
595 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
596 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
599 case ISD::GlobalAddress: {
600 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
601 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
602 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
603 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
604 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
609 case ISD::ZEXTLOAD: {
610 SDOperand Chain = Select(N->getOperand(0));
611 SDOperand Address = Select(N->getOperand(1));
613 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
614 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
616 switch (TypeBeingLoaded) {
617 default: N->dump(); assert(0 && "Cannot load this type!");
618 case MVT::i1: { // this is a bool
619 Opc = IA64::LD1; // first we load a byte, then compare for != 0
620 CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
621 CurDAG->getTargetNode(Opc, MVT::i64, Address),
622 CurDAG->getRegister(IA64::r0, MVT::i64), Chain);
623 return SDOperand(N, Op.ResNo); // XXX: early exit
625 case MVT::i8: Opc = IA64::LD1; break;
626 case MVT::i16: Opc = IA64::LD2; break;
627 case MVT::i32: Opc = IA64::LD4; break;
628 case MVT::i64: Opc = IA64::LD8; break;
630 case MVT::f32: Opc = IA64::LDF4; break;
631 case MVT::f64: Opc = IA64::LDF8; break;
634 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
635 Address, Chain); // TODO: comment this
637 return SDOperand(N, Op.ResNo);
640 case ISD::TRUNCSTORE:
642 SDOperand Address = Select(N->getOperand(2));
643 SDOperand Chain = Select(N->getOperand(0));
646 if (N->getOpcode() == ISD::STORE) {
647 switch (N->getOperand(1).getValueType()) {
648 default: assert(0 && "unknown type in store");
649 case MVT::i1: { // this is a bool
650 Opc = IA64::ST1; // we store either 0 or 1 as a byte
651 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address,
652 CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
653 CurDAG->getRegister(IA64::r0, MVT::i64),
654 CurDAG->getConstant(1, MVT::i64),
655 Select(N->getOperand(1))),
657 return SDOperand(N, 0); // XXX: early exit
659 case MVT::i64: Opc = IA64::ST8; break;
660 case MVT::f64: Opc = IA64::STF8; break;
662 } else { //ISD::TRUNCSTORE
663 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
664 default: assert(0 && "unknown type in truncstore");
665 case MVT::i8: Opc = IA64::ST1; break;
666 case MVT::i16: Opc = IA64::ST2; break;
667 case MVT::i32: Opc = IA64::ST4; break;
668 case MVT::f32: Opc = IA64::STF4; break;
672 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
673 Select(N->getOperand(1)), Chain);
674 return SDOperand(N, 0);
678 SDOperand Chain = Select(N->getOperand(0));
679 SDOperand CC = Select(N->getOperand(1));
680 MachineBasicBlock *Dest =
681 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
682 //FIXME - we do NOT need long branches all the time
683 CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC, CurDAG->getBasicBlock(Dest), Chain);
684 return SDOperand(N, 0);
687 case ISD::CALLSEQ_START:
688 case ISD::CALLSEQ_END: {
689 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
690 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
691 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
692 CurDAG->SelectNodeTo(N, Opc, MVT::Other,
693 getI64Imm(Amt), Select(N->getOperand(0)));
694 return SDOperand(N, 0);
698 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
700 switch (N->getNumOperands()) {
702 assert(0 && "Unknown return instruction!");
704 SDOperand RetVal = Select(N->getOperand(1));
705 switch (RetVal.getValueType()) {
706 default: assert(0 && "I don't know how to return this type! (promote?)");
707 // FIXME: do I need to add support for bools here?
708 // (return '0' or '1' in r8, basically...)
710 // FIXME: need to round floats - 80 bits is bad, the tester
713 // we mark r8 as live on exit up above in LowerArguments()
714 // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
715 Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
718 // we mark F8 as live on exit up above in LowerArguments()
719 // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
720 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
729 // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
730 // the output of this function's alloc instruction back into ar.pfs
731 // before we return. this copy must not float up above the last
732 // outgoing call in this function!!!
733 SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
735 Chain = AR_PFSVal.getValue(1);
736 Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
738 CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain); // and then just emit a 'ret' instruction
740 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
741 // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
743 return SDOperand(N, 0);
747 // FIXME: we don't need long branches all the time!
748 CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1),
749 Select(N->getOperand(0)));
750 return SDOperand(N, 0);
754 return SelectCode(Op);
758 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
759 /// into an IA64-specific DAG, ready for instruction scheduling.
761 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
762 return new IA64DAGToDAGISel(TM);