1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
36 //===--------------------------------------------------------------------===//
37 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
38 /// instructions for SelectionDAG operations.
40 class IA64DAGToDAGISel : public SelectionDAGISel {
41 IA64TargetLowering IA64Lowering;
42 unsigned GlobalBaseReg;
44 IA64DAGToDAGISel(IA64TargetMachine &TM)
45 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
47 virtual bool runOnFunction(Function &Fn) {
48 // Make sure we re-emit a set of the global base reg if necessary
50 return SelectionDAGISel::runOnFunction(Fn);
53 /// getI64Imm - Return a target constant with the specified value, of type
55 inline SDOperand getI64Imm(uint64_t Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i64);
59 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
60 /// base register. Return the virtual register that holds this value.
61 // SDOperand getGlobalBaseReg(); TODO: hmm
63 // Select - Convert the specified operand from a target-independent to a
64 // target-specific node if it hasn't already been changed.
65 SDNode *Select(SDOperand N);
67 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
68 unsigned OCHi, unsigned OCLo,
69 bool IsArithmetic = false,
71 SDNode *SelectBitfieldInsert(SDNode *N);
73 /// SelectCC - Select a comparison of the specified values with the
74 /// specified condition code, returning the CR# of the expression.
75 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
77 /// SelectAddr - Given the specified address, return the two operands for a
78 /// load/store instruction, and return true if it should be an indexed [r+r]
80 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
82 /// InstructionSelectBasicBlock - This callback is invoked by
83 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
84 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
86 virtual const char *getPassName() const {
87 return "IA64 (Itanium) DAG->DAG Instruction Selector";
90 // Include the pieces autogenerated from the target description.
91 #include "IA64GenDAGISel.inc"
94 SDNode *SelectDIV(SDOperand Op);
98 /// InstructionSelectBasicBlock - This callback is invoked by
99 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
100 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
103 // Select target instructions for the DAG.
104 DAG.setRoot(SelectRoot(DAG.getRoot()));
105 DAG.RemoveDeadNodes();
107 // Emit machine code to BB.
108 ScheduleAndEmitDAG(DAG);
111 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
113 SDOperand Chain = N->getOperand(0);
114 SDOperand Tmp1 = N->getOperand(0);
115 SDOperand Tmp2 = N->getOperand(1);
116 AddToISelQueue(Chain);
118 AddToISelQueue(Tmp1);
119 AddToISelQueue(Tmp2);
123 if(MVT::isFloatingPoint(Tmp1.getValueType()))
126 bool isModulus=false; // is it a division or a modulus?
129 switch(N->getOpcode()) {
131 case ISD::SDIV: isModulus=false; isSigned=true; break;
132 case ISD::UDIV: isModulus=false; isSigned=false; break;
134 case ISD::SREM: isModulus=true; isSigned=true; break;
135 case ISD::UREM: isModulus=true; isSigned=false; break;
138 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
140 SDOperand TmpPR, TmpPR2;
141 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
142 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
145 // we'll need copies of F0 and F1
146 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
147 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
149 // OK, emit some code:
152 // first, load the inputs into FP regs.
154 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
155 Chain = TmpF1.getValue(1);
157 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
158 Chain = TmpF2.getValue(1);
160 // next, convert the inputs to FP
163 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
164 Chain = TmpF3.getValue(1);
166 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
167 Chain = TmpF4.getValue(1);
168 } else { // is unsigned
170 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
171 Chain = TmpF3.getValue(1);
173 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
174 Chain = TmpF4.getValue(1);
177 } else { // this is an FP divide/remainder, so we 'leak' some temp
178 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
183 // we start by computing an approximate reciprocal (good to 9 bits?)
184 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
186 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
189 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
192 TmpPR = TmpF5.getValue(1);
193 Chain = TmpF5.getValue(2);
196 if(isModulus) { // for remainders, it'll be handy to have
197 // copies of -input_b
198 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
199 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
200 Chain = minusB.getValue(1);
203 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
205 SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
206 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
208 Chain = TmpE0.getValue(1);
209 SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
210 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
212 Chain = TmpY1.getValue(1);
213 SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
214 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
216 Chain = TmpE1.getValue(1);
217 SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
218 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
220 Chain = TmpY2.getValue(1);
222 if(isFP) { // if this is an FP divide, we finish up here and exit early
224 assert(0 && "Sorry, try another FORTRAN compiler.");
226 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
228 SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
229 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
231 Chain = TmpE2.getValue(1);
232 SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
233 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
235 Chain = TmpY3.getValue(1);
236 SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
238 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
240 Chain = TmpQ0.getValue(1);
241 SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
243 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
245 Chain = TmpR0.getValue(1);
247 // we want Result to have the same target register as the frcpa, so
248 // we two-address hack it. See the comment "for this to work..." on
249 // page 48 of Intel application note #245415
250 SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
251 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
253 Chain = SDOperand(Result, 1);
254 return Result; // XXX: early exit!
255 } else { // this is *not* an FP divide, so there's a bit left to do:
257 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
259 SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
260 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
262 Chain = TmpQ2.getValue(1);
263 SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
264 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
266 Chain = TmpR2.getValue(1);
268 // we want TmpQ3 to have the same target register as the frcpa? maybe we
269 // should two-address hack it. See the comment "for this to work..." on page
270 // 48 of Intel application note #245415
271 SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
272 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
274 Chain = TmpQ3.getValue(1);
276 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
277 // the FPSWA won't be able to help out in the case of large/tiny
278 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
281 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
282 MVT::f64, TmpQ3), 0);
284 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
285 MVT::f64, TmpQ3), 0);
287 Chain = TmpQ.getValue(1);
291 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
292 Chain = FPminusB.getValue(1);
293 SDOperand Remainder =
294 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
295 TmpQ, FPminusB, TmpF1), 0);
296 Chain = Remainder.getValue(1);
297 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
298 Chain = SDOperand(Result, 1);
299 } else { // just an integer divide
300 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
301 Chain = SDOperand(Result, 1);
305 } // wasn't an FP divide
308 // Select - Convert the specified operand from a target-independent to a
309 // target-specific node if it hasn't already been changed.
310 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
312 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
313 N->getOpcode() < IA64ISD::FIRST_NUMBER)
314 return NULL; // Already selected.
316 switch (N->getOpcode()) {
319 case IA64ISD::BRCALL: { // XXX: this is also a hack!
320 SDOperand Chain = N->getOperand(0);
321 SDOperand InFlag; // Null incoming flag value.
323 AddToISelQueue(Chain);
324 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
325 InFlag = N->getOperand(2);
326 AddToISelQueue(InFlag);
330 SDOperand CallOperand;
332 // if we can call directly, do so
333 if (GlobalAddressSDNode *GASD =
334 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
335 CallOpcode = IA64::BRCALL_IPREL_GA;
336 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
337 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
338 // FIXME: we currently NEED this case for correctness, to avoid
339 // "non-pic code with imm reloc.n against dynamic symbol" errors
340 CallOpcode = IA64::BRCALL_IPREL_ES;
341 CallOperand = N->getOperand(1);
343 // otherwise we need to load the function descriptor,
344 // load the branch target (function)'s entry point and GP,
345 // branch (call) then restore the GP
346 SDOperand FnDescriptor = N->getOperand(1);
347 AddToISelQueue(FnDescriptor);
349 // load the branch target's entry point [mem] and
351 SDOperand targetEntryPoint=
352 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
353 Chain = targetEntryPoint.getValue(1);
354 SDOperand targetGPAddr=
355 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
357 CurDAG->getConstant(8, MVT::i64)), 0);
358 Chain = targetGPAddr.getValue(1);
360 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
361 Chain = targetGP.getValue(1);
363 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
364 InFlag = Chain.getValue(1);
365 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
366 InFlag = Chain.getValue(1);
368 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
369 CallOpcode = IA64::BRCALL_INDIRECT;
372 // Finally, once everything is setup, emit the call itself
374 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
375 CallOperand, InFlag), 0);
376 else // there might be no arguments
377 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
378 CallOperand, Chain), 0);
379 InFlag = Chain.getValue(1);
381 std::vector<SDOperand> CallResults;
383 CallResults.push_back(Chain);
384 CallResults.push_back(InFlag);
386 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
387 ReplaceUses(Op.getValue(i), CallResults[i]);
391 case IA64ISD::GETFD: {
392 SDOperand Input = N->getOperand(0);
393 AddToISelQueue(Input);
394 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
402 return SelectDIV(Op);
404 case ISD::TargetConstantFP: {
405 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
408 ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
409 if (N2->getValueAPF().isPosZero()) {
410 V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
411 } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
412 APFloat(+1.0f) : APFloat(+1.0))) {
413 V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
415 assert(0 && "Unexpected FP constant!");
417 ReplaceUses(SDOperand(N, 0), V);
421 case ISD::FrameIndex: { // TODO: reduce creepyness
422 int FI = cast<FrameIndexSDNode>(N)->getIndex();
424 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
425 CurDAG->getTargetFrameIndex(FI, MVT::i64));
427 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
428 CurDAG->getTargetFrameIndex(FI, MVT::i64));
431 case ISD::ConstantPool: { // TODO: nuke the constant pool
432 // (ia64 doesn't need one)
433 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
434 Constant *C = CP->getConstVal();
435 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
437 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
438 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
441 case ISD::GlobalAddress: {
442 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
443 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
445 SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
446 CurDAG->getRegister(IA64::r1,
448 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
452 case ISD::ExternalSymbol: {
453 SDOperand EA = CurDAG->getTargetExternalSymbol(
454 cast<ExternalSymbolSDNode>(N)->getSymbol(),
456 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
457 CurDAG->getRegister(IA64::r1,
460 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
464 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
465 LoadSDNode *LD = cast<LoadSDNode>(N);
466 SDOperand Chain = LD->getChain();
467 SDOperand Address = LD->getBasePtr();
468 AddToISelQueue(Chain);
469 AddToISelQueue(Address);
471 MVT::ValueType TypeBeingLoaded = LD->getMemoryVT();
473 switch (TypeBeingLoaded) {
478 assert(0 && "Cannot load this type!");
479 case MVT::i1: { // this is a bool
480 Opc = IA64::LD1; // first we load a byte, then compare for != 0
481 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
482 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
483 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
484 CurDAG->getRegister(IA64::r0, MVT::i64),
487 /* otherwise, we want to load a bool into something bigger: LD1
488 will do that for us, so we just fall through */
490 case MVT::i8: Opc = IA64::LD1; break;
491 case MVT::i16: Opc = IA64::LD2; break;
492 case MVT::i32: Opc = IA64::LD4; break;
493 case MVT::i64: Opc = IA64::LD8; break;
495 case MVT::f32: Opc = IA64::LDF4; break;
496 case MVT::f64: Opc = IA64::LDF8; break;
499 // TODO: comment this
500 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
505 StoreSDNode *ST = cast<StoreSDNode>(N);
506 SDOperand Address = ST->getBasePtr();
507 SDOperand Chain = ST->getChain();
508 AddToISelQueue(Address);
509 AddToISelQueue(Chain);
512 if (ISD::isNON_TRUNCStore(N)) {
513 switch (N->getOperand(1).getValueType()) {
514 default: assert(0 && "unknown type in store");
515 case MVT::i1: { // this is a bool
516 Opc = IA64::ST1; // we store either 0 or 1 as a byte
518 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
519 Chain = Initial.getValue(1);
520 // then load 1 into the same reg iff the predicate to store is 1
521 SDOperand Tmp = ST->getValue();
524 SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
525 CurDAG->getTargetConstant(1, MVT::i64),
527 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
529 case MVT::i64: Opc = IA64::ST8; break;
530 case MVT::f64: Opc = IA64::STF8; break;
532 } else { // Truncating store
533 switch(ST->getMemoryVT()) {
534 default: assert(0 && "unknown type in truncstore");
535 case MVT::i8: Opc = IA64::ST1; break;
536 case MVT::i16: Opc = IA64::ST2; break;
537 case MVT::i32: Opc = IA64::ST4; break;
538 case MVT::f32: Opc = IA64::STF4; break;
542 SDOperand N1 = N->getOperand(1);
543 SDOperand N2 = N->getOperand(2);
546 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
550 SDOperand Chain = N->getOperand(0);
551 SDOperand CC = N->getOperand(1);
552 AddToISelQueue(Chain);
554 MachineBasicBlock *Dest =
555 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
556 //FIXME - we do NOT need long branches all the time
557 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
558 CurDAG->getBasicBlock(Dest), Chain);
561 case ISD::CALLSEQ_START:
562 case ISD::CALLSEQ_END: {
563 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
564 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
565 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
566 SDOperand N0 = N->getOperand(0);
568 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
572 // FIXME: we don't need long branches all the time!
573 SDOperand N0 = N->getOperand(0);
575 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
576 N->getOperand(1), N0);
579 return SelectCode(Op);
583 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
584 /// into an IA64-specific DAG, ready for instruction scheduling.
587 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
588 return new IA64DAGToDAGISel(TM);