1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
33 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
34 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
36 //===--------------------------------------------------------------------===//
37 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
38 /// instructions for SelectionDAG operations.
40 class IA64DAGToDAGISel : public SelectionDAGISel {
41 IA64TargetLowering IA64Lowering;
42 unsigned GlobalBaseReg;
44 IA64DAGToDAGISel(TargetMachine &TM)
45 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
47 virtual bool runOnFunction(Function &Fn) {
48 // Make sure we re-emit a set of the global base reg if necessary
50 return SelectionDAGISel::runOnFunction(Fn);
53 /// getI64Imm - Return a target constant with the specified value, of type
55 inline SDOperand getI64Imm(uint64_t Imm) {
56 return CurDAG->getTargetConstant(Imm, MVT::i64);
59 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
60 /// base register. Return the virtual register that holds this value.
61 // SDOperand getGlobalBaseReg(); TODO: hmm
63 // Select - Convert the specified operand from a target-independent to a
64 // target-specific node if it hasn't already been changed.
65 SDOperand Select(SDOperand Op);
67 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
68 unsigned OCHi, unsigned OCLo,
69 bool IsArithmetic = false,
71 SDNode *SelectBitfieldInsert(SDNode *N);
73 /// SelectCC - Select a comparison of the specified values with the
74 /// specified condition code, returning the CR# of the expression.
75 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
77 /// SelectAddr - Given the specified address, return the two operands for a
78 /// load/store instruction, and return true if it should be an indexed [r+r]
80 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
82 SDOperand BuildSDIVSequence(SDNode *N);
83 SDOperand BuildUDIVSequence(SDNode *N);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
89 virtual const char *getPassName() const {
90 return "IA64 (Itanium) DAG->DAG Instruction Selector";
93 // Include the pieces autogenerated from the target description.
94 #include "IA64GenDAGISel.inc"
97 SDOperand SelectDIV(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
106 // The selection process is inherently a bottom-up recursive process (users
107 // select their uses before themselves). Given infinite stack space, we
108 // could just start selecting on the root and traverse the whole graph. In
109 // practice however, this causes us to run out of stack space on large basic
110 // blocks. To avoid this problem, select the entry node, then all its uses,
111 // iteratively instead of recursively.
112 std::vector<SDOperand> Worklist;
113 Worklist.push_back(DAG.getEntryNode());
115 // Note that we can do this in the IA64 target (scanning forward across token
116 // chain edges) because no nodes ever get folded across these edges. On a
117 // target like X86 which supports load/modify/store operations, this would
118 // have to be more careful.
119 while (!Worklist.empty()) {
120 SDOperand Node = Worklist.back();
123 // Chose from the least deep of the top two nodes.
124 if (!Worklist.empty() &&
125 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
126 std::swap(Worklist.back(), Node);
128 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
129 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
130 CodeGenMap.count(Node)) continue;
132 for (SDNode::use_iterator UI = Node.Val->use_begin(),
133 E = Node.Val->use_end(); UI != E; ++UI) {
134 // Scan the values. If this use has a value that is a token chain, add it
137 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
138 if (User->getValueType(i) == MVT::Other) {
139 Worklist.push_back(SDOperand(User, i));
144 // Finally, legalize this node.
148 // Select target instructions for the DAG.
149 DAG.setRoot(Select(DAG.getRoot()));
151 DAG.RemoveDeadNodes();
153 // Emit machine code to BB.
154 ScheduleAndEmitDAG(DAG);
157 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
159 SDOperand Chain = Select(N->getOperand(0));
161 SDOperand Tmp1 = Select(N->getOperand(0));
162 SDOperand Tmp2 = Select(N->getOperand(1));
166 if(MVT::isFloatingPoint(Tmp1.getValueType()))
169 bool isModulus=false; // is it a division or a modulus?
172 switch(N->getOpcode()) {
174 case ISD::SDIV: isModulus=false; isSigned=true; break;
175 case ISD::UDIV: isModulus=false; isSigned=false; break;
177 case ISD::SREM: isModulus=true; isSigned=true; break;
178 case ISD::UREM: isModulus=true; isSigned=false; break;
181 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
183 SDOperand TmpPR, TmpPR2;
184 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
185 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
188 // we'll need copies of F0 and F1
189 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
190 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
192 // OK, emit some code:
195 // first, load the inputs into FP regs.
196 TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
197 Chain = TmpF1.getValue(1);
198 TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
199 Chain = TmpF2.getValue(1);
201 // next, convert the inputs to FP
203 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
204 Chain = TmpF3.getValue(1);
205 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
206 Chain = TmpF4.getValue(1);
207 } else { // is unsigned
208 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
209 Chain = TmpF3.getValue(1);
210 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
211 Chain = TmpF4.getValue(1);
214 } else { // this is an FP divide/remainder, so we 'leak' some temp
215 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
220 // we start by computing an approximate reciprocal (good to 9 bits?)
221 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
223 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
226 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
229 TmpPR = TmpF5.getValue(1);
230 Chain = TmpF5.getValue(2);
233 if(isModulus) { // for remainders, it'll be handy to have
234 // copies of -input_b
235 minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
236 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
237 Chain = minusB.getValue(1);
240 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
242 TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
243 TmpF4, TmpF5, F1, TmpPR);
244 Chain = TmpE0.getValue(1);
245 TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
246 TmpF5, TmpE0, TmpF5, TmpPR);
247 Chain = TmpY1.getValue(1);
248 TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
249 TmpE0, TmpE0, F0, TmpPR);
250 Chain = TmpE1.getValue(1);
251 TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
252 TmpY1, TmpE1, TmpY1, TmpPR);
253 Chain = TmpY2.getValue(1);
255 if(isFP) { // if this is an FP divide, we finish up here and exit early
257 assert(0 && "Sorry, try another FORTRAN compiler.");
259 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
261 TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
262 TmpE1, TmpE1, F0, TmpPR);
263 Chain = TmpE2.getValue(1);
264 TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
265 TmpY2, TmpE2, TmpY2, TmpPR);
266 Chain = TmpY3.getValue(1);
267 TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
268 Tmp1, TmpY3, F0, TmpPR);
269 Chain = TmpQ0.getValue(1);
270 TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
271 Tmp2, TmpQ0, Tmp1, TmpPR);
272 Chain = TmpR0.getValue(1);
274 // we want Result to have the same target register as the frcpa, so
275 // we two-address hack it. See the comment "for this to work..." on
276 // page 48 of Intel application note #245415
277 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
278 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
279 Chain = Result.getValue(1);
280 return Result; // XXX: early exit!
281 } else { // this is *not* an FP divide, so there's a bit left to do:
283 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
285 TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
286 TmpF3, TmpY2, F0, TmpPR);
287 Chain = TmpQ2.getValue(1);
288 TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
289 TmpF4, TmpQ2, TmpF3, TmpPR);
290 Chain = TmpR2.getValue(1);
292 // we want TmpQ3 to have the same target register as the frcpa? maybe we
293 // should two-address hack it. See the comment "for this to work..." on page
294 // 48 of Intel application note #245415
295 TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
296 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
297 Chain = TmpQ3.getValue(1);
299 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
300 // the FPSWA won't be able to help out in the case of large/tiny
301 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
304 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
306 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3);
308 Chain = TmpQ.getValue(1);
311 SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64,
313 Chain = FPminusB.getValue(1);
314 SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
315 TmpQ, FPminusB, TmpF1);
316 Chain = Remainder.getValue(1);
317 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
318 Chain = Result.getValue(1);
319 } else { // just an integer divide
320 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
321 Chain = Result.getValue(1);
325 } // wasn't an FP divide
328 // Select - Convert the specified operand from a target-independent to a
329 // target-specific node if it hasn't already been changed.
330 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
332 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
333 N->getOpcode() < IA64ISD::FIRST_NUMBER)
334 return Op; // Already selected.
336 // If this has already been converted, use it.
337 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
338 if (CGMI != CodeGenMap.end()) return CGMI->second;
340 switch (N->getOpcode()) {
343 case IA64ISD::BRCALL: { // XXX: this is also a hack!
344 SDOperand Chain = Select(N->getOperand(0));
345 SDOperand InFlag; // Null incoming flag value.
347 if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
348 InFlag = Select(N->getOperand(2));
351 SDOperand CallOperand;
353 // if we can call directly, do so
354 if (GlobalAddressSDNode *GASD =
355 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
356 CallOpcode = IA64::BRCALL_IPREL_GA;
357 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
358 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
359 // case for correctness, to avoid
360 // "non-pic code with imm reloc.n
361 // against dynamic symbol" errors
362 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
363 CallOpcode = IA64::BRCALL_IPREL_ES;
364 CallOperand = N->getOperand(1);
366 // otherwise we need to load the function descriptor,
367 // load the branch target (function)'s entry point and GP,
368 // branch (call) then restore the GP
369 SDOperand FnDescriptor = Select(N->getOperand(1));
371 // load the branch target's entry point [mem] and
373 SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
375 Chain = targetEntryPoint.getValue(1);
376 SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
377 FnDescriptor, CurDAG->getConstant(8, MVT::i64));
378 Chain = targetGPAddr.getValue(1);
379 SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
381 Chain = targetGP.getValue(1);
383 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
384 InFlag = Chain.getValue(1);
385 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
386 InFlag = Chain.getValue(1);
388 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
389 CallOpcode = IA64::BRCALL_INDIRECT;
392 // Finally, once everything is setup, emit the call itself
394 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag);
395 else // there might be no arguments
396 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain);
397 InFlag = Chain.getValue(1);
399 std::vector<SDOperand> CallResults;
401 CallResults.push_back(Chain);
402 CallResults.push_back(InFlag);
404 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
405 CodeGenMap[Op.getValue(i)] = CallResults[i];
406 return CallResults[Op.ResNo];
409 case IA64ISD::GETFD: {
410 SDOperand Input = Select(N->getOperand(0));
411 SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
412 CodeGenMap[Op] = Result;
420 case ISD::UREM: return SelectDIV(Op);
422 case ISD::ConstantFP: {
423 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
425 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
426 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
427 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
428 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
430 assert(0 && "Unexpected FP constant!");
433 case ISD::FrameIndex: { // TODO: reduce creepyness
434 int FI = cast<FrameIndexSDNode>(N)->getIndex();
436 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
437 CurDAG->getTargetFrameIndex(FI, MVT::i64));
439 return CodeGenMap[Op] = CurDAG->getTargetNode(IA64::MOV, MVT::i64,
440 CurDAG->getTargetFrameIndex(FI, MVT::i64));
443 case ISD::ConstantPool: { // TODO: nuke the constant pool
444 // (ia64 doesn't need one)
445 Constant *C = cast<ConstantPoolSDNode>(N)->get();
446 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
447 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
448 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
451 case ISD::GlobalAddress: {
452 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
453 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
454 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
455 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
456 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
459 /* XXX case ISD::ExternalSymbol: {
460 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
462 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
463 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
464 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
469 case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
470 case ISD::ZEXTLOAD: {
471 SDOperand Chain = Select(N->getOperand(0));
472 SDOperand Address = Select(N->getOperand(1));
474 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
475 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
477 switch (TypeBeingLoaded) {
478 default: N->dump(); assert(0 && "Cannot load this type!");
479 case MVT::i1: { // this is a bool
480 Opc = IA64::LD1; // first we load a byte, then compare for != 0
481 if(N->getValueType(0) == MVT::i1) // XXX: early exit!
482 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
483 CurDAG->getTargetNode(Opc, MVT::i64, Address),
484 CurDAG->getRegister(IA64::r0, MVT::i64),
485 Chain).getValue(Op.ResNo);
486 /* otherwise, we want to load a bool into something bigger: LD1
487 will do that for us, so we just fall through */
489 case MVT::i8: Opc = IA64::LD1; break;
490 case MVT::i16: Opc = IA64::LD2; break;
491 case MVT::i32: Opc = IA64::LD4; break;
492 case MVT::i64: Opc = IA64::LD8; break;
494 case MVT::f32: Opc = IA64::LDF4; break;
495 case MVT::f64: Opc = IA64::LDF8; break;
498 // TODO: comment this
499 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
500 Address, Chain).getValue(Op.ResNo);
503 case ISD::TRUNCSTORE:
505 SDOperand Address = Select(N->getOperand(2));
506 SDOperand Chain = Select(N->getOperand(0));
509 if (N->getOpcode() == ISD::STORE) {
510 switch (N->getOperand(1).getValueType()) {
511 default: assert(0 && "unknown type in store");
512 case MVT::i1: { // this is a bool
513 Opc = IA64::ST1; // we store either 0 or 1 as a byte
515 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
516 Chain = Initial.getValue(1);
517 // then load 1 into the same reg iff the predicate to store is 1
519 CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
520 CurDAG->getConstant(1, MVT::i64),
521 Select(N->getOperand(1)));
522 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
524 case MVT::i64: Opc = IA64::ST8; break;
525 case MVT::f64: Opc = IA64::STF8; break;
527 } else { //ISD::TRUNCSTORE
528 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
529 default: assert(0 && "unknown type in truncstore");
530 case MVT::i8: Opc = IA64::ST1; break;
531 case MVT::i16: Opc = IA64::ST2; break;
532 case MVT::i32: Opc = IA64::ST4; break;
533 case MVT::f32: Opc = IA64::STF4; break;
537 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
538 Select(N->getOperand(1)), Chain);
542 SDOperand Chain = Select(N->getOperand(0));
543 SDOperand CC = Select(N->getOperand(1));
544 MachineBasicBlock *Dest =
545 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
546 //FIXME - we do NOT need long branches all the time
547 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
548 CurDAG->getBasicBlock(Dest), Chain);
551 case ISD::CALLSEQ_START:
552 case ISD::CALLSEQ_END: {
553 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
554 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
555 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
556 return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
557 getI64Imm(Amt), Select(N->getOperand(0)));
561 // FIXME: we don't need long branches all the time!
562 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
563 N->getOperand(1), Select(N->getOperand(0)));
566 return SelectCode(Op);
570 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
571 /// into an IA64-specific DAG, ready for instruction scheduling.
573 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
574 return new IA64DAGToDAGISel(TM);