1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
36 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
37 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
39 //===--------------------------------------------------------------------===//
40 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
41 /// instructions for SelectionDAG operations.
43 class IA64DAGToDAGISel : public SelectionDAGISel {
44 IA64TargetLowering IA64Lowering;
45 unsigned GlobalBaseReg;
47 IA64DAGToDAGISel(IA64TargetMachine &TM)
48 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
50 virtual bool runOnFunction(Function &Fn) {
51 // Make sure we re-emit a set of the global base reg if necessary
53 return SelectionDAGISel::runOnFunction(Fn);
56 /// getI64Imm - Return a target constant with the specified value, of type
58 inline SDOperand getI64Imm(uint64_t Imm) {
59 return CurDAG->getTargetConstant(Imm, MVT::i64);
62 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
63 /// base register. Return the virtual register that holds this value.
64 // SDOperand getGlobalBaseReg(); TODO: hmm
66 // Select - Convert the specified operand from a target-independent to a
67 // target-specific node if it hasn't already been changed.
68 void Select(SDOperand &Result, SDOperand N);
70 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
71 unsigned OCHi, unsigned OCLo,
72 bool IsArithmetic = false,
74 SDNode *SelectBitfieldInsert(SDNode *N);
76 /// SelectCC - Select a comparison of the specified values with the
77 /// specified condition code, returning the CR# of the expression.
78 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
80 /// SelectAddr - Given the specified address, return the two operands for a
81 /// load/store instruction, and return true if it should be an indexed [r+r]
83 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
89 virtual const char *getPassName() const {
90 return "IA64 (Itanium) DAG->DAG Instruction Selector";
93 // Include the pieces autogenerated from the target description.
94 #include "IA64GenDAGISel.inc"
97 SDOperand SelectDIV(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
106 // Select target instructions for the DAG.
107 DAG.setRoot(SelectRoot(DAG.getRoot()));
108 DAG.RemoveDeadNodes();
110 // Emit machine code to BB.
111 ScheduleAndEmitDAG(DAG);
114 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
116 SDOperand Chain, Tmp1, Tmp2;
117 AddToQueue(Chain, N->getOperand(0));
119 AddToQueue(Tmp1, N->getOperand(0));
120 AddToQueue(Tmp2, N->getOperand(1));
124 if(MVT::isFloatingPoint(Tmp1.getValueType()))
127 bool isModulus=false; // is it a division or a modulus?
130 switch(N->getOpcode()) {
132 case ISD::SDIV: isModulus=false; isSigned=true; break;
133 case ISD::UDIV: isModulus=false; isSigned=false; break;
135 case ISD::SREM: isModulus=true; isSigned=true; break;
136 case ISD::UREM: isModulus=true; isSigned=false; break;
139 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
141 SDOperand TmpPR, TmpPR2;
142 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
143 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
146 // we'll need copies of F0 and F1
147 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
148 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
150 // OK, emit some code:
153 // first, load the inputs into FP regs.
155 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
156 Chain = TmpF1.getValue(1);
158 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
159 Chain = TmpF2.getValue(1);
161 // next, convert the inputs to FP
164 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
165 Chain = TmpF3.getValue(1);
167 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
168 Chain = TmpF4.getValue(1);
169 } else { // is unsigned
171 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
172 Chain = TmpF3.getValue(1);
174 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
175 Chain = TmpF4.getValue(1);
178 } else { // this is an FP divide/remainder, so we 'leak' some temp
179 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
184 // we start by computing an approximate reciprocal (good to 9 bits?)
185 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
187 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
190 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
193 TmpPR = TmpF5.getValue(1);
194 Chain = TmpF5.getValue(2);
197 if(isModulus) { // for remainders, it'll be handy to have
198 // copies of -input_b
199 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
200 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
201 Chain = minusB.getValue(1);
204 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
206 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
207 TmpF4, TmpF5, F1, TmpPR), 0);
208 Chain = TmpE0.getValue(1);
209 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
210 TmpF5, TmpE0, TmpF5, TmpPR), 0);
211 Chain = TmpY1.getValue(1);
212 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
213 TmpE0, TmpE0, F0, TmpPR), 0);
214 Chain = TmpE1.getValue(1);
215 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
216 TmpY1, TmpE1, TmpY1, TmpPR), 0);
217 Chain = TmpY2.getValue(1);
219 if(isFP) { // if this is an FP divide, we finish up here and exit early
221 assert(0 && "Sorry, try another FORTRAN compiler.");
223 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
225 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
226 TmpE1, TmpE1, F0, TmpPR), 0);
227 Chain = TmpE2.getValue(1);
228 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
229 TmpY2, TmpE2, TmpY2, TmpPR), 0);
230 Chain = TmpY3.getValue(1);
232 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
233 Tmp1, TmpY3, F0, TmpPR), 0);
234 Chain = TmpQ0.getValue(1);
236 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
237 Tmp2, TmpQ0, Tmp1, TmpPR), 0);
238 Chain = TmpR0.getValue(1);
240 // we want Result to have the same target register as the frcpa, so
241 // we two-address hack it. See the comment "for this to work..." on
242 // page 48 of Intel application note #245415
243 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
244 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
245 Chain = SDOperand(Result, 1);
246 return SDOperand(Result, 0); // XXX: early exit!
247 } else { // this is *not* an FP divide, so there's a bit left to do:
249 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
251 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
252 TmpF3, TmpY2, F0, TmpPR), 0);
253 Chain = TmpQ2.getValue(1);
254 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
255 TmpF4, TmpQ2, TmpF3, TmpPR), 0);
256 Chain = TmpR2.getValue(1);
258 // we want TmpQ3 to have the same target register as the frcpa? maybe we
259 // should two-address hack it. See the comment "for this to work..." on page
260 // 48 of Intel application note #245415
261 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
262 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
263 Chain = TmpQ3.getValue(1);
265 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
266 // the FPSWA won't be able to help out in the case of large/tiny
267 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
270 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
271 MVT::f64, TmpQ3), 0);
273 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
274 MVT::f64, TmpQ3), 0);
276 Chain = TmpQ.getValue(1);
280 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
281 Chain = FPminusB.getValue(1);
282 SDOperand Remainder =
283 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
284 TmpQ, FPminusB, TmpF1), 0);
285 Chain = Remainder.getValue(1);
286 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
287 Chain = SDOperand(Result, 1);
288 } else { // just an integer divide
289 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
290 Chain = SDOperand(Result, 1);
293 return SDOperand(Result, 0);
294 } // wasn't an FP divide
297 // Select - Convert the specified operand from a target-independent to a
298 // target-specific node if it hasn't already been changed.
299 void IA64DAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
301 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
302 N->getOpcode() < IA64ISD::FIRST_NUMBER) {
304 return; // Already selected.
307 switch (N->getOpcode()) {
310 case IA64ISD::BRCALL: { // XXX: this is also a hack!
312 SDOperand InFlag; // Null incoming flag value.
314 AddToQueue(Chain, N->getOperand(0));
315 if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
316 AddToQueue(InFlag, N->getOperand(2));
319 SDOperand CallOperand;
321 // if we can call directly, do so
322 if (GlobalAddressSDNode *GASD =
323 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
324 CallOpcode = IA64::BRCALL_IPREL_GA;
325 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
326 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
327 // case for correctness, to avoid
328 // "non-pic code with imm reloc.n
329 // against dynamic symbol" errors
330 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
331 CallOpcode = IA64::BRCALL_IPREL_ES;
332 CallOperand = N->getOperand(1);
334 // otherwise we need to load the function descriptor,
335 // load the branch target (function)'s entry point and GP,
336 // branch (call) then restore the GP
337 SDOperand FnDescriptor;
338 AddToQueue(FnDescriptor, N->getOperand(1));
340 // load the branch target's entry point [mem] and
342 SDOperand targetEntryPoint=
343 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
344 Chain = targetEntryPoint.getValue(1);
345 SDOperand targetGPAddr=
346 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
347 FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
348 Chain = targetGPAddr.getValue(1);
350 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
351 Chain = targetGP.getValue(1);
353 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
354 InFlag = Chain.getValue(1);
355 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
356 InFlag = Chain.getValue(1);
358 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
359 CallOpcode = IA64::BRCALL_INDIRECT;
362 // Finally, once everything is setup, emit the call itself
364 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
365 CallOperand, InFlag), 0);
366 else // there might be no arguments
367 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
368 CallOperand, Chain), 0);
369 InFlag = Chain.getValue(1);
371 std::vector<SDOperand> CallResults;
373 CallResults.push_back(Chain);
374 CallResults.push_back(InFlag);
376 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
377 ReplaceUses(Op.getValue(i), CallResults[i]);
378 Result = CallResults[Op.ResNo];
382 case IA64ISD::GETFD: {
384 AddToQueue(Input, N->getOperand(0));
385 Result = SDOperand(CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input), 0);
386 ReplaceUses(Op, Result);
395 Result = SelectDIV(Op);
396 ReplaceUses(Op, Result);
399 case ISD::TargetConstantFP: {
400 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
402 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
403 Result = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
404 } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
405 Result = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
407 assert(0 && "Unexpected FP constant!");
411 case ISD::FrameIndex: { // TODO: reduce creepyness
412 int FI = cast<FrameIndexSDNode>(N)->getIndex();
414 Result = CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
415 CurDAG->getTargetFrameIndex(FI, MVT::i64));
417 Result = SDOperand(CurDAG->getTargetNode(IA64::MOV, MVT::i64,
418 CurDAG->getTargetFrameIndex(FI, MVT::i64)), 0);
419 ReplaceUses(Op, Result);
424 case ISD::ConstantPool: { // TODO: nuke the constant pool
425 // (ia64 doesn't need one)
426 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
427 Constant *C = CP->get();
428 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
430 Result = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
431 CurDAG->getRegister(IA64::r1, MVT::i64), CPI), 0);
432 ReplaceUses(Op, Result);
436 case ISD::GlobalAddress: {
437 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
438 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
439 SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
440 CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
441 Result = SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp), 0);
442 ReplaceUses(Op, Result);
446 /* XXX case ISD::ExternalSymbol: {
447 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
449 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
450 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
451 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
456 case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
457 case ISD::ZEXTLOAD: {
458 SDOperand Chain, Address;
459 AddToQueue(Chain, N->getOperand(0));
460 AddToQueue(Address, N->getOperand(1));
462 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
463 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
465 switch (TypeBeingLoaded) {
470 assert(0 && "Cannot load this type!");
471 case MVT::i1: { // this is a bool
472 Opc = IA64::LD1; // first we load a byte, then compare for != 0
473 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
474 Result = CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
475 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
476 CurDAG->getRegister(IA64::r0, MVT::i64),
477 Chain).getValue(Op.ResNo);
480 /* otherwise, we want to load a bool into something bigger: LD1
481 will do that for us, so we just fall through */
483 case MVT::i8: Opc = IA64::LD1; break;
484 case MVT::i16: Opc = IA64::LD2; break;
485 case MVT::i32: Opc = IA64::LD4; break;
486 case MVT::i64: Opc = IA64::LD8; break;
488 case MVT::f32: Opc = IA64::LDF4; break;
489 case MVT::f64: Opc = IA64::LDF8; break;
492 // TODO: comment this
493 Result = CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
494 Address, Chain).getValue(Op.ResNo);
498 case ISD::TRUNCSTORE:
500 SDOperand Address, Chain;
501 AddToQueue(Address, N->getOperand(2));
502 AddToQueue(Chain, N->getOperand(0));
505 if (N->getOpcode() == ISD::STORE) {
506 switch (N->getOperand(1).getValueType()) {
507 default: assert(0 && "unknown type in store");
508 case MVT::i1: { // this is a bool
509 Opc = IA64::ST1; // we store either 0 or 1 as a byte
511 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
512 Chain = Initial.getValue(1);
513 // then load 1 into the same reg iff the predicate to store is 1
515 AddToQueue(Tmp, N->getOperand(1));
516 Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
517 CurDAG->getConstant(1, MVT::i64),
519 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
522 case MVT::i64: Opc = IA64::ST8; break;
523 case MVT::f64: Opc = IA64::STF8; break;
525 } else { //ISD::TRUNCSTORE
526 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
527 default: assert(0 && "unknown type in truncstore");
528 case MVT::i8: Opc = IA64::ST1; break;
529 case MVT::i16: Opc = IA64::ST2; break;
530 case MVT::i32: Opc = IA64::ST4; break;
531 case MVT::f32: Opc = IA64::STF4; break;
536 AddToQueue(N1, N->getOperand(1));
537 AddToQueue(N2, N->getOperand(2));
538 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
544 AddToQueue(Chain, N->getOperand(0));
545 AddToQueue(CC, N->getOperand(1));
546 MachineBasicBlock *Dest =
547 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
548 //FIXME - we do NOT need long branches all the time
549 Result = CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
550 CurDAG->getBasicBlock(Dest), Chain);
554 case ISD::CALLSEQ_START:
555 case ISD::CALLSEQ_END: {
556 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
557 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
558 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
560 AddToQueue(N0, N->getOperand(0));
561 Result = CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
566 // FIXME: we don't need long branches all the time!
568 AddToQueue(N0, N->getOperand(0));
569 Result = CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
570 N->getOperand(1), N0);
574 SelectCode(Result, Op);
578 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
579 /// into an IA64-specific DAG, ready for instruction scheduling.
582 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
583 return new IA64DAGToDAGISel(TM);