1 //===-- IA64Bundling.cpp - IA-64 instruction bundling pass. ------------ --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Add stops where required to prevent read-after-write and write-after-write
11 // dependencies, for both registers and memory addresses. There are exceptions:
13 // - Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
14 // WAW dependencies so long as they all target p0, or are of parallel
17 // FIXME: bundling, for now, is left to the assembler.
18 // FIXME: this might be an appropriate place to translate between different
19 // instructions that do the same thing, if this helps bundling.
21 //===----------------------------------------------------------------------===//
24 #include "IA64InstrInfo.h"
25 #include "IA64TargetMachine.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/ADT/SetOperations.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/Support/Debug.h"
35 Statistic StopBitsAdded("ia64-codegen", "Number of stop bits added");
37 struct IA64BundlingPass : public MachineFunctionPass {
38 /// Target machine description which we query for reg. names, data
41 IA64TargetMachine &TM;
43 IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }
45 virtual const char *getPassName() const {
46 return "IA64 (Itanium) Bundling Pass";
49 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
50 bool runOnMachineFunction(MachineFunction &F) {
52 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
54 Changed |= runOnMachineBasicBlock(*FI);
58 std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
59 // pending writes can cross basic blocks. Note that
60 // taken branches end instruction groups. So we
61 // only need to worry about 'fallthrough' code
63 } // end of anonymous namespace
65 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
66 /// and arranges the result into bundles.
68 FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
69 return new IA64BundlingPass(tm);
72 /// runOnMachineBasicBlock - add stops and bundle this MBB.
74 bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
77 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
78 MachineInstr *CurrentInsn = I++;
79 std::set<unsigned> CurrentReads, CurrentWrites, OrigWrites;
81 for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
82 MachineOperand &MO=CurrentInsn->getOperand(i);
84 if(MO.isUse()) { // TODO: exclude p0
85 CurrentReads.insert(MO.getReg());
87 if(MO.isDef()) { // TODO: exclude p0
88 CurrentWrites.insert(MO.getReg());
89 OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
90 // set_intersect instead?
95 // CurrentReads/CurrentWrites contain info for the current instruction.
96 // Does it read or write any registers that are pending a write?
97 // (i.e. not separated by a stop)
98 set_intersect(CurrentReads, PendingRegWrites);
99 set_intersect(CurrentWrites, PendingRegWrites);
101 if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
102 // there is a conflict, insert a stop and reset PendingRegWrites
103 CurrentInsn = BuildMI(MBB, CurrentInsn,
104 TM.getInstrInfo()->get(IA64::STOP), 0);
105 PendingRegWrites=OrigWrites; // carry over current writes to next insn
106 Changed=true; StopBitsAdded++; // update stats
107 } else { // otherwise, track additional pending writes
108 set_union(PendingRegWrites, OrigWrites);
110 } // onto the next insn in the MBB