1 //===-- HexagonMCTargetDesc.h - Hexagon Target Descriptions -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides Hexagon specific target descriptions.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H
19 #include "llvm/Support/CommandLine.h"
22 struct InstrItinerary;
30 class MCSubtargetInfo;
35 class raw_pwrite_stream;
37 extern Target TheHexagonTarget;
38 extern cl::opt<bool> HexagonDisableCompound;
39 extern cl::opt<bool> HexagonDisableDuplex;
40 extern const InstrStage HexagonStages[];
42 MCInstrInfo *createHexagonMCInstrInfo();
44 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
45 const MCRegisterInfo &MRI,
48 MCAsmBackend *createHexagonAsmBackend(const Target &T,
49 const MCRegisterInfo &MRI,
50 const Triple &TT, StringRef CPU);
52 MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
53 uint8_t OSABI, StringRef CPU);
55 namespace HEXAGON_MC {
56 StringRef selectHexagonCPU(const Triple &TT, StringRef CPU);
59 } // End llvm namespace
61 // Define symbolic names for Hexagon registers. This defines a mapping from
62 // register name to register number.
64 #define GET_REGINFO_ENUM
65 #include "HexagonGenRegisterInfo.inc"
67 // Defines symbolic names for the Hexagon instructions.
69 #define GET_INSTRINFO_ENUM
70 #include "HexagonGenInstrInfo.inc"
72 #define GET_SUBTARGETINFO_ENUM
73 #include "HexagonGenSubtargetInfo.inc"