lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

   1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Hexagon specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "HexagonMCTargetDesc.h"
  15 #include "Hexagon.h"
  16 #include "HexagonMCAsmInfo.h"
  17 #include "HexagonMCELFStreamer.h"
  18 #include "MCTargetDesc/HexagonInstPrinter.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCContext.h"
  21 #include "llvm/MC/MCELFStreamer.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCObjectStreamer.h"
  24 #include "llvm/MC/MCRegisterInfo.h"
  25 #include "llvm/MC/MCStreamer.h"
  26 #include "llvm/MC/MCSubtargetInfo.h"
  27 #include "llvm/MC/MachineLocation.h"
  28 #include "llvm/Support/ELF.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/TargetRegistry.h"
  31
  32 using namespace llvm;
  33
  34 #define GET_INSTRINFO_MC_DESC
  35 #include "HexagonGenInstrInfo.inc"
  36
  37 #define GET_SUBTARGETINFO_MC_DESC
  38 #include "HexagonGenSubtargetInfo.inc"
  39
  40 #define GET_REGINFO_MC_DESC
  41 #include "HexagonGenRegisterInfo.inc"
  42
  43 MCInstrInfo *llvm::createHexagonMCInstrInfo() {
  44   MCInstrInfo *X = new MCInstrInfo();
  45   InitHexagonMCInstrInfo(X);
  46   return X;
  47 }
  48
  49 static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) {
  50   MCRegisterInfo *X = new MCRegisterInfo();
  51   InitHexagonMCRegisterInfo(X, Hexagon::R0);
  52   return X;
  53 }
  54
  55 static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT,
  56                                                      StringRef CPU,
  57                                                      StringRef FS) {
  58   return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
  59 }
  60
  61 namespace {
  62 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
  63 public:
  64   HexagonTargetAsmStreamer(MCStreamer &S,
  65                            formatted_raw_ostream &, bool,
  66                            MCInstPrinter &)
  67       : HexagonTargetStreamer(S) {}
  68   void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
  69                       const MCInst &Inst, const MCSubtargetInfo &STI) override {
  70     assert(HexagonMCInstrInfo::isBundle(Inst));
  71     assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
  72     std::string Buffer;
  73     {
  74       raw_string_ostream TempStream(Buffer);
  75       InstPrinter.printInst(&Inst, TempStream, "", STI);
  76     }
  77     StringRef Contents(Buffer);
  78     auto PacketBundle = Contents.rsplit('\n');
  79     auto HeadTail = PacketBundle.first.split('\n');
  80     auto Preamble = "\t{\n\t\t";
  81     auto Separator = "";
  82     while(!HeadTail.first.empty()) {
  83       OS << Separator;
  84       StringRef Inst;
  85       auto Duplex = HeadTail.first.split('\v');
  86       if(!Duplex.second.empty()){
  87         OS << Duplex.first << "\n";
  88         Inst = Duplex.second;
  89       }
  90       else {
  91         if(!HeadTail.first.startswith("immext"))
  92           Inst = Duplex.first;
  93       }
  94       OS << Preamble;
  95       OS << Inst;
  96       HeadTail = HeadTail.second.split('\n');
  97       Preamble = "";
  98       Separator = "\n\t\t";
  99     }
 100     if(HexagonMCInstrInfo::bundleSize(Inst) != 0)
 101       OS << "\n\t}" << PacketBundle.second;
 102   }
 103 };
 104 }
 105
 106 namespace {
 107 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
 108 public:
 109   MCELFStreamer &getStreamer() {
 110     return static_cast<MCELFStreamer &>(Streamer);
 111   }
 112   HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
 113       : HexagonTargetStreamer(S) {
 114     auto Bits = STI.getFeatureBits();
 115     unsigned Flags;
 116     if (Bits.to_ullong() & llvm::Hexagon::ArchV5)
 117       Flags = ELF::EF_HEXAGON_MACH_V5;
 118     else
 119       Flags = ELF::EF_HEXAGON_MACH_V4;
 120     getStreamer().getAssembler().setELFHeaderEFlags(Flags);
 121   }
 122   void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 123                               unsigned ByteAlignment,
 124                               unsigned AccessSize) override {
 125     HexagonMCELFStreamer &HexagonELFStreamer =
 126         static_cast<HexagonMCELFStreamer &>(getStreamer());
 127     HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
 128                                                  AccessSize);
 129   }
 130   void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 131                                    unsigned ByteAlignment,
 132                                    unsigned AccessSize) override {
 133     HexagonMCELFStreamer &HexagonELFStreamer =
 134         static_cast<HexagonMCELFStreamer &>(getStreamer());
 135     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
 136         Symbol, Size, ByteAlignment, AccessSize);
 137   }
 138 };
 139 }
 140
 141 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
 142                                          const TargetTuple &TT) {
 143   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
 144
 145   // VirtualFP = (R30 + #0).
 146   MCCFIInstruction Inst =
 147       MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
 148   MAI->addInitialFrameState(Inst);
 149
 150   return MAI;
 151 }
 152
 153 static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT,
 154                                                  Reloc::Model RM,
 155                                                  CodeModel::Model CM,
 156                                                  CodeGenOpt::Level OL) {
 157   MCCodeGenInfo *X = new MCCodeGenInfo();
 158   // For the time being, use static relocations, since there's really no
 159   // support for PIC yet.
 160   X->initMCCodeGenInfo(Reloc::Static, CM, OL);
 161   return X;
 162 }
 163
 164 static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT,
 165                                                  unsigned SyntaxVariant,
 166                                                  const MCAsmInfo &MAI,
 167                                                  const MCInstrInfo &MII,
 168                                                  const MCRegisterInfo &MRI) {
 169   if (SyntaxVariant == 0)
 170     return (new HexagonInstPrinter(MAI, MII, MRI));
 171   else
 172     return nullptr;
 173 }
 174
 175 static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
 176                                                    formatted_raw_ostream &OS,
 177                                                    MCInstPrinter *InstPrint,
 178                                                    bool IsVerboseAsm) {
 179   return new HexagonTargetAsmStreamer(S,  OS, IsVerboseAsm, *InstPrint);
 180 }
 181
 182 static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context,
 183                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
 184                                     MCCodeEmitter *Emitter, bool RelaxAll) {
 185   return createHexagonELFStreamer(Context, MAB, OS, Emitter);
 186 }
 187
 188 static MCTargetStreamer *
 189 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
 190   return new HexagonTargetELFStreamer(S, STI);
 191 }
 192
 193 // Force static initialization.
 194 extern "C" void LLVMInitializeHexagonTargetMC() {
 195   // Register the MC asm info.
 196   RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
 197
 198   // Register the MC codegen info.
 199   TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
 200                                         createHexagonMCCodeGenInfo);
 201
 202   // Register the MC instruction info.
 203   TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
 204                                       createHexagonMCInstrInfo);
 205
 206   // Register the MC register info.
 207   TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
 208                                     createHexagonMCRegisterInfo);
 209
 210   // Register the MC subtarget info.
 211   TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
 212                                           createHexagonMCSubtargetInfo);
 213
 214   // Register the MC Code Emitter
 215   TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
 216                                         createHexagonMCCodeEmitter);
 217
 218   // Register the asm backend
 219   TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
 220                                        createHexagonAsmBackend);
 221
 222   // Register the obj streamer
 223   TargetRegistry::RegisterELFStreamer(TheHexagonTarget, createMCStreamer);
 224
 225   // Register the asm streamer
 226   TargetRegistry::RegisterAsmTargetStreamer(TheHexagonTarget,
 227                                             createMCAsmTargetStreamer);
 228
 229   // Register the MC Inst Printer
 230   TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
 231                                         createHexagonMCInstPrinter);
 232
 233   TargetRegistry::RegisterObjectTargetStreamer(
 234       TheHexagonTarget, createHexagonObjectTargetStreamer);
 235 }