lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp

   1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file provides Hexagon specific target descriptions.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "HexagonMCTargetDesc.h"
  15 #include "Hexagon.h"
  16 #include "HexagonMCAsmInfo.h"
  17 #include "HexagonMCELFStreamer.h"
  18 #include "MCTargetDesc/HexagonInstPrinter.h"
  19 #include "llvm/MC/MCCodeGenInfo.h"
  20 #include "llvm/MC/MCContext.h"
  21 #include "llvm/MC/MCELFStreamer.h"
  22 #include "llvm/MC/MCInstrInfo.h"
  23 #include "llvm/MC/MCObjectStreamer.h"
  24 #include "llvm/MC/MCRegisterInfo.h"
  25 #include "llvm/MC/MCStreamer.h"
  26 #include "llvm/MC/MCSubtargetInfo.h"
  27 #include "llvm/MC/MachineLocation.h"
  28 #include "llvm/Support/ELF.h"
  29 #include "llvm/Support/ErrorHandling.h"
  30 #include "llvm/Support/TargetRegistry.h"
  31
  32 using namespace llvm;
  33
  34 #define GET_INSTRINFO_MC_DESC
  35 #include "HexagonGenInstrInfo.inc"
  36
  37 #define GET_SUBTARGETINFO_MC_DESC
  38 #include "HexagonGenSubtargetInfo.inc"
  39
  40 #define GET_REGINFO_MC_DESC
  41 #include "HexagonGenRegisterInfo.inc"
  42
  43 MCInstrInfo *llvm::createHexagonMCInstrInfo() {
  44   MCInstrInfo *X = new MCInstrInfo();
  45   InitHexagonMCInstrInfo(X);
  46   return X;
  47 }
  48
  49 static MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT) {
  50   MCRegisterInfo *X = new MCRegisterInfo();
  51   InitHexagonMCRegisterInfo(X, Hexagon::R0);
  52   return X;
  53 }
  54
  55 static MCSubtargetInfo *
  56 createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
  57   MCSubtargetInfo *X = new MCSubtargetInfo();
  58   InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
  59   return X;
  60 }
  61
  62 namespace {
  63 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
  64 public:
  65   HexagonTargetAsmStreamer(MCStreamer &S,
  66                            formatted_raw_ostream &, bool,
  67                            MCInstPrinter &)
  68       : HexagonTargetStreamer(S) {}
  69   void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS,
  70                       const MCInst &Inst, const MCSubtargetInfo &STI) override {
  71     assert(HexagonMCInstrInfo::isBundle(Inst));
  72     assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
  73     std::string Buffer;
  74     {
  75       raw_string_ostream TempStream(Buffer);
  76       InstPrinter.printInst(&Inst, TempStream, "", STI);
  77     }
  78     StringRef Contents(Buffer);
  79     auto PacketBundle = Contents.rsplit('\n');
  80     auto HeadTail = PacketBundle.first.split('\n');
  81     auto Preamble = "\t{\n\t\t";
  82     auto Separator = "";
  83     while(!HeadTail.first.empty()) {
  84       OS << Separator;
  85       StringRef Inst;
  86       auto Duplex = HeadTail.first.split('\v');
  87       if(!Duplex.second.empty()){
  88         OS << Duplex.first << "\n";
  89         Inst = Duplex.second;
  90       }
  91       else {
  92         if(!HeadTail.first.startswith("immext"))
  93           Inst = Duplex.first;
  94       }
  95       OS << Preamble;
  96       OS << Inst;
  97       HeadTail = HeadTail.second.split('\n');
  98       Preamble = "";
  99       Separator = "\n\t\t";
 100     }
 101     if(HexagonMCInstrInfo::bundleSize(Inst) != 0)
 102       OS << "\n\t}" << PacketBundle.second;
 103   }
 104 };
 105 } // namespace
 106
 107 namespace {
 108 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
 109 public:
 110   MCELFStreamer &getStreamer() {
 111     return static_cast<MCELFStreamer &>(Streamer);
 112   }
 113   HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
 114       : HexagonTargetStreamer(S) {
 115     auto Bits = STI.getFeatureBits();
 116     unsigned Flags;
 117     if (Bits.to_ullong() & llvm::Hexagon::ArchV5)
 118       Flags = ELF::EF_HEXAGON_MACH_V5;
 119     else
 120       Flags = ELF::EF_HEXAGON_MACH_V4;
 121     getStreamer().getAssembler().setELFHeaderEFlags(Flags);
 122   }
 123   void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 124                               unsigned ByteAlignment,
 125                               unsigned AccessSize) override {
 126     HexagonMCELFStreamer &HexagonELFStreamer =
 127         static_cast<HexagonMCELFStreamer &>(getStreamer());
 128     HexagonELFStreamer.HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment,
 129                                                  AccessSize);
 130   }
 131   void EmitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
 132                                    unsigned ByteAlignment,
 133                                    unsigned AccessSize) override {
 134     HexagonMCELFStreamer &HexagonELFStreamer =
 135         static_cast<HexagonMCELFStreamer &>(getStreamer());
 136     HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
 137         Symbol, Size, ByteAlignment, AccessSize);
 138   }
 139 };
 140 } // namespace
 141
 142 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
 143                                          const Triple &TT) {
 144   MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
 145
 146   // VirtualFP = (R30 + #0).
 147   MCCFIInstruction Inst =
 148       MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0);
 149   MAI->addInitialFrameState(Inst);
 150
 151   return MAI;
 152 }
 153
 154 static MCCodeGenInfo *createHexagonMCCodeGenInfo(StringRef TT, Reloc::Model RM,
 155                                                  CodeModel::Model CM,
 156                                                  CodeGenOpt::Level OL) {
 157   MCCodeGenInfo *X = new MCCodeGenInfo();
 158   // For the time being, use static relocations, since there's really no
 159   // support for PIC yet.
 160   X->initMCCodeGenInfo(Reloc::Static, CM, OL);
 161   return X;
 162 }
 163
 164 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
 165                                                  unsigned SyntaxVariant,
 166                                                  const MCAsmInfo &MAI,
 167                                                  const MCInstrInfo &MII,
 168                                                  const MCRegisterInfo &MRI) {
 169   if (SyntaxVariant == 0)
 170     return (new HexagonInstPrinter(MAI, MII, MRI));
 171   else
 172     return nullptr;
 173 }
 174
 175 MCTargetStreamer *createMCAsmTargetStreamer(
 176       MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint,
 177       bool IsVerboseAsm) {
 178   return new HexagonTargetAsmStreamer(S,  OS, IsVerboseAsm, *InstPrint);
 179 }
 180
 181 static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
 182                                     MCAsmBackend &MAB, raw_pwrite_stream &OS,
 183                                     MCCodeEmitter *Emitter, bool RelaxAll) {
 184   return createHexagonELFStreamer(Context, MAB, OS, Emitter);
 185 }
 186
 187 static MCTargetStreamer *
 188 createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) {
 189   return new HexagonTargetELFStreamer(S, STI);
 190 }
 191
 192 // Force static initialization.
 193 extern "C" void LLVMInitializeHexagonTargetMC() {
 194   // Register the MC asm info.
 195   RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo);
 196
 197   // Register the MC codegen info.
 198   TargetRegistry::RegisterMCCodeGenInfo(TheHexagonTarget,
 199                                         createHexagonMCCodeGenInfo);
 200
 201   // Register the MC instruction info.
 202   TargetRegistry::RegisterMCInstrInfo(TheHexagonTarget,
 203                                       createHexagonMCInstrInfo);
 204
 205   // Register the MC register info.
 206   TargetRegistry::RegisterMCRegInfo(TheHexagonTarget,
 207                                     createHexagonMCRegisterInfo);
 208
 209   // Register the MC subtarget info.
 210   TargetRegistry::RegisterMCSubtargetInfo(TheHexagonTarget,
 211                                           createHexagonMCSubtargetInfo);
 212
 213   // Register the MC Code Emitter
 214   TargetRegistry::RegisterMCCodeEmitter(TheHexagonTarget,
 215                                         createHexagonMCCodeEmitter);
 216
 217   // Register the asm backend
 218   TargetRegistry::RegisterMCAsmBackend(TheHexagonTarget,
 219                                        createHexagonAsmBackend);
 220
 221   // Register the obj streamer
 222   TargetRegistry::RegisterELFStreamer(TheHexagonTarget, createMCStreamer);
 223
 224   // Register the asm streamer
 225   TargetRegistry::RegisterAsmTargetStreamer(TheHexagonTarget,
 226                                             createMCAsmTargetStreamer);
 227
 228   // Register the MC Inst Printer
 229   TargetRegistry::RegisterMCInstPrinter(TheHexagonTarget,
 230                                         createHexagonMCInstPrinter);
 231
 232   TargetRegistry::RegisterObjectTargetStreamer(
 233       TheHexagonTarget, createHexagonObjectTargetStreamer);
 234 }