1 //===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "MCTargetDesc/HexagonBaseInfo.h"
12 #include "MCTargetDesc/HexagonFixupKinds.h"
13 #include "MCTargetDesc/HexagonMCCodeEmitter.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "MCTargetDesc/HexagonMCTargetDesc.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/EndianStream.h"
26 #include "llvm/Support/raw_ostream.h"
28 #define DEBUG_TYPE "mccodeemitter"
31 using namespace Hexagon;
33 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
35 HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
38 Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
40 uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
42 MCInst const &MCI) const {
43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
44 if (Instruction == 0) {
45 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
47 assert(Instruction != Last);
48 return HexagonII::INST_PARSE_LOOP_END;
51 if (Instruction == 1) {
52 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
54 assert(Instruction != Last);
55 return HexagonII::INST_PARSE_LOOP_END;
59 assert(Instruction == Last);
60 return HexagonII::INST_PARSE_DUPLEX;
62 if(Instruction == Last)
63 return HexagonII::INST_PARSE_PACKET_END;
64 return HexagonII::INST_PARSE_NOT_END;
67 void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
68 SmallVectorImpl<MCFixup> &Fixups,
69 MCSubtargetInfo const &STI) const {
70 MCInst &HMB = const_cast<MCInst &>(MI);
72 assert(HexagonMCInstrInfo::isBundle(HMB));
73 DEBUG(dbgs() << "Encoding bundle\n";);
77 size_t Instruction = 0;
78 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
79 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
80 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
81 EncodeSingleInstruction(HMI, OS, Fixups, STI,
82 parseBits(Instruction, Last, HMB, HMI),
84 *Extended = HexagonMCInstrInfo::isImmext(HMI);
85 *Addend += HEXAGON_INSTR_SIZE;
91 /// EncodeSingleInstruction - Emit a single
92 void HexagonMCCodeEmitter::EncodeSingleInstruction(
93 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
94 const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
96 assert(!HexagonMCInstrInfo::isBundle(HMB));
99 // Compound instructions are limited to using registers 0-7 and 16-23
100 // and here we make a map 16-23 to 8-15 so they can be correctly encoded.
101 static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10,
102 Hexagon::R11, Hexagon::R12, Hexagon::R13,
103 Hexagon::R14, Hexagon::R15};
105 // Pseudo instructions don't get encoded and shouldn't be here
106 // in the first place!
107 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
108 "pseudo-instruction found");
109 DEBUG(dbgs() << "Encoding insn"
110 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
113 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
114 for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
115 if (HMB.getOperand(i).isReg()) {
117 MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg());
118 if ((Reg <= 23) && (Reg >= 16))
119 HMB.getOperand(i).setReg(RegMap[Reg - 16]);
123 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
124 // Calculate the new value distance to the associated producer
126 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
127 unsigned SOffset = 0;
128 unsigned Register = MCO.getReg();
130 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
131 auto i = Instructions.begin() + Index - 1;
133 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
134 MCInst const &Inst = *i->getInst();
135 if (HexagonMCInstrInfo::isImmext(Inst))
139 HexagonMCInstrInfo::hasNewValue(MCII, Inst)
140 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
141 : static_cast<unsigned>(Hexagon::NoRegister);
142 if (Register != Register1)
143 // This isn't the register we're looking for
145 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
146 // Producer is unpredicated
148 assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
149 "Unpredicated consumer depending on predicated producer");
150 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
151 HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
152 // Producer predicate sense matched ours
155 // Hexagon PRM 10.11 Construct Nt from distance
156 unsigned Offset = SOffset;
158 MCO.setReg(Offset + Hexagon::R0);
161 Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
162 // Check for unimplemented instructions. Immediate extenders
163 // are encoded as zero, so they need to be accounted for.
165 ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
166 (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
167 (HMB.getOpcode() != A4_ext_g))) {
168 // Use a A2_nop for unimplemented instructions.
169 DEBUG(dbgs() << "Unimplemented inst: "
170 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
172 llvm_unreachable("Unimplemented Instruction");
176 // if we need to emit a duplexed instruction
177 if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
178 HMB.getOpcode() <= Hexagon::DuplexIClassF) {
179 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
180 "Emitting duplex without duplex parse bits");
182 switch (HMB.getOpcode()) {
183 case Hexagon::DuplexIClass0:
186 case Hexagon::DuplexIClass1:
189 case Hexagon::DuplexIClass2:
192 case Hexagon::DuplexIClass3:
195 case Hexagon::DuplexIClass4:
198 case Hexagon::DuplexIClass5:
201 case Hexagon::DuplexIClass6:
204 case Hexagon::DuplexIClass7:
207 case Hexagon::DuplexIClass8:
210 case Hexagon::DuplexIClass9:
213 case Hexagon::DuplexIClassA:
216 case Hexagon::DuplexIClassB:
219 case Hexagon::DuplexIClassC:
222 case Hexagon::DuplexIClassD:
225 case Hexagon::DuplexIClassE:
228 case Hexagon::DuplexIClassF:
232 llvm_unreachable("Unimplemented DuplexIClass");
235 // 29 is the bit position.
236 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
237 // Last bit is moved to bit position 13
238 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
240 const MCInst *subInst0 = HMB.getOperand(0).getInst();
241 const MCInst *subInst1 = HMB.getOperand(1).getInst();
243 // get subinstruction slot 0
244 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
245 // get subinstruction slot 1
246 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
248 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
250 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
254 static Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI,
256 const MCSymbolRefExpr::VariantKind kind) {
257 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
258 unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI);
260 if (insnType == HexagonII::TypePREFIX) {
262 case llvm::MCSymbolRefExpr::VK_GOTOFF:
263 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
264 case llvm::MCSymbolRefExpr::VK_GOT:
265 return Hexagon::fixup_Hexagon_GOT_32_6_X;
266 case llvm::MCSymbolRefExpr::VK_TPREL:
267 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
268 case llvm::MCSymbolRefExpr::VK_DTPREL:
269 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
270 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
271 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
272 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
273 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
274 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
275 return Hexagon::fixup_Hexagon_IE_32_6_X;
276 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
277 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
280 return Hexagon::fixup_Hexagon_B32_PCREL_X;
282 return Hexagon::fixup_Hexagon_32_6_X;
284 } else if (MCID.isBranch())
285 return (Hexagon::fixup_Hexagon_B13_PCREL);
287 switch (MCID.getOpcode()) {
289 case Hexagon::A2_tfrih:
291 case llvm::MCSymbolRefExpr::VK_GOT:
292 return Hexagon::fixup_Hexagon_GOT_HI16;
293 case llvm::MCSymbolRefExpr::VK_GOTOFF:
294 return Hexagon::fixup_Hexagon_GOTREL_HI16;
295 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
296 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
297 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
298 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
299 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
300 return Hexagon::fixup_Hexagon_IE_HI16;
301 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
302 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
303 case llvm::MCSymbolRefExpr::VK_TPREL:
304 return Hexagon::fixup_Hexagon_TPREL_HI16;
305 case llvm::MCSymbolRefExpr::VK_DTPREL:
306 return Hexagon::fixup_Hexagon_DTPREL_HI16;
308 return Hexagon::fixup_Hexagon_HI16;
312 case Hexagon::A2_tfril:
314 case llvm::MCSymbolRefExpr::VK_GOT:
315 return Hexagon::fixup_Hexagon_GOT_LO16;
316 case llvm::MCSymbolRefExpr::VK_GOTOFF:
317 return Hexagon::fixup_Hexagon_GOTREL_LO16;
318 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
319 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
320 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
321 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
322 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
323 return Hexagon::fixup_Hexagon_IE_LO16;
324 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
325 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
326 case llvm::MCSymbolRefExpr::VK_TPREL:
327 return Hexagon::fixup_Hexagon_TPREL_LO16;
328 case llvm::MCSymbolRefExpr::VK_DTPREL:
329 return Hexagon::fixup_Hexagon_DTPREL_LO16;
331 return Hexagon::fixup_Hexagon_LO16;
334 // The only relocs left should be GP relative:
336 if (MCID.mayStore() || MCID.mayLoad()) {
337 for (const uint16_t *ImpUses = MCID.getImplicitUses(); *ImpUses;
339 if (*ImpUses == Hexagon::GP) {
340 switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
341 case HexagonII::MemAccessSize::ByteAccess:
342 return fixup_Hexagon_GPREL16_0;
343 case HexagonII::MemAccessSize::HalfWordAccess:
344 return fixup_Hexagon_GPREL16_1;
345 case HexagonII::MemAccessSize::WordAccess:
346 return fixup_Hexagon_GPREL16_2;
347 case HexagonII::MemAccessSize::DoubleWordAccess:
348 return fixup_Hexagon_GPREL16_3;
350 llvm_unreachable("unhandled fixup");
355 llvm_unreachable("unhandled fixup");
358 return LastTargetFixupKind;
362 extern const MCInstrDesc HexagonInsts[];
366 bool isPCRel (unsigned Kind) {
368 case fixup_Hexagon_B22_PCREL:
369 case fixup_Hexagon_B15_PCREL:
370 case fixup_Hexagon_B7_PCREL:
371 case fixup_Hexagon_B13_PCREL:
372 case fixup_Hexagon_B9_PCREL:
373 case fixup_Hexagon_B32_PCREL_X:
374 case fixup_Hexagon_B22_PCREL_X:
375 case fixup_Hexagon_B15_PCREL_X:
376 case fixup_Hexagon_B13_PCREL_X:
377 case fixup_Hexagon_B9_PCREL_X:
378 case fixup_Hexagon_B7_PCREL_X:
379 case fixup_Hexagon_32_PCREL:
380 case fixup_Hexagon_PLT_B22_PCREL:
381 case fixup_Hexagon_GD_PLT_B22_PCREL:
382 case fixup_Hexagon_LD_PLT_B22_PCREL:
383 case fixup_Hexagon_6_PCREL_X:
391 unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
394 SmallVectorImpl<MCFixup> &Fixups,
395 const MCSubtargetInfo &STI) const
400 if (ME->evaluateAsAbsolute(Res))
403 MCExpr::ExprKind MK = ME->getKind();
404 if (MK == MCExpr::Constant) {
405 return cast<MCConstantExpr>(ME)->getValue();
407 if (MK == MCExpr::Binary) {
409 Res = getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getLHS(), Fixups, STI);
411 getExprOpValue(MI, MO, cast<MCBinaryExpr>(ME)->getRHS(), Fixups, STI);
415 assert(MK == MCExpr::SymbolRef);
417 Hexagon::Fixups FixupKind =
418 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
419 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
420 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
421 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
422 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
423 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
425 DEBUG(dbgs() << "----------------------------------------\n");
426 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
428 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
429 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
430 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
431 DEBUG(dbgs() << "----------------------------------------\n");
435 DEBUG(dbgs() << "unrecognized bit count of " << bits << '\n');
440 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
441 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
443 case llvm::MCSymbolRefExpr::VK_GOT:
444 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
445 : Hexagon::fixup_Hexagon_GOT_32;
447 case llvm::MCSymbolRefExpr::VK_GOTOFF:
448 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
449 : Hexagon::fixup_Hexagon_GOTREL_32;
451 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
452 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
453 : Hexagon::fixup_Hexagon_GD_GOT_32;
455 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
456 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
457 : Hexagon::fixup_Hexagon_LD_GOT_32;
459 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
460 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
461 : Hexagon::fixup_Hexagon_IE_32;
463 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
464 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
465 : Hexagon::fixup_Hexagon_IE_GOT_32;
467 case llvm::MCSymbolRefExpr::VK_TPREL:
468 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
469 : Hexagon::fixup_Hexagon_TPREL_32;
471 case llvm::MCSymbolRefExpr::VK_DTPREL:
472 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
473 : Hexagon::fixup_Hexagon_DTPREL_32;
477 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
484 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_PLT:
485 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
487 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_PLT:
488 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
491 if (MCID.isBranch() || MCID.isCall()) {
492 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
493 : Hexagon::fixup_Hexagon_B22_PCREL;
495 errs() << "unrecognized relocation, bits: " << bits << "\n";
496 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
506 FixupKind = Hexagon::fixup_Hexagon_16_X;
508 case llvm::MCSymbolRefExpr::VK_GOT:
509 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
511 case llvm::MCSymbolRefExpr::VK_GOTOFF:
512 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
514 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
515 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
517 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
518 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
520 case llvm::MCSymbolRefExpr::VK_Hexagon_IE:
521 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
523 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
524 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
526 case llvm::MCSymbolRefExpr::VK_TPREL:
527 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
529 case llvm::MCSymbolRefExpr::VK_DTPREL:
530 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
536 errs() << "unrecognized relocation, bits " << bits << "\n";
537 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
539 case llvm::MCSymbolRefExpr::VK_GOTOFF:
540 if ((MCID.getOpcode() == Hexagon::HI) ||
541 (MCID.getOpcode() == Hexagon::LO_H))
542 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
544 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
546 case llvm::MCSymbolRefExpr::VK_Hexagon_GPREL:
547 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
549 case llvm::MCSymbolRefExpr::VK_Hexagon_LO16:
550 FixupKind = Hexagon::fixup_Hexagon_LO16;
552 case llvm::MCSymbolRefExpr::VK_Hexagon_HI16:
553 FixupKind = Hexagon::fixup_Hexagon_HI16;
555 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
556 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
558 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
559 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
561 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
562 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
564 case llvm::MCSymbolRefExpr::VK_TPREL:
565 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
567 case llvm::MCSymbolRefExpr::VK_DTPREL:
568 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
574 if (MCID.isBranch() || MCID.isCall())
575 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
576 : Hexagon::fixup_Hexagon_B15_PCREL;
581 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
583 errs() << "unrecognized relocation, bits " << bits << "\n";
584 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
592 FixupKind = Hexagon::fixup_Hexagon_12_X;
594 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
595 case llvm::MCSymbolRefExpr::VK_GOT:
596 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
598 case llvm::MCSymbolRefExpr::VK_GOTOFF:
599 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
603 errs() << "unrecognized relocation, bits " << bits << "\n";
604 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
612 FixupKind = Hexagon::fixup_Hexagon_11_X;
614 case llvm::MCSymbolRefExpr::VK_GOT:
615 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
617 case llvm::MCSymbolRefExpr::VK_GOTOFF:
618 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
620 case llvm::MCSymbolRefExpr::VK_Hexagon_GD_GOT:
621 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
623 case llvm::MCSymbolRefExpr::VK_Hexagon_LD_GOT:
624 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
626 case llvm::MCSymbolRefExpr::VK_Hexagon_IE_GOT:
627 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
629 case llvm::MCSymbolRefExpr::VK_TPREL:
630 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
632 case llvm::MCSymbolRefExpr::VK_DTPREL:
633 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
637 errs() << "unrecognized relocation, bits " << bits << "\n";
638 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
644 FixupKind = Hexagon::fixup_Hexagon_10_X;
648 if (MCID.isBranch() ||
649 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
650 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
651 : Hexagon::fixup_Hexagon_B9_PCREL;
653 FixupKind = Hexagon::fixup_Hexagon_9_X;
655 errs() << "unrecognized relocation, bits " << bits << "\n";
656 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
662 FixupKind = Hexagon::fixup_Hexagon_8_X;
664 errs() << "unrecognized relocation, bits " << bits << "\n";
665 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
670 if (MCID.isBranch() ||
671 (llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
672 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
673 : Hexagon::fixup_Hexagon_B7_PCREL;
675 FixupKind = Hexagon::fixup_Hexagon_7_X;
677 errs() << "unrecognized relocation, bits " << bits << "\n";
678 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
686 FixupKind = Hexagon::fixup_Hexagon_6_X;
688 case llvm::MCSymbolRefExpr::VK_Hexagon_PCREL:
689 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
691 // This is part of an extender, GOT_11 is a
692 // Word32_U6 unsigned/truncated reloc.
693 case llvm::MCSymbolRefExpr::VK_GOT:
694 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
696 case llvm::MCSymbolRefExpr::VK_GOTOFF:
697 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
701 errs() << "unrecognized relocation, bits " << bits << "\n";
702 errs() << "name = " << HexagonMCInstrInfo::getName(MCII, MI) << "\n";
707 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
711 MCExpr const *FixupExpression = (*Addend > 0 && isPCRel(FixupKind)) ?
712 MCBinaryExpr::createAdd(MO.getExpr(),
713 MCConstantExpr::create(*Addend, MCT), MCT) :
716 MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
717 MCFixupKind(FixupKind), MI.getLoc());
718 Fixups.push_back(fixup);
719 // All of the information is in the fixup.
724 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
725 SmallVectorImpl<MCFixup> &Fixups,
726 MCSubtargetInfo const &STI) const {
728 return MCT.getRegisterInfo()->getEncodingValue(MO.getReg());
730 return static_cast<unsigned>(MO.getImm());
734 return getExprOpValue(MI, MO, MO.getExpr(), Fixups, STI);
737 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
738 MCRegisterInfo const &MRI,
740 return new HexagonMCCodeEmitter(MII, MCT);
743 #include "HexagonGenMCCodeEmitter.inc"