1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
53 #define DEBUG_TYPE "packets"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56 cl::ZeroOrMore, cl::Hidden, cl::init(true),
57 cl::desc("Allow non-solo packetization of volatile memory references"));
60 void initializeHexagonPacketizerPass(PassRegistry&);
65 class HexagonPacketizer : public MachineFunctionPass {
69 HexagonPacketizer() : MachineFunctionPass(ID) {
70 initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
73 void getAnalysisUsage(AnalysisUsage &AU) const override {
75 AU.addRequired<MachineDominatorTree>();
76 AU.addRequired<MachineBranchProbabilityInfo>();
77 AU.addPreserved<MachineDominatorTree>();
78 AU.addRequired<MachineLoopInfo>();
79 AU.addPreserved<MachineLoopInfo>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 const char *getPassName() const override {
84 return "Hexagon Packetizer";
87 bool runOnMachineFunction(MachineFunction &Fn) override;
89 char HexagonPacketizer::ID = 0;
91 class HexagonPacketizerList : public VLIWPacketizerList {
95 // Has the instruction been promoted to a dot-new instruction.
96 bool PromotedToDotNew;
98 // Has the instruction been glued to allocframe.
99 bool GlueAllocframeStore;
101 // Has the feeder instruction been glued to new value jump.
102 bool GlueToNewValueJump;
104 // Check if there is a dependence between some instruction already in this
105 // packet and this instruction.
108 // Only check for dependence if there are resources available to
109 // schedule this instruction.
110 bool FoundSequentialDependence;
112 /// \brief A handle to the branch probability pass.
113 const MachineBranchProbabilityInfo *MBPI;
115 // Track MIs with ignored dependece.
116 std::vector<MachineInstr*> IgnoreDepMIs;
120 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
121 const MachineBranchProbabilityInfo *MBPI);
123 // initPacketizerState - initialize some internal flags.
124 void initPacketizerState() override;
126 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
127 bool ignorePseudoInstruction(MachineInstr *MI,
128 MachineBasicBlock *MBB) override;
130 // isSoloInstruction - return true if instruction MI can not be packetized
131 // with any other instruction, which means that MI itself is a packet.
132 bool isSoloInstruction(MachineInstr *MI) override;
134 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
136 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
138 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
140 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
142 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
144 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
145 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
146 MachineBasicBlock::iterator &MII,
147 const TargetRegisterClass* RC);
148 bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
149 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
150 MachineBasicBlock::iterator &MII,
151 const TargetRegisterClass *RC);
153 CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
154 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
155 MachineBasicBlock::iterator &MII);
156 bool CanPromoteToNewValueStore(
157 MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
158 const std::map<MachineInstr *, SUnit *> &MIToSUnit);
159 bool DemoteToDotOld(MachineInstr *MI);
160 bool ArePredicatesComplements(
161 MachineInstr *MI1, MachineInstr *MI2,
162 const std::map<MachineInstr *, SUnit *> &MIToSUnit);
163 bool RestrictingDepExistInPacket(MachineInstr *, unsigned,
164 const std::map<MachineInstr *, SUnit *> &);
165 bool isNewifiable(MachineInstr* MI);
166 bool isCondInst(MachineInstr* MI);
167 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
168 bool canReserveResourcesForConstExt(MachineInstr *MI);
169 void reserveResourcesForConstExt(MachineInstr* MI);
170 bool isNewValueInst(MachineInstr* MI);
174 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
176 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
177 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
178 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
179 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
180 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
184 // HexagonPacketizerList Ctor.
185 HexagonPacketizerList::HexagonPacketizerList(
186 MachineFunction &MF, MachineLoopInfo &MLI,
187 const MachineBranchProbabilityInfo *MBPI)
188 : VLIWPacketizerList(MF, MLI, true) {
192 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
193 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
194 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
195 const MachineBranchProbabilityInfo *MBPI =
196 &getAnalysis<MachineBranchProbabilityInfo>();
197 // Instantiate the packetizer.
198 HexagonPacketizerList Packetizer(Fn, MLI, MBPI);
200 // DFA state table should not be empty.
201 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
204 // Loop over all basic blocks and remove KILL pseudo-instructions
205 // These instructions confuse the dependence analysis. Consider:
207 // R0 = KILL R0, D0 (Insn 1)
209 // Here, Insn 1 will result in the dependence graph not emitting an output
210 // dependence between Insn 0 and Insn 2. This can lead to incorrect
213 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
214 MBB != MBBe; ++MBB) {
215 MachineBasicBlock::iterator End = MBB->end();
216 MachineBasicBlock::iterator MI = MBB->begin();
219 MachineBasicBlock::iterator DeleteMI = MI;
221 MBB->erase(DeleteMI);
229 // Loop over all of the basic blocks.
230 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
231 MBB != MBBe; ++MBB) {
232 // Find scheduling regions and schedule / packetize each region.
233 unsigned RemainingCount = MBB->size();
234 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
235 RegionEnd != MBB->begin();) {
236 // The next region starts above the previous region. Look backward in the
237 // instruction stream until we find the nearest boundary.
238 MachineBasicBlock::iterator I = RegionEnd;
239 for(;I != MBB->begin(); --I, --RemainingCount) {
240 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
245 // Skip empty scheduling regions.
246 if (I == RegionEnd) {
247 RegionEnd = std::prev(RegionEnd);
251 // Skip regions with one instruction.
252 if (I == std::prev(RegionEnd)) {
253 RegionEnd = std::prev(RegionEnd);
257 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
266 static bool IsIndirectCall(MachineInstr* MI) {
267 return MI->getOpcode() == Hexagon::J2_callr;
270 // Reserve resources for constant extender. Trigure an assertion if
272 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274 MachineFunction *MF = MI->getParent()->getParent();
275 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
278 if (ResourceTracker->canReserveResources(PseudoMI)) {
279 ResourceTracker->reserveResources(PseudoMI);
280 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
282 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
283 llvm_unreachable("can not reserve resources for constant extender.");
288 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
289 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
290 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
291 "Should only be called for constant extended instructions");
292 MachineFunction *MF = MI->getParent()->getParent();
293 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
295 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
296 MF->DeleteMachineInstr(PseudoMI);
300 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
301 // true, otherwise, return false.
302 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
303 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
304 MachineFunction *MF = MI->getParent()->getParent();
305 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::A4_ext),
308 if (ResourceTracker->canReserveResources(PseudoMI)) {
309 ResourceTracker->reserveResources(PseudoMI);
310 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
313 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
319 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
323 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
324 const HexagonRegisterInfo *QRI =
325 (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
327 // Check for lr dependence
328 if (DepReg == QRI->getRARegister()) {
332 if (QII->isDeallocRet(MI)) {
333 if (DepReg == QRI->getFrameRegister() ||
334 DepReg == QRI->getStackRegister())
338 // Check if this is a predicate dependence
339 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
340 if (RC == &Hexagon::PredRegsRegClass) {
345 // Lastly check for an operand used in an indirect call
346 // If we had an attribute for checking if an instruction is an indirect call,
347 // then we could have avoided this relatively brittle implementation of
350 // Assumes that the first operand of the CALLr is the function address
352 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
353 MachineOperand MO = MI->getOperand(0);
354 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
362 static bool IsRegDependence(const SDep::Kind DepType) {
363 return (DepType == SDep::Data || DepType == SDep::Anti ||
364 DepType == SDep::Output);
367 static bool IsDirectJump(MachineInstr* MI) {
368 return (MI->getOpcode() == Hexagon::J2_jump);
371 static bool IsSchedBarrier(MachineInstr* MI) {
372 switch (MI->getOpcode()) {
373 case Hexagon::Y2_barrier:
379 static bool IsControlFlow(MachineInstr* MI) {
380 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
383 static bool IsLoopN(MachineInstr *MI) {
384 return (MI->getOpcode() == Hexagon::J2_loop0i ||
385 MI->getOpcode() == Hexagon::J2_loop0r);
388 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
389 /// callee-saved register.
390 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
391 const TargetRegisterInfo *TRI) {
392 for (const MCPhysReg *CSR =
393 TRI->getCalleeSavedRegs(MI->getParent()->getParent());
395 unsigned CalleeSavedReg = *CSR;
396 if (MI->modifiesRegister(CalleeSavedReg, TRI))
402 // Returns true if an instruction can be promoted to .new predicate
403 // or new-value store.
404 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
405 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
406 if ( isCondInst(MI) || QII->mayBeNewStore(MI))
412 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
413 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
414 const MCInstrDesc& TID = MI->getDesc();
415 // bug 5670: until that is fixed,
416 // this portion is disabled.
417 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
418 || QII->isConditionalTransfer(MI)
419 || QII->isConditionalALU32(MI)
420 || QII->isConditionalLoad(MI)
421 || QII->isConditionalStore(MI)) {
428 // Promote an instructiont to its .new form.
429 // At this time, we have already made a call to CanPromoteToDotNew
430 // and made sure that it can *indeed* be promoted.
431 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
432 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
433 const TargetRegisterClass* RC) {
435 assert (DepType == SDep::Data);
436 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
439 if (RC == &Hexagon::PredRegsRegClass)
440 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
442 NewOpcode = QII->GetDotNewOp(MI);
443 MI->setDesc(QII->get(NewOpcode));
448 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
449 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
450 int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
451 MI->setDesc(QII->get(NewOpcode));
461 /// Returns true if an instruction is predicated on p0 and false if it's
462 /// predicated on !p0.
463 static PredicateKind getPredicateSense(MachineInstr* MI,
464 const HexagonInstrInfo *QII) {
465 if (!QII->isPredicated(MI))
468 if (QII->isPredicatedTrue(MI))
474 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
475 const HexagonInstrInfo *QII) {
476 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
478 // Post Increment means duplicates. Use dense map to find duplicates in the
479 // list. Caution: Densemap initializes with the minimum of 64 buckets,
480 // whereas there are at most 5 operands in the post increment.
481 DenseMap<unsigned, unsigned> DefRegsSet;
482 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
483 if (MI->getOperand(opNum).isReg() &&
484 MI->getOperand(opNum).isDef()) {
485 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
488 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
489 if (MI->getOperand(opNum).isReg() &&
490 MI->getOperand(opNum).isUse()) {
491 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
492 return MI->getOperand(opNum);
496 if (MI->getDesc().mayLoad()) {
497 // The 2nd operand is always the post increment operand in load.
498 assert(MI->getOperand(1).isReg() &&
499 "Post increment operand has be to a register.");
500 return (MI->getOperand(1));
502 if (MI->getDesc().mayStore()) {
503 // The 1st operand is always the post increment operand in store.
504 assert(MI->getOperand(0).isReg() &&
505 "Post increment operand has be to a register.");
506 return (MI->getOperand(0));
509 // we should never come here.
510 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
513 // get the value being stored
514 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
515 // value being stored is always the last operand.
516 return (MI->getOperand(MI->getNumOperands()-1));
519 // can be new value store?
520 // Following restrictions are to be respected in convert a store into
521 // a new value store.
522 // 1. If an instruction uses auto-increment, its address register cannot
523 // be a new-value register. Arch Spec 5.4.2.1
524 // 2. If an instruction uses absolute-set addressing mode,
525 // its address register cannot be a new-value register.
526 // Arch Spec 5.4.2.1.TODO: This is not enabled as
527 // as absolute-set address mode patters are not implemented.
528 // 3. If an instruction produces a 64-bit result, its registers cannot be used
529 // as new-value registers. Arch Spec 5.4.2.2.
530 // 4. If the instruction that sets a new-value register is conditional, then
531 // the instruction that uses the new-value register must also be conditional,
532 // and both must always have their predicates evaluate identically.
533 // Arch Spec 5.4.2.3.
534 // 5. There is an implied restriction of a packet can not have another store,
535 // if there is a new value store in the packet. Corollary, if there is
536 // already a store in a packet, there can not be a new value store.
537 // Arch Spec: 3.4.4.2
538 bool HexagonPacketizerList::CanPromoteToNewValueStore(
539 MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
540 const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
541 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
542 // Make sure we are looking at the store, that can be promoted.
543 if (!QII->mayBeNewStore(MI))
546 // Make sure there is dependency and can be new value'ed
547 if (GetStoreValueOperand(MI).isReg() &&
548 GetStoreValueOperand(MI).getReg() != DepReg)
551 const HexagonRegisterInfo *QRI =
552 (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
553 const MCInstrDesc& MCID = PacketMI->getDesc();
554 // first operand is always the result
556 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
558 // if there is already an store in the packet, no can do new value store
559 // Arch Spec 3.4.4.2.
560 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
561 VE = CurrentPacketMIs.end();
563 SUnit *PacketSU = MIToSUnit.find(*VI)->second;
564 if (PacketSU->getInstr()->getDesc().mayStore() ||
565 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
566 // then we don't need this
567 PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
568 PacketSU->getInstr()->getOpcode() == Hexagon::L2_deallocframe)
572 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
573 // new value store constraint: double regs can not feed into new value store
574 // arch spec section: 5.4.2.2
578 // Make sure it's NOT the post increment register that we are going to
580 if (QII->isPostIncrement(MI) &&
581 MI->getDesc().mayStore() &&
582 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
586 if (QII->isPostIncrement(PacketMI) &&
587 PacketMI->getDesc().mayLoad() &&
588 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
589 // if source is post_inc, or absolute-set addressing,
590 // it can not feed into new value store
592 // memw(r30 + #-1404) = r2.new -> can not be new value store
593 // arch spec section: 5.4.2.1
597 // If the source that feeds the store is predicated, new value store must
598 // also be predicated.
599 if (QII->isPredicated(PacketMI)) {
600 if (!QII->isPredicated(MI))
603 // Check to make sure that they both will have their predicates
604 // evaluate identically
605 unsigned predRegNumSrc = 0;
606 unsigned predRegNumDst = 0;
607 const TargetRegisterClass* predRegClass = nullptr;
609 // Get predicate register used in the source instruction
610 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
611 if ( PacketMI->getOperand(opNum).isReg())
612 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
613 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
614 if (predRegClass == &Hexagon::PredRegsRegClass) {
618 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
619 ("predicate register not found in a predicated PacketMI instruction"));
621 // Get predicate register used in new-value store instruction
622 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
623 if ( MI->getOperand(opNum).isReg())
624 predRegNumDst = MI->getOperand(opNum).getReg();
625 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
626 if (predRegClass == &Hexagon::PredRegsRegClass) {
630 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
631 ("predicate register not found in a predicated MI instruction"));
633 // New-value register producer and user (store) need to satisfy these
635 // 1) Both instructions should be predicated on the same register.
636 // 2) If producer of the new-value register is .new predicated then store
637 // should also be .new predicated and if producer is not .new predicated
638 // then store should not be .new predicated.
639 // 3) Both new-value register producer and user should have same predicate
640 // sense, i.e, either both should be negated or both should be none negated.
642 if (( predRegNumDst != predRegNumSrc) ||
643 QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
644 getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
649 // Make sure that other than the new-value register no other store instruction
650 // register has been modified in the same packet. Predicate registers can be
651 // modified by they should not be modified between the producer and the store
652 // instruction as it will make them both conditional on different values.
653 // We already know this to be true for all the instructions before and
654 // including PacketMI. Howerver, we need to perform the check for the
655 // remaining instructions in the packet.
657 std::vector<MachineInstr*>::iterator VI;
658 std::vector<MachineInstr*>::iterator VE;
659 unsigned StartCheck = 0;
661 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
663 SUnit *TempSU = MIToSUnit.find(*VI)->second;
664 MachineInstr* TempMI = TempSU->getInstr();
666 // Following condition is true for all the instructions until PacketMI is
667 // reached (StartCheck is set to 0 before the for loop).
668 // StartCheck flag is 1 for all the instructions after PacketMI.
669 if (TempMI != PacketMI && !StartCheck) // start processing only after
670 continue; // encountering PacketMI
673 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
676 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
677 if (MI->getOperand(opNum).isReg() &&
678 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
684 // Make sure that for non-POST_INC stores:
685 // 1. The only use of reg is DepReg and no other registers.
686 // This handles V4 base+index registers.
687 // The following store can not be dot new.
688 // Eg. r0 = add(r0, #3)a
689 // memw(r1+r0<<#2) = r0
690 if (!QII->isPostIncrement(MI) &&
691 GetStoreValueOperand(MI).isReg() &&
692 GetStoreValueOperand(MI).getReg() == DepReg) {
693 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
694 if (MI->getOperand(opNum).isReg() &&
695 MI->getOperand(opNum).getReg() == DepReg) {
699 // 2. If data definition is because of implicit definition of the register,
700 // do not newify the store. Eg.
701 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
702 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
703 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
704 if (PacketMI->getOperand(opNum).isReg() &&
705 PacketMI->getOperand(opNum).getReg() == DepReg &&
706 PacketMI->getOperand(opNum).isDef() &&
707 PacketMI->getOperand(opNum).isImplicit()) {
713 // Can be dot new store.
717 // can this MI to promoted to either
718 // new value store or new value jump
719 bool HexagonPacketizerList::CanPromoteToNewValue(
720 MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
721 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
722 MachineBasicBlock::iterator &MII) {
724 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
725 if (!QII->mayBeNewStore(MI))
728 MachineInstr *PacketMI = PacketSU->getInstr();
730 // Check to see the store can be new value'ed.
731 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
734 // Check to see the compare/jump can be new value'ed.
735 // This is done as a pass on its own. Don't need to check it here.
739 // Check to see if an instruction can be dot new
740 // There are three kinds.
741 // 1. dot new on predicate - V2/V3/V4
742 // 2. dot new on stores NV/ST - V4
743 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
744 bool HexagonPacketizerList::CanPromoteToDotNew(
745 MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
746 const std::map<MachineInstr *, SUnit *> &MIToSUnit,
747 MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) {
748 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
749 // Already a dot new instruction.
750 if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
753 if (!isNewifiable(MI))
757 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
759 else if (RC != &Hexagon::PredRegsRegClass &&
760 !QII->mayBeNewStore(MI)) // MI is not a new-value store
763 // Create a dot new machine instruction to see if resources can be
764 // allocated. If not, bail out now.
765 int NewOpcode = QII->GetDotNewOp(MI);
766 const MCInstrDesc &desc = QII->get(NewOpcode);
768 MachineInstr *NewMI =
769 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
770 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
771 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
773 if (!ResourcesAvailable)
776 // new value store only
777 // new new value jump generated as a passes
778 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
785 // Go through the packet instructions and search for anti dependency
786 // between them and DepReg from MI
787 // Consider this case:
789 // a) %R1<def> = TFRI_cdNotPt %P3, 2
792 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
793 // c) %P3<def> = TFR_PdRs %R23
794 // d) %R1<def> = TFRI_cdnPt %P3, 4
796 // The P3 from a) and d) will be complements after
797 // a)'s P3 is converted to .new form
798 // Anti Dep between c) and b) is irrelevant for this case
799 bool HexagonPacketizerList::RestrictingDepExistInPacket(
800 MachineInstr *MI, unsigned DepReg,
801 const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
803 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
804 SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
806 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
807 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
809 // We only care for dependencies to predicated instructions
810 if(!QII->isPredicated(*VIN)) continue;
812 // Scheduling Unit for current insn in the packet
813 SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
815 // Look at dependencies between current members of the packet
816 // and predicate defining instruction MI.
817 // Make sure that dependency is on the exact register
819 if (PacketSU->isSucc(PacketSUDep)) {
820 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
821 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
822 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
823 (PacketSU->Succs[i].getReg() == DepReg)) {
834 /// Gets the predicate register of a predicated instruction.
835 static unsigned getPredicatedRegister(MachineInstr *MI,
836 const HexagonInstrInfo *QII) {
837 /// We use the following rule: The first predicate register that is a use is
838 /// the predicate register of a predicated instruction.
840 assert(QII->isPredicated(MI) && "Must be predicated instruction");
842 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
843 OE = MI->operands_end(); OI != OE; ++OI) {
844 MachineOperand &Op = *OI;
845 if (Op.isReg() && Op.getReg() && Op.isUse() &&
846 Hexagon::PredRegsRegClass.contains(Op.getReg()))
850 llvm_unreachable("Unknown instruction operand layout");
855 // Given two predicated instructions, this function detects whether
856 // the predicates are complements
857 bool HexagonPacketizerList::ArePredicatesComplements(
858 MachineInstr *MI1, MachineInstr *MI2,
859 const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
861 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
863 // If we don't know the predicate sense of the instructions bail out early, we
865 if (getPredicateSense(MI1, QII) == PK_Unknown ||
866 getPredicateSense(MI2, QII) == PK_Unknown)
869 // Scheduling unit for candidate
870 SUnit *SU = MIToSUnit.find(MI1)->second;
872 // One corner case deals with the following scenario:
874 // a) %R24<def> = TFR_cPt %P0, %R25
878 // b) %R25<def> = TFR_cNotPt %P0, %R24
879 // c) %P0<def> = CMPEQri %R26, 1
882 // On general check a) and b) are complements, but
883 // presence of c) will convert a) to .new form, and
884 // then it is not a complement
885 // We attempt to detect it by analyzing existing
886 // dependencies in the packet
888 // Analyze relationships between all existing members of the packet.
889 // Look for Anti dependecy on the same predicate reg
890 // as used in the candidate
891 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
892 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
894 // Scheduling Unit for current insn in the packet
895 SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
897 // If this instruction in the packet is succeeded by the candidate...
898 if (PacketSU->isSucc(SU)) {
899 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
900 // The corner case exist when there is true data
901 // dependency between candidate and one of current
902 // packet members, this dep is on predicate reg, and
903 // there already exist anti dep on the same pred in
905 if (PacketSU->Succs[i].getSUnit() == SU &&
906 PacketSU->Succs[i].getKind() == SDep::Data &&
907 Hexagon::PredRegsRegClass.contains(
908 PacketSU->Succs[i].getReg()) &&
909 // Here I know that *VIN is predicate setting instruction
910 // with true data dep to candidate on the register
911 // we care about - c) in the above example.
912 // Now I need to see if there is an anti dependency
913 // from c) to any other instruction in the
914 // same packet on the pred reg of interest
915 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
923 // If the above case does not apply, check regular
924 // complement condition.
925 // Check that the predicate register is the same and
926 // that the predicate sense is different
927 // We also need to differentiate .old vs. .new:
928 // !p0 is not complimentary to p0.new
929 unsigned PReg1 = getPredicatedRegister(MI1, QII);
930 unsigned PReg2 = getPredicatedRegister(MI2, QII);
931 return ((PReg1 == PReg2) &&
932 Hexagon::PredRegsRegClass.contains(PReg1) &&
933 Hexagon::PredRegsRegClass.contains(PReg2) &&
934 (getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
935 (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
938 // initPacketizerState - Initialize packetizer flags
939 void HexagonPacketizerList::initPacketizerState() {
942 PromotedToDotNew = false;
943 GlueToNewValueJump = false;
944 GlueAllocframeStore = false;
945 FoundSequentialDependence = false;
950 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
951 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
952 MachineBasicBlock *MBB) {
953 if (MI->isDebugValue())
956 // We must print out inline assembly
957 if (MI->isInlineAsm())
960 // We check if MI has any functional units mapped to it.
961 // If it doesn't, we ignore the instruction.
962 const MCInstrDesc& TID = MI->getDesc();
963 unsigned SchedClass = TID.getSchedClass();
964 const InstrStage* IS =
965 ResourceTracker->getInstrItins()->beginStage(SchedClass);
966 unsigned FuncUnits = IS->getUnits();
970 // isSoloInstruction: - Returns true for instructions that must be
971 // scheduled in their own packet.
972 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
974 if (MI->isInlineAsm())
980 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
981 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
982 // They must not be grouped with other instructions in a packet.
983 if (IsSchedBarrier(MI))
989 // isLegalToPacketizeTogether:
990 // SUI is the current instruction that is out side of the current packet.
991 // SUJ is the current instruction inside the current packet against which that
992 // SUI will be packetized.
993 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
994 MachineInstr *I = SUI->getInstr();
995 MachineInstr *J = SUJ->getInstr();
996 assert(I && J && "Unable to packetize null instruction!");
998 const MCInstrDesc &MCIDI = I->getDesc();
999 const MCInstrDesc &MCIDJ = J->getDesc();
1001 MachineBasicBlock::iterator II = I;
1003 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1004 const HexagonRegisterInfo *QRI =
1005 (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
1006 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1008 // Inline asm cannot go in the packet.
1009 if (I->getOpcode() == Hexagon::INLINEASM)
1010 llvm_unreachable("Should not meet inline asm here!");
1012 if (isSoloInstruction(I))
1013 llvm_unreachable("Should not meet solo instr here!");
1015 // A save callee-save register function call can only be in a packet
1016 // with instructions that don't write to the callee-save registers.
1017 if ((QII->isSaveCalleeSavedRegsCall(I) &&
1018 DoesModifyCalleeSavedReg(J, QRI)) ||
1019 (QII->isSaveCalleeSavedRegsCall(J) &&
1020 DoesModifyCalleeSavedReg(I, QRI))) {
1025 // Two control flow instructions cannot go in the same packet.
1026 if (IsControlFlow(I) && IsControlFlow(J)) {
1031 // A LoopN instruction cannot appear in the same packet as a jump or call.
1033 (IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
1038 (IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
1043 // dealloc_return cannot appear in the same packet as a conditional or
1044 // unconditional jump.
1045 if (QII->isDeallocRet(I) &&
1046 (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
1052 // V4 allows dual store. But does not allow second store, if the
1053 // first store is not in SLOT0. New value store, new value jump,
1054 // dealloc_return and memop always take SLOT0.
1055 // Arch spec 3.4.4.2
1056 if (MCIDI.mayStore() && MCIDJ.mayStore() &&
1057 (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
1062 if ((QII->isMemOp(J) && MCIDI.mayStore())
1063 || (MCIDJ.mayStore() && QII->isMemOp(I))
1064 || (QII->isMemOp(J) && QII->isMemOp(I))) {
1070 if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
1075 // If an instruction feeds new value jump, glue it.
1076 MachineBasicBlock::iterator NextMII = I;
1078 if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
1079 MachineInstr *NextMI = NextMII;
1081 bool secondRegMatch = false;
1082 bool maintainNewValueJump = false;
1084 if (NextMI->getOperand(1).isReg() &&
1085 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
1086 secondRegMatch = true;
1087 maintainNewValueJump = true;
1090 if (!secondRegMatch &&
1091 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
1092 maintainNewValueJump = true;
1095 for (std::vector<MachineInstr*>::iterator
1096 VI = CurrentPacketMIs.begin(),
1097 VE = CurrentPacketMIs.end();
1098 (VI != VE && maintainNewValueJump); ++VI) {
1099 SUnit *PacketSU = MIToSUnit.find(*VI)->second;
1101 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
1102 if (PacketSU->getInstr()->getDesc().isCall()) {
1107 // 1. Packet does not have a store in it.
1108 // 2. If the first operand of the nvj is newified, and the second
1109 // operand is also a reg, it (second reg) is not defined in
1111 // 3. If the second operand of the nvj is newified, (which means
1112 // first operand is also a reg), first reg is not defined in
1114 if (PacketSU->getInstr()->getDesc().mayStore() ||
1115 PacketSU->getInstr()->getOpcode() == Hexagon::S2_allocframe ||
1117 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
1118 PacketSU->getInstr()->modifiesRegister(
1119 NextMI->getOperand(1).getReg(), QRI)) ||
1122 PacketSU->getInstr()->modifiesRegister(
1123 NextMI->getOperand(0).getReg(), QRI))) {
1129 GlueToNewValueJump = true;
1134 if (SUJ->isSucc(SUI)) {
1135 for (unsigned i = 0;
1136 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
1139 if (SUJ->Succs[i].getSUnit() != SUI) {
1143 SDep::Kind DepType = SUJ->Succs[i].getKind();
1145 // For direct calls:
1146 // Ignore register dependences for call instructions for
1147 // packetization purposes except for those due to r31 and
1148 // predicate registers.
1150 // For indirect calls:
1151 // Same as direct calls + check for true dependences to the register
1152 // used in the indirect call.
1154 // We completely ignore Order dependences for call instructions
1157 // Ignore register dependences for return instructions like jumpr,
1158 // dealloc return unless we have dependencies on the explicit uses
1159 // of the registers used by jumpr (like r31) or dealloc return
1160 // (like r29 or r30).
1162 // TODO: Currently, jumpr is handling only return of r31. So, the
1163 // following logic (specificaly IsCallDependent) is working fine.
1164 // We need to enable jumpr for register other than r31 and then,
1165 // we need to rework the last part, where it handles indirect call
1166 // of that (IsCallDependent) function. Bug 6216 is opened for this.
1168 unsigned DepReg = 0;
1169 const TargetRegisterClass* RC = nullptr;
1170 if (DepType == SDep::Data) {
1171 DepReg = SUJ->Succs[i].getReg();
1172 RC = QRI->getMinimalPhysRegClass(DepReg);
1174 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
1175 (!IsRegDependence(DepType) ||
1176 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
1180 // For instructions that can be promoted to dot-new, try to promote.
1181 else if ((DepType == SDep::Data) &&
1182 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
1183 PromoteToDotNew(I, DepType, II, RC)) {
1184 PromotedToDotNew = true;
1188 else if ((DepType == SDep::Data) &&
1189 (QII->isNewValueJump(I))) {
1193 // For predicated instructions, if the predicates are complements
1194 // then there can be no dependence.
1195 else if (QII->isPredicated(I) &&
1196 QII->isPredicated(J) &&
1197 ArePredicatesComplements(I, J, MIToSUnit)) {
1201 else if (IsDirectJump(I) &&
1202 !MCIDJ.isBranch() &&
1204 (DepType == SDep::Order)) {
1205 // Ignore Order dependences between unconditional direct branches
1206 // and non-control-flow instructions
1209 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
1210 (DepType != SDep::Output)) {
1211 // Ignore all dependences for jumps except for true and output
1216 // Ignore output dependences due to superregs. We can
1217 // write to two different subregisters of R1:0 for instance
1218 // in the same cycle
1223 // If neither I nor J defines DepReg, then this is a
1224 // superfluous output dependence. The dependence must be of the
1228 // and there is an output dependence between the two instructions
1231 // We want to ignore these dependences.
1232 // Ideally, the dependence constructor should annotate such
1233 // dependences. We can then avoid this relatively expensive check.
1235 else if (DepType == SDep::Output) {
1236 // DepReg is the register that's responsible for the dependence.
1237 unsigned DepReg = SUJ->Succs[i].getReg();
1239 // Check if I and J really defines DepReg.
1240 if (I->definesRegister(DepReg) ||
1241 J->definesRegister(DepReg)) {
1242 FoundSequentialDependence = true;
1247 // We ignore Order dependences for
1248 // 1. Two loads unless they are volatile.
1249 // 2. Two stores in V4 unless they are volatile.
1250 else if ((DepType == SDep::Order) &&
1251 !I->hasOrderedMemoryRef() &&
1252 !J->hasOrderedMemoryRef()) {
1253 if (MCIDI.mayStore() && MCIDJ.mayStore()) {
1256 // store followed by store-- not OK on V2
1257 // store followed by load -- not OK on all (OK if addresses
1259 // load followed by store -- OK on all
1260 // load followed by load -- OK on all
1261 else if ( !MCIDJ.mayStore()) {
1265 FoundSequentialDependence = true;
1270 // For V4, special case ALLOCFRAME. Even though there is dependency
1271 // between ALLOCFRAME and subsequent store, allow it to be
1272 // packetized in a same packet. This implies that the store is using
1273 // caller's SP. Hence, offset needs to be updated accordingly.
1274 else if (DepType == SDep::Data
1275 && J->getOpcode() == Hexagon::S2_allocframe
1276 && (I->getOpcode() == Hexagon::S2_storerd_io
1277 || I->getOpcode() == Hexagon::S2_storeri_io
1278 || I->getOpcode() == Hexagon::S2_storerb_io)
1279 && I->getOperand(0).getReg() == QRI->getStackRegister()
1280 && QII->isValidOffset(I->getOpcode(),
1281 I->getOperand(1).getImm() -
1282 (FrameSize + HEXAGON_LRFP_SIZE)))
1284 GlueAllocframeStore = true;
1285 // Since this store is to be glued with allocframe in the same
1286 // packet, it will use SP of the previous stack frame, i.e
1287 // caller's SP. Therefore, we need to recalculate offset according
1289 I->getOperand(1).setImm(I->getOperand(1).getImm() -
1290 (FrameSize + HEXAGON_LRFP_SIZE));
1294 // Skip over anti-dependences. Two instructions that are
1295 // anti-dependent can share a packet
1297 else if (DepType != SDep::Anti) {
1298 FoundSequentialDependence = true;
1303 if (FoundSequentialDependence) {
1312 // isLegalToPruneDependencies
1313 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1314 MachineInstr *I = SUI->getInstr();
1315 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
1317 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1321 // Check if the instruction was promoted to a dot-new. If so, demote it
1322 // back into a dot-old.
1323 if (PromotedToDotNew) {
1327 // Check if the instruction (must be a store) was glued with an Allocframe
1328 // instruction. If so, restore its offset to its original value, i.e. use
1329 // curent SP instead of caller's SP.
1330 if (GlueAllocframeStore) {
1331 I->getOperand(1).setImm(I->getOperand(1).getImm() +
1332 FrameSize + HEXAGON_LRFP_SIZE);
1340 MachineBasicBlock::iterator
1341 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
1343 MachineBasicBlock::iterator MII = MI;
1344 MachineBasicBlock *MBB = MI->getParent();
1346 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1348 if (GlueToNewValueJump) {
1351 MachineInstr *nvjMI = MII;
1352 assert(ResourceTracker->canReserveResources(MI));
1353 ResourceTracker->reserveResources(MI);
1354 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
1355 !tryAllocateResourcesForConstExt(MI)) {
1357 ResourceTracker->reserveResources(MI);
1358 assert(canReserveResourcesForConstExt(MI) &&
1359 "Ensure that there is a slot");
1360 reserveResourcesForConstExt(MI);
1361 // Reserve resources for new value jump constant extender.
1362 assert(canReserveResourcesForConstExt(MI) &&
1363 "Ensure that there is a slot");
1364 reserveResourcesForConstExt(nvjMI);
1365 assert(ResourceTracker->canReserveResources(nvjMI) &&
1366 "Ensure that there is a slot");
1368 } else if ( // Extended instruction takes two slots in the packet.
1369 // Try reserve and allocate 4-byte in the current packet first.
1370 (QII->isExtended(nvjMI)
1371 && (!tryAllocateResourcesForConstExt(nvjMI)
1372 || !ResourceTracker->canReserveResources(nvjMI)))
1373 || // For non-extended instruction, no need to allocate extra 4 bytes.
1374 (!QII->isExtended(nvjMI) &&
1375 !ResourceTracker->canReserveResources(nvjMI)))
1378 // A new and empty packet starts.
1379 // We are sure that the resources requirements can be satisfied.
1380 // Therefore, do not need to call "canReserveResources" anymore.
1381 ResourceTracker->reserveResources(MI);
1382 if (QII->isExtended(nvjMI))
1383 reserveResourcesForConstExt(nvjMI);
1385 // Here, we are sure that "reserveResources" would succeed.
1386 ResourceTracker->reserveResources(nvjMI);
1387 CurrentPacketMIs.push_back(MI);
1388 CurrentPacketMIs.push_back(nvjMI);
1390 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
1391 && ( !tryAllocateResourcesForConstExt(MI)
1392 || !ResourceTracker->canReserveResources(MI)))
1395 // Check if the instruction was promoted to a dot-new. If so, demote it
1396 // back into a dot-old
1397 if (PromotedToDotNew) {
1400 reserveResourcesForConstExt(MI);
1402 // In case that "MI" is not an extended insn,
1403 // the resource availability has already been checked.
1404 ResourceTracker->reserveResources(MI);
1405 CurrentPacketMIs.push_back(MI);
1410 //===----------------------------------------------------------------------===//
1411 // Public Constructor Functions
1412 //===----------------------------------------------------------------------===//
1414 FunctionPass *llvm::createHexagonPacketizer() {
1415 return new HexagonPacketizer();