lib/Target/Hexagon/HexagonTargetMachine.cpp

   1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // Implements the info about Hexagon target spec.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "HexagonTargetMachine.h"
  15 #include "Hexagon.h"
  16 #include "HexagonISelLowering.h"
  17 #include "llvm/Module.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/PassManager.h"
  20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
  21 #include "llvm/Transforms/Scalar.h"
  22 #include "llvm/Support/CommandLine.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 static cl::
  28 opt<bool> DisableHardwareLoops(
  29                         "disable-hexagon-hwloops", cl::Hidden,
  30                         cl::desc("Disable Hardware Loops for Hexagon target"));
  31 static cl::
  32 opt<bool> DisableCExtOpt(
  33                         "disable-hexagon-cextopt", cl::Hidden,
  34                         cl::desc("Disable Optimization of Constant Extenders"));
  35
  36 /// HexagonTargetMachineModule - Note that this is used on hosts that
  37 /// cannot link in a library unless there are references into the
  38 /// library.  In particular, it seems that it is not possible to get
  39 /// things to work on Win32 without this.  Though it is unused, do not
  40 /// remove it.
  41 extern "C" int HexagonTargetMachineModule;
  42 int HexagonTargetMachineModule = 0;
  43
  44 extern "C" void LLVMInitializeHexagonTarget() {
  45   // Register the target.
  46   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
  47 }
  48
  49
  50 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
  51 ///
  52
  53 /// Hexagon_TODO: Do I need an aggregate alignment?
  54 ///
  55 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
  56                                            StringRef CPU, StringRef FS,
  57                                            const TargetOptions &Options,
  58                                            Reloc::Model RM,
  59                                            CodeModel::Model CM,
  60                                            CodeGenOpt::Level OL)
  61   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  62     DataLayout("e-p:32:32:32-"
  63                 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
  64                 "f64:64:64-f32:32:32-a0:0-n32") ,
  65     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
  66     TSInfo(*this),
  67     FrameLowering(Subtarget),
  68     InstrItins(&Subtarget.getInstrItineraryData()) {
  69   setMCUseCFI(false);
  70 }
  71
  72 // addPassesForOptimizations - Allow the backend (target) to add Target
  73 // Independent Optimization passes to the Pass Manager.
  74 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
  75
  76   PM.add(createConstantPropagationPass());
  77   PM.add(createLoopSimplifyPass());
  78   PM.add(createDeadCodeEliminationPass());
  79   PM.add(createConstantPropagationPass());
  80   PM.add(createLoopUnrollPass());
  81   PM.add(createLoopStrengthReducePass(getTargetLowering()));
  82   return true;
  83 }
  84
  85 namespace {
  86 /// Hexagon Code Generator Pass Configuration Options.
  87 class HexagonPassConfig : public TargetPassConfig {
  88 public:
  89   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
  90     : TargetPassConfig(TM, PM) {}
  91
  92   HexagonTargetMachine &getHexagonTargetMachine() const {
  93     return getTM<HexagonTargetMachine>();
  94   }
  95
  96   virtual bool addInstSelector();
  97   virtual bool addPreRegAlloc();
  98   virtual bool addPostRegAlloc();
  99   virtual bool addPreSched2();
 100   virtual bool addPreEmitPass();
 101 };
 102 } // namespace
 103
 104 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
 105   return new HexagonPassConfig(this, PM);
 106 }
 107
 108 bool HexagonPassConfig::addInstSelector() {
 109   PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
 110   PM->add(createHexagonISelDag(getHexagonTargetMachine()));
 111   PM->add(createHexagonPeephole());
 112   return false;
 113 }
 114
 115
 116 bool HexagonPassConfig::addPreRegAlloc() {
 117   if (!DisableCExtOpt) {
 118     PM->add(createHexagonOptimizeConstExt(getHexagonTargetMachine()));
 119   }
 120   if (!DisableHardwareLoops) {
 121     PM->add(createHexagonHardwareLoops());
 122   }
 123   return false;
 124 }
 125
 126 bool HexagonPassConfig::addPostRegAlloc() {
 127   PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
 128   return true;
 129 }
 130
 131
 132 bool HexagonPassConfig::addPreSched2() {
 133   addPass(IfConverterID);
 134   return true;
 135 }
 136
 137 bool HexagonPassConfig::addPreEmitPass() {
 138
 139   if (!DisableHardwareLoops) {
 140     PM->add(createHexagonFixupHwLoops());
 141   }
 142
 143   PM->add(createHexagonNewValueJump());
 144
 145   // Expand Spill code for predicate registers.
 146   PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
 147
 148   // Split up TFRcondsets into conditional transfers.
 149   PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
 150
 151   // Create Packets.
 152   PM->add(createHexagonPacketizer());
 153
 154   return false;
 155 }