1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but becuase we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this ealier at some piont
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "llvm/PassSupport.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "HexagonTargetMachine.h"
42 #include "HexagonRegisterInfo.h"
43 #include "HexagonSubtarget.h"
44 #include "HexagonInstrInfo.h"
45 #include "HexagonMachineFunctionInfo.h"
49 #include "llvm/Support/CommandLine.h"
52 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
54 cl::opt<int> DebugHexagonNewValueJump("debug-nvj", cl::Hidden, cl::desc(""));
57 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
58 "Maximum number of predicated jumps to be converted to New Value Jump"));
60 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
61 cl::ZeroOrMore, cl::init(false),
62 cl::desc("Disable New Value Jumps"));
65 struct HexagonNewValueJump : public MachineFunctionPass {
66 const HexagonInstrInfo *QII;
67 const HexagonRegisterInfo *QRI;
72 HexagonNewValueJump() : MachineFunctionPass(ID) { }
74 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
75 MachineFunctionPass::getAnalysisUsage(AU);
78 const char *getPassName() const {
79 return "Hexagon NewValueJump";
82 virtual bool runOnMachineFunction(MachineFunction &Fn);
88 } // end of anonymous namespace
90 char HexagonNewValueJump::ID = 0;
92 // We have identified this II could be feeder to NVJ,
93 // verify that it can be.
94 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
95 const TargetRegisterInfo *TRI,
96 MachineBasicBlock::iterator II,
97 MachineBasicBlock::iterator end,
98 MachineBasicBlock::iterator skip,
99 MachineFunction &MF) {
101 // Predicated instruction can not be feeder to NVJ.
102 if (QII->isPredicated(II))
105 // Bail out if feederReg is a paired register (double regs in
106 // our case). One would think that we can check to see if a given
107 // register cmpReg1 or cmpReg2 is a sub register of feederReg
108 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
109 // before the callsite of this function
110 // But we can not as it comes in the following fashion.
111 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
112 // %R0<def> = KILL %R0, %D0<imp-use,kill>
113 // %P0<def> = CMPEQri %R0<kill>, 0
114 // Hence, we need to check if it's a KILL instruction.
115 if (II->getOpcode() == TargetOpcode::KILL)
119 // Make sure there there is no 'def' or 'use' of any of the uses of
120 // feeder insn between it's definition, this MI and jump, jmpInst
121 // skipping compare, cmpInst.
122 // Here's the example.
123 // r21=memub(r22+r24<<#0)
124 // p0 = cmp.eq(r21, #0)
125 // r4=memub(r3+r21<<#0)
126 // if (p0.new) jump:t .LBB29_45
127 // Without this check, it will be converted into
128 // r4=memub(r3+r21<<#0)
129 // r21=memub(r22+r24<<#0)
130 // p0 = cmp.eq(r21, #0)
131 // if (p0.new) jump:t .LBB29_45
132 // and result WAR hazards if converted to New Value Jump.
134 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
135 if (II->getOperand(i).isReg() &&
136 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
137 MachineBasicBlock::iterator localII = II;
139 unsigned Reg = II->getOperand(i).getReg();
140 for (MachineBasicBlock::iterator localBegin = localII;
141 localBegin != end; ++localBegin) {
142 if (localBegin == skip ) continue;
143 // Check for Subregisters too.
144 if (localBegin->modifiesRegister(Reg, TRI) ||
145 localBegin->readsRegister(Reg, TRI))
153 // These are the common checks that need to performed
155 // 1. compare instruction can be moved before jump.
156 // 2. feeder to the compare instruction can be moved before jump.
157 static bool commonChecksToProhibitNewValueJump(bool afterRA,
158 MachineBasicBlock::iterator MII) {
160 // If store in path, bail out.
161 if (MII->getDesc().mayStore())
164 // if call in path, bail out.
165 if (MII->getOpcode() == Hexagon::CALLv3)
168 // if NVJ is running prior to RA, do the following checks.
170 // The following Target Opcode instructions are spurious
171 // to new value jump. If they are in the path, bail out.
172 // KILL sets kill flag on the opcode. It also sets up a
173 // single register, out of pair.
174 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
175 // %R0<def> = KILL %R0, %D0<imp-use,kill>
176 // %P0<def> = CMPEQri %R0<kill>, 0
177 // PHI can be anything after RA.
178 // COPY can remateriaze things in between feeder, compare and nvj.
179 if (MII->getOpcode() == TargetOpcode::KILL ||
180 MII->getOpcode() == TargetOpcode::PHI ||
181 MII->getOpcode() == TargetOpcode::COPY)
184 // The following pseudo Hexagon instructions sets "use" and "def"
185 // of registers by individual passes in the backend. At this time,
186 // we don't know the scope of usage and definitions of these
188 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
189 MII->getOpcode() == Hexagon::TFR_condset_ii ||
190 MII->getOpcode() == Hexagon::TFR_condset_ri ||
191 MII->getOpcode() == Hexagon::TFR_condset_ir ||
192 MII->getOpcode() == Hexagon::LDriw_pred ||
193 MII->getOpcode() == Hexagon::STriw_pred)
200 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
201 const TargetRegisterInfo *TRI,
202 MachineBasicBlock::iterator II,
206 MachineBasicBlock::iterator end,
207 MachineFunction &MF) {
209 MachineInstr *MI = II;
211 // If the second operand of the compare is an imm, make sure it's in the
212 // range specified by the arch.
214 int64_t v = MI->getOperand(2).getImm();
215 if (MI->getOpcode() == Hexagon::CMPGEri ||
216 (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
219 if (!(isUInt<5>(v) ||
220 ((MI->getOpcode() == Hexagon::CMPEQri ||
221 MI->getOpcode() == Hexagon::CMPGTri ||
222 MI->getOpcode() == Hexagon::CMPGEri) &&
227 unsigned cmpReg1, cmpOp2;
228 cmpReg1 = MI->getOperand(1).getReg();
231 cmpOp2 = MI->getOperand(2).getReg();
233 // Make sure that that second register is not from COPY
234 // At machine code level, we don't need this, but if we decide
235 // to move new value jump prior to RA, we would be needing this.
236 MachineRegisterInfo &MRI = MF.getRegInfo();
237 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
238 MachineInstr *def = MRI.getVRegDef(cmpOp2);
239 if (def->getOpcode() == TargetOpcode::COPY)
244 // Walk the instructions after the compare (predicate def) to the jump,
245 // and satisfy the following conditions.
247 for (MachineBasicBlock::iterator localII = II; localII != end;
251 // If "common" checks fail, bail out.
252 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
256 // If there is a def or use of predicate (result of compare), bail out.
257 if (localII->modifiesRegister(pReg, TRI) ||
258 localII->readsRegister(pReg, TRI))
262 // If there is a def of any of the use of the compare (operands of compare),
265 // p0 = cmp.eq(r2, r0)
267 // if (p0.new) jump:t .LBB28_3
268 if (localII->modifiesRegister(cmpReg1, TRI) ||
269 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
275 // Given a compare operator, return a matching New Value Jump
276 // compare operator. Make sure that MI here is included in
277 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
278 static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
279 bool secondRegNewified) {
280 switch (MI->getOpcode()) {
281 case Hexagon::CMPEQrr:
282 return Hexagon::JMP_EQrrPt_nv_V4;
284 case Hexagon::CMPEQri: {
286 return Hexagon::JMP_EQriPt_nv_V4;
288 return Hexagon::JMP_EQriPtneg_nv_V4;
291 case Hexagon::CMPLTrr:
292 case Hexagon::CMPGTrr: {
293 if (secondRegNewified)
294 return Hexagon::JMP_GTrrdnPt_nv_V4;
296 return Hexagon::JMP_GTrrPt_nv_V4;
299 case Hexagon::CMPGEri: {
301 return Hexagon::JMP_GTriPt_nv_V4;
303 return Hexagon::JMP_GTriPtneg_nv_V4;
306 case Hexagon::CMPGTri: {
308 return Hexagon::JMP_GTriPt_nv_V4;
310 return Hexagon::JMP_GTriPtneg_nv_V4;
313 case Hexagon::CMPLTUrr:
314 case Hexagon::CMPGTUrr: {
315 if (secondRegNewified)
316 return Hexagon::JMP_GTUrrdnPt_nv_V4;
318 return Hexagon::JMP_GTUrrPt_nv_V4;
321 case Hexagon::CMPGTUri:
322 return Hexagon::JMP_GTUriPt_nv_V4;
324 case Hexagon::CMPGEUri: {
326 return Hexagon::JMP_EQrrPt_nv_V4;
328 return Hexagon::JMP_GTUriPt_nv_V4;
332 llvm_unreachable("Could not find matching New Value Jump instruction.");
334 // return *some value* to avoid compiler warning
338 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
340 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
341 << "********** Function: "
342 << MF.getFunction()->getName() << "\n");
345 // for now disable this, if we move NewValueJump before register
346 // allocation we need this information.
347 LiveVariables &LVs = getAnalysis<LiveVariables>();
350 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
352 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
354 if (!QRI->Subtarget.hasV4TOps() ||
355 DisableNewValueJumps) {
359 int nvjCount = DbgNVJCount;
360 int nvjGenerated = 0;
362 // Loop through all the bb's of the function
363 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
364 MBBb != MBBe; ++MBBb) {
365 MachineBasicBlock* MBB = MBBb;
367 DEBUG(dbgs() << "** dumping bb ** "
368 << MBB->getNumber() << "\n");
370 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
371 bool foundJump = false;
372 bool foundCompare = false;
373 bool invertPredicate = false;
374 unsigned predReg = 0; // predicate reg of the jump.
375 unsigned cmpReg1 = 0;
377 bool MO1IsKill = false;
378 bool MO2IsKill = false;
379 MachineBasicBlock::iterator jmpPos;
380 MachineBasicBlock::iterator cmpPos;
381 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
382 MachineBasicBlock *jmpTarget = NULL;
383 bool afterRA = false;
384 bool isSecondOpReg = false;
385 bool isSecondOpNewified = false;
386 // Traverse the basic block - bottom up
387 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
389 MachineInstr *MI = --MII;
390 if (MI->isDebugValue()) {
394 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
397 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
400 (MI->getOpcode() == Hexagon::JMP_c ||
401 MI->getOpcode() == Hexagon::JMP_cNot ||
402 MI->getOpcode() == Hexagon::JMP_cdnPt ||
403 MI->getOpcode() == Hexagon::JMP_cdnPnt ||
404 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
405 MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
406 // This is where you would insert your compare and
407 // instr that feeds compare
410 predReg = MI->getOperand(0).getReg();
411 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
413 // If ifconverter had not messed up with the kill flags of the
414 // operands, the following check on the kill flag would suffice.
415 // if(!jmpInstr->getOperand(0).isKill()) break;
417 // This predicate register is live out out of BB
418 // this would only work if we can actually use Live
419 // variable analysis on phy regs - but LLVM does not
420 // provide LV analysis on phys regs.
421 //if(LVs.isLiveOut(predReg, *MBB)) break;
423 // Get all the successors of this block - which will always
424 // be 2. Check if the predicate register is live in in those
425 // successor. If yes, we can not delete the predicate -
426 // I am doing this only because LLVM does not provide LiveOut
428 bool predLive = false;
429 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
430 SIE = MBB->succ_end(); SI != SIE; ++SI) {
431 MachineBasicBlock* succMBB = *SI;
432 if (succMBB->isLiveIn(predReg)) {
439 jmpTarget = MI->getOperand(1).getMBB();
441 if (MI->getOpcode() == Hexagon::JMP_cNot ||
442 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
443 MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
444 invertPredicate = true;
449 // No new value jump if there is a barrier. A barrier has to be in its
450 // own packet. A barrier has zero operands. We conservatively bail out
451 // here if we see any instruction with zero operands.
452 if (foundJump && MI->getNumOperands() == 0)
457 MI->getOperand(0).isReg() &&
458 MI->getOperand(0).getReg() == predReg) {
460 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
461 if (QII->isNewValueJumpCandidate(MI)) {
463 assert((MI->getDesc().isCompare()) &&
464 "Only compare instruction can be collapsed into New Value Jump");
465 isSecondOpReg = MI->getOperand(2).isReg();
467 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
468 afterRA, jmpPos, MF))
475 // We need cmpReg1 and cmpOp2(imm or reg) while building
476 // new value jump instruction.
477 cmpReg1 = MI->getOperand(1).getReg();
478 if (MI->getOperand(1).isKill())
482 cmpOp2 = MI->getOperand(2).getReg();
483 if (MI->getOperand(2).isKill())
486 cmpOp2 = MI->getOperand(2).getImm();
491 if (foundCompare && foundJump) {
493 // If "common" checks fail, bail out on this BB.
494 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
497 bool foundFeeder = false;
498 MachineBasicBlock::iterator feederPos = MII;
499 if (MI->getOperand(0).isReg() &&
500 MI->getOperand(0).isDef() &&
501 (MI->getOperand(0).getReg() == cmpReg1 ||
503 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
505 unsigned feederReg = MI->getOperand(0).getReg();
507 // First try to see if we can get the feeder from the first operand
508 // of the compare. If we can not, and if secondOpReg is true
509 // (second operand of the compare is also register), try that one.
510 // TODO: Try to come up with some heuristic to figure out which
511 // feeder would benefit.
513 if (feederReg == cmpReg1) {
514 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
525 feederReg == (unsigned) cmpOp2)
526 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
530 // In case of CMPLT, or CMPLTU, or EQ with the second register
531 // to newify, swap the operands.
532 if (cmpInstr->getOpcode() == Hexagon::CMPLTrr ||
533 cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
534 (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
535 feederReg == (unsigned) cmpOp2)) {
536 unsigned tmp = cmpReg1;
537 bool tmpIsKill = MO1IsKill;
539 MO1IsKill = MO2IsKill;
541 MO2IsKill = tmpIsKill;
544 // Now we have swapped the operands, all we need to check is,
545 // if the second operand (after swap) is the feeder.
546 // And if it is, make a note.
547 if (feederReg == (unsigned)cmpOp2)
548 isSecondOpNewified = true;
551 // Now that we are moving feeder close the jump,
552 // make sure we are respecting the kill values of
553 // the operands of the feeder.
555 bool updatedIsKill = false;
556 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
557 MachineOperand &MO = MI->getOperand(i);
558 if (MO.isReg() && MO.isUse()) {
559 unsigned feederReg = MO.getReg();
560 for (MachineBasicBlock::iterator localII = feederPos,
561 end = jmpPos; localII != end; localII++) {
562 MachineInstr *localMI = localII;
563 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
564 MachineOperand &localMO = localMI->getOperand(j);
565 if (localMO.isReg() && localMO.isUse() &&
566 localMO.isKill() && feederReg == localMO.getReg()) {
567 // We found that there is kill of a use register
568 // Set up a kill flag on the register
569 localMO.setIsKill(false);
571 updatedIsKill = true;
575 if (updatedIsKill) break;
578 if (updatedIsKill) break;
581 MBB->splice(jmpPos, MI->getParent(), MI);
582 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
583 DebugLoc dl = MI->getDebugLoc();
586 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
587 "This compare is not a New Value Jump candidate.");
588 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
591 opc = QII->getInvertedPredicatedOpcode(opc);
593 // Manage the conversions from CMPGEUri to either CMPEQrr
594 // or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
595 // This has to be after the getNewValueJumpOpcode function call as
596 // second operand of the compare could be modified in this logic.
597 if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
600 MO2IsKill = MO1IsKill;
601 isSecondOpReg = true;
606 // Manage the conversions from CMPGEri to CMPGTUri properly.
607 // See Arch spec for CMPGEri instructions.
608 if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
612 NewMI = BuildMI(*MBB, jmpPos, dl,
614 .addReg(cmpReg1, getKillRegState(MO1IsKill))
615 .addReg(cmpOp2, getKillRegState(MO2IsKill))
619 NewMI = BuildMI(*MBB, jmpPos, dl,
621 .addReg(cmpReg1, getKillRegState(MO1IsKill))
626 assert(NewMI && "New Value Jump Instruction Not created!");
627 if (cmpInstr->getOperand(0).isReg() &&
628 cmpInstr->getOperand(0).isKill())
629 cmpInstr->getOperand(0).setIsKill(false);
630 if (cmpInstr->getOperand(1).isReg() &&
631 cmpInstr->getOperand(1).isKill())
632 cmpInstr->getOperand(1).setIsKill(false);
633 cmpInstr->eraseFromParent();
634 jmpInstr->eraseFromParent();
647 FunctionPass *llvm::createHexagonNewValueJump() {
648 return new HexagonNewValueJump();