1 //===----- HexagonNewValueJump.cpp - Hexagon Backend New Value Jump -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements NewValueJump pass in Hexagon.
11 // Ideally, we should merge this as a Peephole pass prior to register
12 // allocation, but becuase we have a spill in between the feeder and new value
13 // jump instructions, we are forced to write after register allocation.
14 // Having said that, we should re-attempt to pull this ealier at some piont
17 // The basic approach looks for sequence of predicated jump, compare instruciton
18 // that genereates the predicate and, the feeder to the predicate. Once it finds
19 // all, it collapses compare and jump instruction into a new valu jump
23 //===----------------------------------------------------------------------===//
24 #define DEBUG_TYPE "hexagon-nvj"
25 #include "llvm/PassSupport.h"
26 #include "llvm/Support/Compiler.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/Statistic.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/LiveVariables.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetInstrInfo.h"
39 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "HexagonTargetMachine.h"
42 #include "HexagonRegisterInfo.h"
43 #include "HexagonSubtarget.h"
44 #include "HexagonInstrInfo.h"
45 #include "HexagonMachineFunctionInfo.h"
50 #include "llvm/Support/CommandLine.h"
53 STATISTIC(NumNVJGenerated, "Number of New Value Jump Instructions created");
55 cl::opt<int> DebugHexagonNewValueJump("debug-nvj", cl::Hidden, cl::desc(""));
58 DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, cl::desc(
59 "Maximum number of predicated jumps to be converted to New Value Jump"));
61 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
62 cl::ZeroOrMore, cl::init(false),
63 cl::desc("Disable New Value Jumps"));
66 struct HexagonNewValueJump : public MachineFunctionPass {
67 const HexagonInstrInfo *QII;
68 const HexagonRegisterInfo *QRI;
73 HexagonNewValueJump() : MachineFunctionPass(ID) { }
75 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
76 MachineFunctionPass::getAnalysisUsage(AU);
79 const char *getPassName() const {
80 return "Hexagon NewValueJump";
83 virtual bool runOnMachineFunction(MachineFunction &Fn);
89 } // end of anonymous namespace
91 char HexagonNewValueJump::ID = 0;
93 // We have identified this II could be feeder to NVJ,
94 // verify that it can be.
95 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII,
96 const TargetRegisterInfo *TRI,
97 MachineBasicBlock::iterator II,
98 MachineBasicBlock::iterator end,
99 MachineBasicBlock::iterator skip,
100 MachineFunction &MF) {
102 // Predicated instruction can not be feeder to NVJ.
103 if (QII->isPredicated(II))
106 // Bail out if feederReg is a paired register (double regs in
107 // our case). One would think that we can check to see if a given
108 // register cmpReg1 or cmpReg2 is a sub register of feederReg
109 // using -- if (QRI->isSubRegister(feederReg, cmpReg1) logic
110 // before the callsite of this function
111 // But we can not as it comes in the following fashion.
112 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
113 // %R0<def> = KILL %R0, %D0<imp-use,kill>
114 // %P0<def> = CMPEQri %R0<kill>, 0
115 // Hence, we need to check if it's a KILL instruction.
116 if (II->getOpcode() == TargetOpcode::KILL)
120 // Make sure there there is no 'def' or 'use' of any of the uses of
121 // feeder insn between it's definition, this MI and jump, jmpInst
122 // skipping compare, cmpInst.
123 // Here's the example.
124 // r21=memub(r22+r24<<#0)
125 // p0 = cmp.eq(r21, #0)
126 // r4=memub(r3+r21<<#0)
127 // if (p0.new) jump:t .LBB29_45
128 // Without this check, it will be converted into
129 // r4=memub(r3+r21<<#0)
130 // r21=memub(r22+r24<<#0)
131 // p0 = cmp.eq(r21, #0)
132 // if (p0.new) jump:t .LBB29_45
133 // and result WAR hazards if converted to New Value Jump.
135 for (unsigned i = 0; i < II->getNumOperands(); ++i) {
136 if (II->getOperand(i).isReg() &&
137 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
138 MachineBasicBlock::iterator localII = II;
140 unsigned Reg = II->getOperand(i).getReg();
141 for (MachineBasicBlock::iterator localBegin = localII;
142 localBegin != end; ++localBegin) {
143 if (localBegin == skip ) continue;
144 // Check for Subregisters too.
145 if (localBegin->modifiesRegister(Reg, TRI) ||
146 localBegin->readsRegister(Reg, TRI))
154 // These are the common checks that need to performed
156 // 1. compare instruction can be moved before jump.
157 // 2. feeder to the compare instruction can be moved before jump.
158 static bool commonChecksToProhibitNewValueJump(bool afterRA,
159 MachineBasicBlock::iterator MII) {
161 // If store in path, bail out.
162 if (MII->getDesc().mayStore())
165 // if call in path, bail out.
166 if (MII->getOpcode() == Hexagon::CALLv3)
169 // if NVJ is running prior to RA, do the following checks.
171 // The following Target Opcode instructions are spurious
172 // to new value jump. If they are in the path, bail out.
173 // KILL sets kill flag on the opcode. It also sets up a
174 // single register, out of pair.
175 // %D0<def> = Hexagon_S2_lsr_r_p %D0<kill>, %R2<kill>
176 // %R0<def> = KILL %R0, %D0<imp-use,kill>
177 // %P0<def> = CMPEQri %R0<kill>, 0
178 // PHI can be anything after RA.
179 // COPY can remateriaze things in between feeder, compare and nvj.
180 if (MII->getOpcode() == TargetOpcode::KILL ||
181 MII->getOpcode() == TargetOpcode::PHI ||
182 MII->getOpcode() == TargetOpcode::COPY)
185 // The following pseudo Hexagon instructions sets "use" and "def"
186 // of registers by individual passes in the backend. At this time,
187 // we don't know the scope of usage and definitions of these
189 if (MII->getOpcode() == Hexagon::TFR_condset_rr ||
190 MII->getOpcode() == Hexagon::TFR_condset_ii ||
191 MII->getOpcode() == Hexagon::TFR_condset_ri ||
192 MII->getOpcode() == Hexagon::TFR_condset_ir ||
193 MII->getOpcode() == Hexagon::LDriw_pred ||
194 MII->getOpcode() == Hexagon::STriw_pred)
201 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
202 const TargetRegisterInfo *TRI,
203 MachineBasicBlock::iterator II,
207 MachineBasicBlock::iterator end,
208 MachineFunction &MF) {
210 MachineInstr *MI = II;
212 // If the second operand of the compare is an imm, make sure it's in the
213 // range specified by the arch.
215 int64_t v = MI->getOperand(2).getImm();
216 if (MI->getOpcode() == Hexagon::CMPGEri ||
217 (MI->getOpcode() == Hexagon::CMPGEUri && v > 0))
220 if (!(isUInt<5>(v) ||
221 ((MI->getOpcode() == Hexagon::CMPEQri ||
222 MI->getOpcode() == Hexagon::CMPGTri ||
223 MI->getOpcode() == Hexagon::CMPGEri) &&
228 unsigned cmpReg1, cmpOp2;
229 cmpReg1 = MI->getOperand(1).getReg();
232 cmpOp2 = MI->getOperand(2).getReg();
234 // Make sure that that second register is not from COPY
235 // At machine code level, we don't need this, but if we decide
236 // to move new value jump prior to RA, we would be needing this.
237 MachineRegisterInfo &MRI = MF.getRegInfo();
238 if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
239 MachineInstr *def = MRI.getVRegDef(cmpOp2);
240 if (def->getOpcode() == TargetOpcode::COPY)
245 // Walk the instructions after the compare (predicate def) to the jump,
246 // and satisfy the following conditions.
248 for (MachineBasicBlock::iterator localII = II; localII != end;
252 // If "common" checks fail, bail out.
253 if (!commonChecksToProhibitNewValueJump(optLocation, localII))
257 // If there is a def or use of predicate (result of compare), bail out.
258 if (localII->modifiesRegister(pReg, TRI) ||
259 localII->readsRegister(pReg, TRI))
263 // If there is a def of any of the use of the compare (operands of compare),
266 // p0 = cmp.eq(r2, r0)
268 // if (p0.new) jump:t .LBB28_3
269 if (localII->modifiesRegister(cmpReg1, TRI) ||
270 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
276 // Given a compare operator, return a matching New Value Jump
277 // compare operator. Make sure that MI here is included in
278 // HexagonInstrInfo.cpp::isNewValueJumpCandidate
279 static unsigned getNewValueJumpOpcode(const MachineInstr *MI, int reg,
280 bool secondRegNewified) {
281 switch (MI->getOpcode()) {
282 case Hexagon::CMPEQrr:
283 return Hexagon::JMP_EQrrPt_nv_V4;
285 case Hexagon::CMPEQri: {
287 return Hexagon::JMP_EQriPt_nv_V4;
289 return Hexagon::JMP_EQriPtneg_nv_V4;
292 case Hexagon::CMPLTrr:
293 case Hexagon::CMPGTrr: {
294 if (secondRegNewified)
295 return Hexagon::JMP_GTrrdnPt_nv_V4;
297 return Hexagon::JMP_GTrrPt_nv_V4;
300 case Hexagon::CMPGEri: {
302 return Hexagon::JMP_GTriPt_nv_V4;
304 return Hexagon::JMP_GTriPtneg_nv_V4;
307 case Hexagon::CMPGTri: {
309 return Hexagon::JMP_GTriPt_nv_V4;
311 return Hexagon::JMP_GTriPtneg_nv_V4;
314 case Hexagon::CMPLTUrr:
315 case Hexagon::CMPGTUrr: {
316 if (secondRegNewified)
317 return Hexagon::JMP_GTUrrdnPt_nv_V4;
319 return Hexagon::JMP_GTUrrPt_nv_V4;
322 case Hexagon::CMPGTUri:
323 return Hexagon::JMP_GTUriPt_nv_V4;
325 case Hexagon::CMPGEUri: {
327 return Hexagon::JMP_EQrrPt_nv_V4;
329 return Hexagon::JMP_GTUriPt_nv_V4;
333 llvm_unreachable("Could not find matching New Value Jump instruction.");
335 // return *some value* to avoid compiler warning
339 bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
341 DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n"
342 << "********** Function: "
343 << MF.getFunction()->getName() << "\n");
346 // for now disable this, if we move NewValueJump before register
347 // allocation we need this information.
348 LiveVariables &LVs = getAnalysis<LiveVariables>();
351 QII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
353 static_cast<const HexagonRegisterInfo *>(MF.getTarget().getRegisterInfo());
355 if (!QRI->Subtarget.hasV4TOps() ||
356 DisableNewValueJumps) {
360 int nvjCount = DbgNVJCount;
361 int nvjGenerated = 0;
363 // Loop through all the bb's of the function
364 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
365 MBBb != MBBe; ++MBBb) {
366 MachineBasicBlock* MBB = MBBb;
368 DEBUG(dbgs() << "** dumping bb ** "
369 << MBB->getNumber() << "\n");
371 DEBUG(dbgs() << "\n" << "********** dumping instr bottom up **********\n");
372 bool foundJump = false;
373 bool foundCompare = false;
374 bool invertPredicate = false;
375 unsigned predReg = 0; // predicate reg of the jump.
376 unsigned cmpReg1 = 0;
378 bool MO1IsKill = false;
379 bool MO2IsKill = false;
380 MachineBasicBlock::iterator jmpPos;
381 MachineBasicBlock::iterator cmpPos;
382 MachineInstr *cmpInstr = NULL, *jmpInstr = NULL;
383 MachineBasicBlock *jmpTarget = NULL;
384 bool afterRA = false;
385 bool isSecondOpReg = false;
386 bool isSecondOpNewified = false;
387 // Traverse the basic block - bottom up
388 for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
390 MachineInstr *MI = --MII;
391 if (MI->isDebugValue()) {
395 if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
398 DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
401 (MI->getOpcode() == Hexagon::JMP_c ||
402 MI->getOpcode() == Hexagon::JMP_cNot ||
403 MI->getOpcode() == Hexagon::JMP_cdnPt ||
404 MI->getOpcode() == Hexagon::JMP_cdnPnt ||
405 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
406 MI->getOpcode() == Hexagon::JMP_cdnNotPnt)) {
407 // This is where you would insert your compare and
408 // instr that feeds compare
411 predReg = MI->getOperand(0).getReg();
412 afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
414 // If ifconverter had not messed up with the kill flags of the
415 // operands, the following check on the kill flag would suffice.
416 // if(!jmpInstr->getOperand(0).isKill()) break;
418 // This predicate register is live out out of BB
419 // this would only work if we can actually use Live
420 // variable analysis on phy regs - but LLVM does not
421 // provide LV analysis on phys regs.
422 //if(LVs.isLiveOut(predReg, *MBB)) break;
424 // Get all the successors of this block - which will always
425 // be 2. Check if the predicate register is live in in those
426 // successor. If yes, we can not delete the predicate -
427 // I am doing this only because LLVM does not provide LiveOut
429 bool predLive = false;
430 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
431 SIE = MBB->succ_end(); SI != SIE; ++SI) {
432 MachineBasicBlock* succMBB = *SI;
433 if (succMBB->isLiveIn(predReg)) {
440 jmpTarget = MI->getOperand(1).getMBB();
442 if (MI->getOpcode() == Hexagon::JMP_cNot ||
443 MI->getOpcode() == Hexagon::JMP_cdnNotPt ||
444 MI->getOpcode() == Hexagon::JMP_cdnNotPnt) {
445 invertPredicate = true;
450 // No new value jump if there is a barrier. A barrier has to be in its
451 // own packet. A barrier has zero operands. We conservatively bail out
452 // here if we see any instruction with zero operands.
453 if (foundJump && MI->getNumOperands() == 0)
458 MI->getOperand(0).isReg() &&
459 MI->getOperand(0).getReg() == predReg) {
461 // Not all compares can be new value compare. Arch Spec: 7.6.1.1
462 if (QII->isNewValueJumpCandidate(MI)) {
464 assert((MI->getDesc().isCompare()) &&
465 "Only compare instruction can be collapsed into New Value Jump");
466 isSecondOpReg = MI->getOperand(2).isReg();
468 if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
469 afterRA, jmpPos, MF))
476 // We need cmpReg1 and cmpOp2(imm or reg) while building
477 // new value jump instruction.
478 cmpReg1 = MI->getOperand(1).getReg();
479 if (MI->getOperand(1).isKill())
483 cmpOp2 = MI->getOperand(2).getReg();
484 if (MI->getOperand(2).isKill())
487 cmpOp2 = MI->getOperand(2).getImm();
492 if (foundCompare && foundJump) {
494 // If "common" checks fail, bail out on this BB.
495 if (!commonChecksToProhibitNewValueJump(afterRA, MII))
498 bool foundFeeder = false;
499 MachineBasicBlock::iterator feederPos = MII;
500 if (MI->getOperand(0).isReg() &&
501 MI->getOperand(0).isDef() &&
502 (MI->getOperand(0).getReg() == cmpReg1 ||
504 MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
506 unsigned feederReg = MI->getOperand(0).getReg();
508 // First try to see if we can get the feeder from the first operand
509 // of the compare. If we can not, and if secondOpReg is true
510 // (second operand of the compare is also register), try that one.
511 // TODO: Try to come up with some heuristic to figure out which
512 // feeder would benefit.
514 if (feederReg == cmpReg1) {
515 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF)) {
526 feederReg == (unsigned) cmpOp2)
527 if (!canBeFeederToNewValueJump(QII, QRI, MII, jmpPos, cmpPos, MF))
531 // In case of CMPLT, or CMPLTU, or EQ with the second register
532 // to newify, swap the operands.
533 if (cmpInstr->getOpcode() == Hexagon::CMPLTrr ||
534 cmpInstr->getOpcode() == Hexagon::CMPLTUrr ||
535 (cmpInstr->getOpcode() == Hexagon::CMPEQrr &&
536 feederReg == (unsigned) cmpOp2)) {
537 unsigned tmp = cmpReg1;
538 bool tmpIsKill = MO1IsKill;
540 MO1IsKill = MO2IsKill;
542 MO2IsKill = tmpIsKill;
545 // Now we have swapped the operands, all we need to check is,
546 // if the second operand (after swap) is the feeder.
547 // And if it is, make a note.
548 if (feederReg == (unsigned)cmpOp2)
549 isSecondOpNewified = true;
552 // Now that we are moving feeder close the jump,
553 // make sure we are respecting the kill values of
554 // the operands of the feeder.
556 bool updatedIsKill = false;
557 for (unsigned i = 0; i < MI->getNumOperands(); i++) {
558 MachineOperand &MO = MI->getOperand(i);
559 if (MO.isReg() && MO.isUse()) {
560 unsigned feederReg = MO.getReg();
561 for (MachineBasicBlock::iterator localII = feederPos,
562 end = jmpPos; localII != end; localII++) {
563 MachineInstr *localMI = localII;
564 for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
565 MachineOperand &localMO = localMI->getOperand(j);
566 if (localMO.isReg() && localMO.isUse() &&
567 localMO.isKill() && feederReg == localMO.getReg()) {
568 // We found that there is kill of a use register
569 // Set up a kill flag on the register
570 localMO.setIsKill(false);
572 updatedIsKill = true;
576 if (updatedIsKill) break;
579 if (updatedIsKill) break;
582 MBB->splice(jmpPos, MI->getParent(), MI);
583 MBB->splice(jmpPos, MI->getParent(), cmpInstr);
584 DebugLoc dl = MI->getDebugLoc();
587 assert((QII->isNewValueJumpCandidate(cmpInstr)) &&
588 "This compare is not a New Value Jump candidate.");
589 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
592 opc = QII->getInvertedPredicatedOpcode(opc);
594 // Manage the conversions from CMPGEUri to either CMPEQrr
595 // or CMPGTUri properly. See Arch spec for CMPGEUri instructions.
596 // This has to be after the getNewValueJumpOpcode function call as
597 // second operand of the compare could be modified in this logic.
598 if (cmpInstr->getOpcode() == Hexagon::CMPGEUri) {
601 MO2IsKill = MO1IsKill;
602 isSecondOpReg = true;
607 // Manage the conversions from CMPGEri to CMPGTUri properly.
608 // See Arch spec for CMPGEri instructions.
609 if (cmpInstr->getOpcode() == Hexagon::CMPGEri)
613 NewMI = BuildMI(*MBB, jmpPos, dl,
615 .addReg(cmpReg1, getKillRegState(MO1IsKill))
616 .addReg(cmpOp2, getKillRegState(MO2IsKill))
620 NewMI = BuildMI(*MBB, jmpPos, dl,
622 .addReg(cmpReg1, getKillRegState(MO1IsKill))
627 assert(NewMI && "New Value Jump Instruction Not created!");
628 if (cmpInstr->getOperand(0).isReg() &&
629 cmpInstr->getOperand(0).isKill())
630 cmpInstr->getOperand(0).setIsKill(false);
631 if (cmpInstr->getOperand(1).isReg() &&
632 cmpInstr->getOperand(1).isKill())
633 cmpInstr->getOperand(1).setIsKill(false);
634 cmpInstr->eraseFromParent();
635 jmpInstr->eraseFromParent();
648 FunctionPass *llvm::createHexagonNewValueJump() {
649 return new HexagonNewValueJump();