lib/Target/Hexagon/HexagonIntrinsicsV5.td

   1 //===- HexagonIntrinsicsV5.td - V5 Instruction intrinsics --*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 //Rdd[+]=vrmpybsu(Rss,Rtt)
  11 //Rdd[+]=vrmpybuu(Rss,Rtt)
  12 let Predicates = [HasV5T]  in {
  13 def : T_PP_pat  <M5_vrmpybsu, int_hexagon_M5_vrmpybsu>;
  14 def : T_PP_pat  <M5_vrmpybuu, int_hexagon_M5_vrmpybuu>;
  15
  16 def : T_PP_pat <M5_vdmpybsu, int_hexagon_M5_vdmpybsu>;
  17
  18 def : T_PPP_pat <M5_vrmacbsu, int_hexagon_M5_vrmacbsu>;
  19 def : T_PPP_pat <M5_vrmacbuu, int_hexagon_M5_vrmacbuu>;
  20 //Rxx+=vdmpybsu(Rss,Rtt):sat
  21 def : T_PPP_pat <M5_vdmacbsu, int_hexagon_M5_vdmacbsu>;
  22
  23 // Vector multiply bytes
  24 // Rdd=vmpyb[s]u(Rs,Rt)
  25 def : T_RR_pat <M5_vmpybsu, int_hexagon_M5_vmpybsu>;
  26 def : T_RR_pat <M5_vmpybuu, int_hexagon_M5_vmpybuu>;
  27
  28 // Rxx+=vmpyb[s]u(Rs,Rt)
  29 def : T_PRR_pat <M5_vmacbsu, int_hexagon_M5_vmacbsu>;
  30 def : T_PRR_pat <M5_vmacbuu, int_hexagon_M5_vmacbuu>;
  31
  32 // Rd=vaddhub(Rss,Rtt):sat
  33 def : T_PP_pat <A5_vaddhubs, int_hexagon_A5_vaddhubs>;
  34 }
  35
  36 def : T_FF_pat<F2_sfadd, int_hexagon_F2_sfadd>;
  37 def : T_FF_pat<F2_sfsub, int_hexagon_F2_sfsub>;
  38 def : T_FF_pat<F2_sfmpy, int_hexagon_F2_sfmpy>;
  39 def : T_FF_pat<F2_sfmax, int_hexagon_F2_sfmax>;
  40 def : T_FF_pat<F2_sfmin, int_hexagon_F2_sfmin>;
  41
  42 def : T_FF_pat<F2_sffixupn, int_hexagon_F2_sffixupn>;
  43 def : T_FF_pat<F2_sffixupd, int_hexagon_F2_sffixupd>;
  44 def : T_F_pat <F2_sffixupr, int_hexagon_F2_sffixupr>;
  45
  46 def: qi_CRInst_qiqi_pat<C4_fastcorner9,     int_hexagon_C4_fastcorner9>;
  47 def: qi_CRInst_qiqi_pat<C4_fastcorner9_not, int_hexagon_C4_fastcorner9_not>;
  48
  49 def : T_P_pat <S5_popcountp, int_hexagon_S5_popcountp>;
  50 def : T_PI_pat <S5_asrhub_sat, int_hexagon_S5_asrhub_sat>;
  51
  52 def : T_PI_pat <S2_asr_i_p_rnd, int_hexagon_S2_asr_i_p_rnd>;
  53 def : T_PI_pat <S2_asr_i_p_rnd_goodsyntax,
  54                 int_hexagon_S2_asr_i_p_rnd_goodsyntax>;
  55
  56 def : T_PI_pat <S5_asrhub_rnd_sat_goodsyntax,
  57                 int_hexagon_S5_asrhub_rnd_sat_goodsyntax>;
  58
  59 def : T_PI_pat <S5_vasrhrnd_goodsyntax, int_hexagon_S5_vasrhrnd_goodsyntax>;
  60
  61 def : T_FFF_pat <F2_sffma, int_hexagon_F2_sffma>;
  62 def : T_FFF_pat <F2_sffms, int_hexagon_F2_sffms>;
  63 def : T_FFF_pat <F2_sffma_lib, int_hexagon_F2_sffma_lib>;
  64 def : T_FFF_pat <F2_sffms_lib, int_hexagon_F2_sffms_lib>;
  65 def : T_FFFQ_pat <F2_sffma_sc, int_hexagon_F2_sffma_sc>;
  66
  67 // Compare floating-point value
  68 def : T_FF_pat <F2_sfcmpge, int_hexagon_F2_sfcmpge>;
  69 def : T_FF_pat <F2_sfcmpuo, int_hexagon_F2_sfcmpuo>;
  70 def : T_FF_pat <F2_sfcmpeq, int_hexagon_F2_sfcmpeq>;
  71 def : T_FF_pat <F2_sfcmpgt, int_hexagon_F2_sfcmpgt>;
  72
  73 def : T_DD_pat <F2_dfcmpeq, int_hexagon_F2_dfcmpeq>;
  74 def : T_DD_pat <F2_dfcmpgt, int_hexagon_F2_dfcmpgt>;
  75 def : T_DD_pat <F2_dfcmpge, int_hexagon_F2_dfcmpge>;
  76 def : T_DD_pat <F2_dfcmpuo, int_hexagon_F2_dfcmpuo>;
  77
  78 // Create floating-point value
  79 def : T_I_pat <F2_sfimm_p, int_hexagon_F2_sfimm_p>;
  80 def : T_I_pat <F2_sfimm_n, int_hexagon_F2_sfimm_n>;
  81 def : T_I_pat <F2_dfimm_p, int_hexagon_F2_dfimm_p>;
  82 def : T_I_pat <F2_dfimm_n, int_hexagon_F2_dfimm_n>;
  83
  84 def : T_DI_pat <F2_dfclass, int_hexagon_F2_dfclass>;
  85 def : T_FI_pat <F2_sfclass, int_hexagon_F2_sfclass>;
  86 def : T_F_pat <F2_conv_sf2df, int_hexagon_F2_conv_sf2df>;
  87 def : T_D_pat <F2_conv_df2sf, int_hexagon_F2_conv_df2sf>;
  88 def : T_R_pat <F2_conv_uw2sf, int_hexagon_F2_conv_uw2sf>;
  89 def : T_R_pat <F2_conv_uw2df, int_hexagon_F2_conv_uw2df>;
  90 def : T_R_pat <F2_conv_w2sf,  int_hexagon_F2_conv_w2sf>;
  91 def : T_R_pat <F2_conv_w2df,  int_hexagon_F2_conv_w2df>;
  92 def : T_P_pat <F2_conv_ud2sf, int_hexagon_F2_conv_ud2sf>;
  93 def : T_P_pat <F2_conv_ud2df, int_hexagon_F2_conv_ud2df>;
  94 def : T_P_pat <F2_conv_d2sf,  int_hexagon_F2_conv_d2sf>;
  95 def : T_P_pat <F2_conv_d2df,  int_hexagon_F2_conv_d2df>;
  96 def : T_F_pat <F2_conv_sf2uw, int_hexagon_F2_conv_sf2uw>;
  97 def : T_F_pat <F2_conv_sf2w,  int_hexagon_F2_conv_sf2w>;
  98 def : T_F_pat <F2_conv_sf2ud, int_hexagon_F2_conv_sf2ud>;
  99 def : T_F_pat <F2_conv_sf2d,  int_hexagon_F2_conv_sf2d>;
 100 def : T_D_pat <F2_conv_df2uw, int_hexagon_F2_conv_df2uw>;
 101 def : T_D_pat <F2_conv_df2w,  int_hexagon_F2_conv_df2w>;
 102 def : T_D_pat <F2_conv_df2ud, int_hexagon_F2_conv_df2ud>;
 103 def : T_D_pat <F2_conv_df2d,  int_hexagon_F2_conv_df2d>;
 104 def : T_F_pat <F2_conv_sf2uw_chop, int_hexagon_F2_conv_sf2uw_chop>;
 105 def : T_F_pat <F2_conv_sf2w_chop,  int_hexagon_F2_conv_sf2w_chop>;
 106 def : T_F_pat <F2_conv_sf2ud_chop, int_hexagon_F2_conv_sf2ud_chop>;
 107 def : T_F_pat <F2_conv_sf2d_chop,  int_hexagon_F2_conv_sf2d_chop>;
 108 def : T_D_pat <F2_conv_df2uw_chop, int_hexagon_F2_conv_df2uw_chop>;
 109 def : T_D_pat <F2_conv_df2w_chop,  int_hexagon_F2_conv_df2w_chop>;
 110 def : T_D_pat <F2_conv_df2ud_chop, int_hexagon_F2_conv_df2ud_chop>;
 111 def : T_D_pat <F2_conv_df2d_chop,  int_hexagon_F2_conv_df2d_chop>;