Taints the non-acquire RMW's store address with the load part
[oota-llvm.git] / lib / Target / Hexagon / HexagonIntrinsicsDerived.td
1 //===-- HexagonIntrinsicsDerived.td - Derived intrinsics ---*- tablegen -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Multiply 64-bit and use lower result
11 //
12 // Optimized with intrinisics accumulates
13 //
14 def : Pat <(mul DoubleRegs:$src1, DoubleRegs:$src2),
15       (i64
16        (A2_combinew
17         (M2_maci
18          (M2_maci
19           (i32
20            (EXTRACT_SUBREG
21             (i64
22              (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
23                                           subreg_loreg)),
24                      (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
25                                           subreg_loreg)))),
26             subreg_hireg)),
27           (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28           (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29          (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30          (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
31         (i32
32          (EXTRACT_SUBREG
33           (i64
34            (M2_dpmpyuu_s0 
35              (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
36                    (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
37                                         subreg_loreg)))), subreg_loreg))))>;
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