lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  25   : Pat<(IntID Imm1:$Is, Imm2:$It),
  26         (MI Imm1:$Is, Imm2:$It)>;
  27
  28 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  29   : Pat<(IntID I32:$Rs, ImmPred:$It),
  30         (MI I32:$Rs, ImmPred:$It)>;
  31
  32 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  34         (MI ImmPred:$Is, I32:$Rt)>;
  35
  36 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  37   : Pat <(IntID I32:$Rs, I32:$Rt),
  38          (MI I32:$Rs, I32:$Rt)>;
  39
  40 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  41   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  42          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  43
  44 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  45   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  46          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  47
  48 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  49   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  50          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  51
  52 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  53   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  54          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  55
  56 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
  57   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
  58          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // MPYS / Multipy signed/unsigned halfwords
  62 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
  63 //===----------------------------------------------------------------------===//
  64
  65 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
  66 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
  67 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
  68 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
  69 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
  70 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
  71 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
  72 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
  73
  74 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
  75 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
  76 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
  77 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
  78 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
  79 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
  80 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
  81 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
  82
  83 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
  84 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
  85 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
  86 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
  87 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
  88 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
  89 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
  90 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
  91
  92 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
  93 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
  94 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
  95 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
  96 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
  97 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
  98 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
  99 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 100
 101 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 102 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 103 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 104 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 105 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 106 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 107 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 108 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 109
 110
 111 //===----------------------------------------------------------------------===//
 112 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 113 // result from the accumulator.
 114 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 115 //===----------------------------------------------------------------------===//
 116
 117 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 118 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 119 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 120 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 121 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 122 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 123 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 124 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 125
 126 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 127 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 128 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 129 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 130 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 131 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 132 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 133 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 134
 135 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 136 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 137 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 138 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 139 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 140 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 141 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 142 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 143
 144 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 145 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 146 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 147 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 148 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 149 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 150 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 151 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 152
 153 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 154 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 155 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 156 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 157 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 158 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 159 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 160 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 161
 162 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 163 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 164 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 165 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 166 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 167 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 168 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 169 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 170
 171
 172 //===----------------------------------------------------------------------===//
 173 // Multiply signed/unsigned halfwords with and without saturation and rounding
 174 // into a 64-bits destination register.
 175 //===----------------------------------------------------------------------===//
 176
 177 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 178 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 179 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 180 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 181 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 182 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 183 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 184 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 185
 186 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 187 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 188 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 189 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 190 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 191 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 192 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 193 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 194
 195 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 196 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 197 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 198 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 199 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 200 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 201 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 202 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 203
 204 //===----------------------------------------------------------------------===//
 205 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 206 // result from the 64-bit destination register.
 207 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 208 //===----------------------------------------------------------------------===//
 209
 210 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 211 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 212 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 213 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 214
 215 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 216 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 217 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 218 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 219
 220 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 221 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 222 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 223 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 224
 225 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 226 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 227 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 228 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 229
 230 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 231 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 232 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 233 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 234
 235 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 236 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 237 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 238 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 239
 240 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 241 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 242 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 243 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 244
 245 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 246 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 247 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 248 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 249
 250 /********************************************************************
 251 *            ALU32/ALU                                              *
 252 *********************************************************************/
 253 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 254 def : T_RI_pat<ADD_ri,      int_hexagon_A2_addi>;
 255 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 256 def : T_IR_pat<SUB_ri,      int_hexagon_A2_subri>;
 257 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 258 def : T_RI_pat<AND_ri,      int_hexagon_A2_andir>;
 259 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 260 def : T_RI_pat<OR_ri,       int_hexagon_A2_orir>;
 261 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 262 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 263
 264 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 265 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 266            (SUB_ri -1, IntRegs:$Rs)>;
 267
 268 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 269 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 270            (SUB_ri 0, IntRegs:$Rs)>;
 271
 272 // Transfer immediate
 273 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 274             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 275 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 276             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 277
 278 //  Transfer Register/immediate.
 279 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 280 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 281
 282 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 283 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 284           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 285
 286 /********************************************************************
 287 *            ALU32/PERM                                             *
 288 *********************************************************************/
 289 // Combine
 290 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 291 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 292 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 293 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 294
 295 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 296
 297 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs),
 298                                                      (I32:$Rt))),
 299          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 300
 301 // Mux
 302 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 303 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 304 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 305
 306 // Shift halfword
 307 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 308 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 309 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 310
 311 // Sign/zero extend
 312 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 313 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 314 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 315 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 316
 317 //
 318 // ALU 32 types.
 319 //
 320
 321 class qi_ALU32_sisi<string opc, Intrinsic IntID>
 322   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 323              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 324              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 325
 326 class qi_ALU32_sis10<string opc, Intrinsic IntID>
 327   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 328              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 329              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 330
 331 class qi_ALU32_sis8<string opc, Intrinsic IntID>
 332   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
 333              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 334              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 335
 336 class qi_ALU32_siu8<string opc, Intrinsic IntID>
 337   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u8Imm:$src2),
 338              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 339              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 340
 341 class qi_ALU32_siu9<string opc, Intrinsic IntID>
 342   : ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
 343              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 344              [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 345
 346 class si_ALU32_qisisi<string opc, Intrinsic IntID>
 347   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 348                                       IntRegs:$src3),
 349              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 350              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 351                                         IntRegs:$src3))]>;
 352
 353 class si_ALU32_qis8si<string opc, Intrinsic IntID>
 354   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2,
 355                                        IntRegs:$src3),
 356              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, $src3)")),
 357              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
 358                                         IntRegs:$src3))]>;
 359
 360 class si_ALU32_qisis8<string opc, Intrinsic IntID>
 361   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
 362                                        s8Imm:$src3),
 363              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 364              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 365                                         imm:$src3))]>;
 366
 367 class si_ALU32_qis8s8<string opc, Intrinsic IntID>
 368   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2, s8Imm:$src3),
 369              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 370              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 371
 372 class si_ALU32_sisi<string opc, Intrinsic IntID>
 373   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 374              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 375              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 376
 377 class si_ALU32_sisi_sat<string opc, Intrinsic IntID>
 378   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 379              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 380              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 381
 382 class si_ALU32_sisi_rnd<string opc, Intrinsic IntID>
 383   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 384              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 385              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 386
 387 class si_ALU32_sis16<string opc, Intrinsic IntID>
 388   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s16Imm:$src2),
 389              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 390              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 391
 392 class si_ALU32_sis10<string opc, Intrinsic IntID>
 393   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
 394              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 395              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 396
 397 class si_ALU32_s10si<string opc, Intrinsic IntID>
 398   : ALU32_rr<(outs IntRegs:$dst), (ins s10Imm:$src1, IntRegs:$src2),
 399              !strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
 400              [(set IntRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
 401
 402 class si_lo_ALU32_siu16<string opc, Intrinsic IntID>
 403   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 404              !strconcat("$dst.l = ", !strconcat(opc , "#$src2")),
 405              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 406
 407 class si_hi_ALU32_siu16<string opc, Intrinsic IntID>
 408   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u16Imm:$src2),
 409              !strconcat("$dst.h = ", !strconcat(opc , "#$src2")),
 410              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 411
 412 class si_ALU32_s16<string opc, Intrinsic IntID>
 413   : ALU32_rr<(outs IntRegs:$dst), (ins s16Imm:$src1),
 414              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 415              [(set IntRegs:$dst, (IntID imm:$src1))]>;
 416
 417 class di_ALU32_s8<string opc, Intrinsic IntID>
 418   : ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1),
 419              !strconcat("$dst = ", !strconcat(opc , "#$src1")),
 420              [(set DoubleRegs:$dst, (IntID imm:$src1))]>;
 421
 422 class di_ALU64_di<string opc, Intrinsic IntID>
 423   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 424              !strconcat("$dst = ", !strconcat(opc , "$src")),
 425              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 426
 427 class si_ALU32_si<string opc, Intrinsic IntID>
 428   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 429              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 430              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 431
 432 class si_ALU32_si_tfr<string opc, Intrinsic IntID>
 433   : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 434              !strconcat("$dst = ", !strconcat(opc , "$src")),
 435              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 436
 437 //
 438 // ALU 64 types.
 439 //
 440
 441 class si_ALU64_si_sat<string opc, Intrinsic IntID>
 442   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src),
 443              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 444              [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 445
 446 class si_ALU64_didi<string opc, Intrinsic IntID>
 447   : ALU64_rr<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 448              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 449              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 450
 451 class di_ALU64_sidi<string opc, Intrinsic IntID>
 452   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 453              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 454              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 455
 456 class di_ALU64_didi<string opc, Intrinsic IntID>
 457   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 458              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 459              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 460                                            DoubleRegs:$src2))]>;
 461
 462 class di_ALU64_qididi<string opc, Intrinsic IntID>
 463   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2,
 464                                           DoubleRegs:$src3),
 465              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 466              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2,
 467                                            DoubleRegs:$src3))]>;
 468
 469 class di_ALU64_sisi<string opc, Intrinsic IntID>
 470   : ALU64_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 471              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 472              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 473
 474 class di_ALU64_didi_sat<string opc, Intrinsic IntID>
 475   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 476              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 477              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 478                                            DoubleRegs:$src2))]>;
 479
 480 class di_ALU64_didi_rnd<string opc, Intrinsic IntID>
 481   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 482              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
 483              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 484                                            DoubleRegs:$src2))]>;
 485
 486 class di_ALU64_didi_crnd<string opc, Intrinsic IntID>
 487   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 488              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd")),
 489              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 490                                            DoubleRegs:$src2))]>;
 491
 492 class di_ALU64_didi_rnd_sat<string opc, Intrinsic IntID>
 493   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 494              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
 495              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 496                                            DoubleRegs:$src2))]>;
 497
 498 class di_ALU64_didi_crnd_sat<string opc, Intrinsic IntID>
 499   : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 500              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):crnd:sat")),
 501              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
 502                                            DoubleRegs:$src2))]>;
 503
 504 class qi_ALU64_didi<string opc, Intrinsic IntID>
 505   : ALU64_rr<(outs PredRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 506              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 507              [(set PredRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 508
 509 class si_ALU64_sisi<string opc, Intrinsic IntID>
 510   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 511              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 512              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 513
 514 class si_ALU64_sisi_sat_lh<string opc, Intrinsic IntID>
 515   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 516              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 517              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 518
 519 class si_ALU64_sisi_l16_sat_hh<string opc, Intrinsic IntID>
 520   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 521              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
 522              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 523
 524 class si_ALU64_sisi_l16_sat_lh<string opc, Intrinsic IntID>
 525   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 526              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
 527              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 528
 529 class si_ALU64_sisi_l16_sat_hl<string opc, Intrinsic IntID>
 530   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 531              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
 532              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 533
 534 class si_ALU64_sisi_l16_sat_ll<string opc, Intrinsic IntID>
 535   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 536              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
 537              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 538
 539 class si_ALU64_sisi_l16_hh<string opc, Intrinsic IntID>
 540   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 541              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
 542              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 543
 544 class si_ALU64_sisi_l16_hl<string opc, Intrinsic IntID>
 545   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 546              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
 547              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 548
 549 class si_ALU64_sisi_l16_lh<string opc, Intrinsic IntID>
 550   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 551              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 552              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 553
 554 class si_ALU64_sisi_l16_ll<string opc, Intrinsic IntID>
 555   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 556              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 557              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 558
 559 class si_ALU64_sisi_h16_sat_hh<string opc, Intrinsic IntID>
 560   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 561              !strconcat("$dst = ", !strconcat(opc ,
 562                                               "($src1.H, $src2.H):sat:<<16")),
 563              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 564
 565 class si_ALU64_sisi_h16_sat_lh<string opc, Intrinsic IntID>
 566   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 567              !strconcat("$dst = ", !strconcat(opc ,
 568                                               "($src1.L, $src2.H):sat:<<16")),
 569              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 570
 571 class si_ALU64_sisi_h16_sat_hl<string opc, Intrinsic IntID>
 572   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 573              !strconcat("$dst = ", !strconcat(opc ,
 574                                               "($src1.H, $src2.L):sat:<<16")),
 575              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 576
 577 class si_ALU64_sisi_h16_sat_ll<string opc, Intrinsic IntID>
 578   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 579              !strconcat("$dst = ", !strconcat(opc ,
 580                                               "($src1.L, $src2.L):sat:<<16")),
 581              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 582
 583 class si_ALU64_sisi_h16_hh<string opc, Intrinsic IntID>
 584   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 585              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<16")),
 586              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 587
 588 class si_ALU64_sisi_h16_hl<string opc, Intrinsic IntID>
 589   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 590              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<16")),
 591              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 592
 593 class si_ALU64_sisi_h16_lh<string opc, Intrinsic IntID>
 594   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 595              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<16")),
 596              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 597
 598 class si_ALU64_sisi_h16_ll<string opc, Intrinsic IntID>
 599   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 600              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<16")),
 601              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 602
 603 class si_ALU64_sisi_lh<string opc, Intrinsic IntID>
 604   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 605              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
 606              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 607
 608 class si_ALU64_sisi_ll<string opc, Intrinsic IntID>
 609   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 610              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
 611              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 612
 613 class si_ALU64_sisi_sat<string opc, Intrinsic IntID>
 614   : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 615              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
 616              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 617
 618 //
 619 // SInst classes.
 620 //
 621
 622 class qi_SInst_qi<string opc, Intrinsic IntID>
 623   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 624              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 625              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 626
 627 class qi_SInst_qi_pxfer<string opc, Intrinsic IntID>
 628   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 629              !strconcat("$dst = ", !strconcat(opc , "$src")),
 630              [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 631
 632 class qi_SInst_qiqi<string opc, Intrinsic IntID>
 633   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 634              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 635              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 636
 637 class qi_SInst_qiqi_neg<string opc, Intrinsic IntID>
 638   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 639              !strconcat("$dst = ", !strconcat(opc , "($src1, !$src2)")),
 640              [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 641
 642 class di_SInst_di<string opc, Intrinsic IntID>
 643   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 644              !strconcat("$dst = ", !strconcat(opc , "($src)")),
 645              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 646
 647 class di_SInst_di_sat<string opc, Intrinsic IntID>
 648   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src),
 649              !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 650              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src))]>;
 651
 652 class si_SInst_di<string opc, Intrinsic IntID>
 653   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 654           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 655           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 656
 657 class si_SInst_di_sat<string opc, Intrinsic IntID>
 658   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src),
 659           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 660           [(set IntRegs:$dst, (IntID DoubleRegs:$src))]>;
 661
 662 class di_SInst_disi<string opc, Intrinsic IntID>
 663   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 664           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 665           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 666
 667 class di_SInst_didi<string opc, Intrinsic IntID>
 668   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
 669           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 670           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
 671
 672 class di_SInst_si<string opc, Intrinsic IntID>
 673   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1),
 674           !strconcat("$dst = ", !strconcat(opc , "($src1)")),
 675           [(set DoubleRegs:$dst, (IntID IntRegs:$src1))]>;
 676
 677 class si_SInst_sisiu3<string opc, Intrinsic IntID>
 678   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, u3Imm:$src3),
 679           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 680           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
 681                                      imm:$src3))]>;
 682
 683 class si_SInst_diu5<string opc, Intrinsic IntID>
 684   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, u5Imm:$src2),
 685           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 686           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 687
 688 class si_SInst_disi<string opc, Intrinsic IntID>
 689   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
 690           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 691           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
 692
 693 class si_SInst_sidi<string opc, Intrinsic IntID>
 694   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, DoubleRegs:$src2),
 695           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 696           [(set IntRegs:$dst, (IntID IntRegs:$src1, DoubleRegs:$src2))]>;
 697
 698 class di_SInst_disisi<string opc, Intrinsic IntID>
 699   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2,
 700                                        IntRegs:$src3),
 701           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 702           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2,
 703                                         IntRegs:$src3))]>;
 704
 705 class di_SInst_sisi<string opc, Intrinsic IntID>
 706   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 707           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 708           [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 709
 710 class qi_SInst_siu5<string opc, Intrinsic IntID>
 711   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 712           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 713           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 714
 715 class qi_SInst_siu6<string opc, Intrinsic IntID>
 716   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, u6Imm:$src2),
 717           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 718           [(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 719
 720 class qi_SInst_sisi<string opc, Intrinsic IntID>
 721   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 722           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 723           [(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 724
 725 class si_SInst_si<string opc, Intrinsic IntID>
 726   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 727           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 728           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 729
 730 class si_SInst_si_sat<string opc, Intrinsic IntID>
 731   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 732           !strconcat("$dst = ", !strconcat(opc , "($src):sat")),
 733           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 734
 735 class di_SInst_qi<string opc, Intrinsic IntID>
 736   : SInst<(outs DoubleRegs:$dst), (ins IntRegs:$src),
 737           !strconcat("$dst = ", !strconcat(opc , "($src)")),
 738           [(set DoubleRegs:$dst, (IntID IntRegs:$src))]>;
 739
 740 class si_SInst_qi<string opc, Intrinsic IntID>
 741   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src),
 742           !strconcat("$dst = ", !strconcat(opc , "$src")),
 743           [(set IntRegs:$dst, (IntID IntRegs:$src))]>;
 744
 745 class si_SInst_qiqi<string opc, Intrinsic IntID>
 746   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 747           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 748           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 749
 750 class qi_SInst_si<string opc, Intrinsic IntID>
 751   : SInst<(outs PredRegs:$dst), (ins IntRegs:$src),
 752           !strconcat("$dst = ", !strconcat(opc , "$src")),
 753           [(set PredRegs:$dst, (IntID IntRegs:$src))]>;
 754
 755 class si_SInst_sisi<string opc, Intrinsic IntID>
 756   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 757           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 758           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 759
 760 class di_SInst_diu6<string opc, Intrinsic IntID>
 761   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
 762           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 763           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2))]>;
 764
 765 class si_SInst_siu5<string opc, Intrinsic IntID>
 766   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 767           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
 768           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 769
 770 class si_SInst_siu5_rnd<string opc, Intrinsic IntID>
 771   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
 772           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):rnd")),
 773           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
 774
 775 class si_SInst_siu5u5<string opc, Intrinsic IntID>
 776   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2, u5Imm:$src3),
 777           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 778           [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2, imm:$src3))]>;
 779
 780 class si_SInst_sisisi_acc<string opc, Intrinsic IntID>
 781   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 782                                         IntRegs:$src2),
 783               !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 784               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 785                                          IntRegs:$src2))],
 786               "$dst2 = $dst">;
 787
 788 class si_SInst_sisisi_nac<string opc, Intrinsic IntID>
 789   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 790                                         IntRegs:$src2),
 791               !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 792               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 793                                          IntRegs:$src2))],
 794               "$dst2 = $dst">;
 795
 796 class di_SInst_didisi_acc<string opc, Intrinsic IntID>
 797   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 798                                            IntRegs:$src2),
 799                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
 800                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 801                                              DoubleRegs:$src1,
 802                                              IntRegs:$src2))],
 803                "$dst2 = $dst">;
 804
 805 class di_SInst_didisi_nac<string opc, Intrinsic IntID>
 806   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 807                                            IntRegs:$src2),
 808           !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
 809           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 810                                         DoubleRegs:$src1, IntRegs:$src2))],
 811           "$dst2 = $dst">;
 812
 813 class si_SInst_sisiu5u5<string opc, Intrinsic IntID>
 814   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 815                                         u5Imm:$src2, u5Imm:$src3),
 816               !strconcat("$dst = ", !strconcat(opc ,
 817                                                "($src1, #$src2, #$src3)")),
 818               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 819                                          imm:$src2, imm:$src3))],
 820               "$dst2 = $dst">;
 821
 822 class si_SInst_sisidi<string opc, Intrinsic IntID>
 823   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 824                                         DoubleRegs:$src2),
 825               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 826               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 827                                          DoubleRegs:$src2))],
 828               "$dst2 = $dst">;
 829
 830 class di_SInst_didiu6u6<string opc, Intrinsic IntID>
 831   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 832                                            u6Imm:$src2, u6Imm:$src3),
 833               !strconcat("$dst = ", !strconcat(opc ,
 834                                                "($src1, #$src2, #$src3)")),
 835               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 836                                             imm:$src2, imm:$src3))],
 837               "$dst2 = $dst">;
 838
 839 class di_SInst_dididi<string opc, Intrinsic IntID>
 840   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 841                                            DoubleRegs:$src2),
 842               !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
 843               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 844                                             DoubleRegs:$src1,
 845                                             DoubleRegs:$src2))],
 846               "$dst2 = $dst">;
 847
 848 class di_SInst_diu6u6<string opc, Intrinsic IntID>
 849   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2,
 850                                        u6Imm:$src3),
 851           !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2, #$src3)")),
 852           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, imm:$src2,
 853                                         imm:$src3))]>;
 854
 855 class di_SInst_didiqi<string opc, Intrinsic IntID>
 856   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 857                                        IntRegs:$src3),
 858           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, $src3)")),
 859           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 860                                         IntRegs:$src3))]>;
 861
 862 class di_SInst_didiu3<string opc, Intrinsic IntID>
 863   : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2,
 864                                        u3Imm:$src3),
 865           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2, #$src3)")),
 866           [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2,
 867                                         imm:$src3))]>;
 868
 869 class di_SInst_didisi_or<string opc, Intrinsic IntID>
 870   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 871                                            IntRegs:$src2),
 872           !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 873           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 874                                         IntRegs:$src2))],
 875           "$dst2 = $dst">;
 876
 877 class di_SInst_didisi_and<string opc, Intrinsic IntID>
 878   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 879                                            IntRegs:$src2),
 880           !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 881           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 882                                         IntRegs:$src2))],
 883           "$dst2 = $dst">;
 884
 885 class di_SInst_didiu6_and<string opc, Intrinsic IntID>
 886   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 887                                            u6Imm:$src2),
 888           !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 889           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 890                                         imm:$src2))],
 891           "$dst2 = $dst">;
 892
 893 class di_SInst_didiu6_or<string opc, Intrinsic IntID>
 894   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 895                                            u6Imm:$src2),
 896           !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 897           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 898                                         imm:$src2))],
 899           "$dst2 = $dst">;
 900
 901 class di_SInst_didiu6_xor<string opc, Intrinsic IntID>
 902   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 903                                            u6Imm:$src2),
 904           !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 905           [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 906                                         imm:$src2))],
 907           "$dst2 = $dst">;
 908
 909 class si_SInst_sisisi_and<string opc, Intrinsic IntID>
 910   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 911                                         IntRegs:$src2),
 912               !strconcat("$dst &= ", !strconcat(opc , "($src1, $src2)")),
 913               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 914                                          IntRegs:$src2))],
 915               "$dst2 = $dst">;
 916
 917 class si_SInst_sisisi_or<string opc, Intrinsic IntID>
 918   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 919                                         IntRegs:$src2),
 920               !strconcat("$dst |= ", !strconcat(opc , "($src1, $src2)")),
 921               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 922                                          IntRegs:$src2))],
 923               "$dst2 = $dst">;
 924
 925
 926 class si_SInst_sisiu5_and<string opc, Intrinsic IntID>
 927   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 928                                         u5Imm:$src2),
 929               !strconcat("$dst &= ", !strconcat(opc , "($src1, #$src2)")),
 930               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 931                                          imm:$src2))],
 932               "$dst2 = $dst">;
 933
 934 class si_SInst_sisiu5_or<string opc, Intrinsic IntID>
 935   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 936                                         u5Imm:$src2),
 937               !strconcat("$dst |= ", !strconcat(opc , "($src1, #$src2)")),
 938               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 939                                          imm:$src2))],
 940               "$dst2 = $dst">;
 941
 942 class si_SInst_sisiu5_xor<string opc, Intrinsic IntID>
 943   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 944                                         u5Imm:$src2),
 945               !strconcat("$dst ^= ", !strconcat(opc , "($src1, #$src2)")),
 946               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 947                                          imm:$src2))],
 948               "$dst2 = $dst">;
 949
 950 class si_SInst_sisiu5_acc<string opc, Intrinsic IntID>
 951   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 952                                         u5Imm:$src2),
 953               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 954               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 955                                          imm:$src2))],
 956               "$dst2 = $dst">;
 957
 958 class si_SInst_sisiu5_nac<string opc, Intrinsic IntID>
 959   : SInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
 960                                         u5Imm:$src2),
 961               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 962               [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
 963                                          imm:$src2))],
 964               "$dst2 = $dst">;
 965
 966 class di_SInst_didiu6_acc<string opc, Intrinsic IntID>
 967   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 968                                            u5Imm:$src2),
 969               !strconcat("$dst += ", !strconcat(opc , "($src1, #$src2)")),
 970               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
 971                                             DoubleRegs:$src1, imm:$src2))],
 972               "$dst2 = $dst">;
 973
 974 class di_SInst_didiu6_nac<string opc, Intrinsic IntID>
 975   : SInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
 976                                            u5Imm:$src2),
 977               !strconcat("$dst -= ", !strconcat(opc , "($src1, #$src2)")),
 978               [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
 979                                             imm:$src2))],
 980               "$dst2 = $dst">;
 981
 982
 983 //
 984 // MInst classes.
 985 //
 986
 987 class di_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
 988   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 989                !strconcat("$dst = ", !strconcat(opc ,
 990                                                 "($src1.H, $src2.H):<<1:rnd")),
 991                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 992
 993 class di_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
 994   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
 995                !strconcat("$dst = ", !strconcat(opc ,
 996                                                 "($src1.H, $src2.H):rnd")),
 997                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
 998
 999 class di_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1000   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1001                !strconcat("$dst = ", !strconcat(opc ,
1002                                                 "($src1.H, $src2.L):<<1:rnd")),
1003                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1004
1005 class di_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1006   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1007                !strconcat("$dst = ", !strconcat(opc ,
1008                                                 "($src1.H, $src2.L):rnd")),
1009                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1010
1011 class di_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1012   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1013                !strconcat("$dst = ", !strconcat(opc ,
1014                                                 "($src1.L, $src2.H):<<1:rnd")),
1015                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1016
1017 class di_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1018   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1019                !strconcat("$dst = ", !strconcat(opc ,
1020                                                 "($src1.L, $src2.H):rnd")),
1021                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1022
1023 class di_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1024   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1025                !strconcat("$dst = ", !strconcat(opc ,
1026                                                 "($src1.L, $src2.L):<<1:rnd")),
1027                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1028
1029 class di_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1030   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1031                !strconcat("$dst = ", !strconcat(opc ,
1032                                                 "($src1.L, $src2.L):rnd")),
1033                [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1034
1035 class di_MInst_disisi_acc<string opc, Intrinsic IntID>
1036   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1037                                            IntRegs:$src2),
1038              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1039              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1040                                            IntRegs:$src2))],
1041              "$dst2 = $dst">;
1042
1043 class di_MInst_disisi_nac<string opc, Intrinsic IntID>
1044   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1045                                            IntRegs:$src2),
1046              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2)")),
1047              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1048                                            IntRegs:$src2))],
1049              "$dst2 = $dst">;
1050
1051 class di_MInst_disisi_acc_sat<string opc, Intrinsic IntID>
1052   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1053                                            IntRegs:$src2),
1054              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1055              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1056                                            IntRegs:$src2))],
1057              "$dst2 = $dst">;
1058
1059 class di_MInst_disisi_nac_sat<string opc, Intrinsic IntID>
1060   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1061                                            IntRegs:$src2),
1062              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2):sat")),
1063              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1064                                            IntRegs:$src2))],
1065              "$dst2 = $dst">;
1066
1067 class di_MInst_disisi_acc_sat_conj<string opc, Intrinsic IntID>
1068   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1069                                            IntRegs:$src2),
1070              !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*):sat")),
1071              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1072                                            IntRegs:$src2))],
1073              "$dst2 = $dst">;
1074
1075 class di_MInst_disisi_nac_sat_conj<string opc, Intrinsic IntID>
1076   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1077                                            IntRegs:$src2),
1078              !strconcat("$dst -= ", !strconcat(opc , "($src1, $src2*):sat")),
1079              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1080                                            IntRegs:$src2))],
1081              "$dst2 = $dst">;
1082
1083 class di_MInst_disisi_nac_s1_sat<string opc, Intrinsic IntID>
1084   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1085                                            IntRegs:$src2),
1086              !strconcat("$dst -= ", !strconcat(opc ,
1087                                                "($src1, $src2):<<1:sat")),
1088              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1089                                            IntRegs:$src2))],
1090              "$dst2 = $dst">;
1091
1092 class di_MInst_disisi_acc_s1_sat_conj<string opc, Intrinsic IntID>
1093   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1094                                            IntRegs:$src2),
1095              !strconcat("$dst += ", !strconcat(opc ,
1096                                                "($src1, $src2*):<<1:sat")),
1097              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1098                                            IntRegs:$src2))],
1099              "$dst2 = $dst">;
1100
1101 class di_MInst_disisi_nac_s1_sat_conj<string opc, Intrinsic IntID>
1102   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1103                                            IntRegs:$src2),
1104              !strconcat("$dst -= ", !strconcat(opc ,
1105                                                "($src1, $src2*):<<1:sat")),
1106              [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1107                                            IntRegs:$src2))],
1108              "$dst2 = $dst">;
1109
1110 class di_MInst_s8s8<string opc, Intrinsic IntID>
1111   : MInst<(outs DoubleRegs:$dst), (ins s8Imm:$src1, s8Imm:$src2),
1112              !strconcat("$dst = ", !strconcat(opc , "(#$src1, #$src2)")),
1113              [(set DoubleRegs:$dst, (IntID imm:$src1, imm:$src2))]>;
1114
1115 class si_MInst_sis9<string opc, Intrinsic IntID>
1116   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Imm:$src2),
1117              !strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
1118              [(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
1119
1120 class si_MInst_sisi<string opc, Intrinsic IntID>
1121   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1122              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1123              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1124
1125 class di_MInst_sisi_hh<string opc, Intrinsic IntID>
1126   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1127              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1128              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1129
1130 class di_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1131   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1132              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1133              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1134
1135 class di_MInst_sisi_lh<string opc, Intrinsic IntID>
1136   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1137              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1138              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1139
1140 class di_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1141   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1142              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1143              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1144
1145 class di_MInst_sisi_hl<string opc, Intrinsic IntID>
1146   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1147              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1148              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1149
1150 class di_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1151   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1152              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1153              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1154
1155 class di_MInst_sisi_ll<string opc, Intrinsic IntID>
1156   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1157              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1158              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1159
1160 class di_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1161   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1162              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1163              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1164
1165
1166 class si_MInst_sisi_hh<string opc, Intrinsic IntID>
1167   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1168              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H)")),
1169              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1170
1171 class si_MInst_sisi_hh_s1<string opc, Intrinsic IntID>
1172   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1173              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):<<1")),
1174              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1175
1176 class si_MInst_sisi_lh<string opc, Intrinsic IntID>
1177   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1178              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H)")),
1179              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1180
1181 class si_MInst_sisi_lh_s1<string opc, Intrinsic IntID>
1182   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1183              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):<<1")),
1184              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1185
1186 class si_MInst_sisi_hl<string opc, Intrinsic IntID>
1187   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1188              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L)")),
1189              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1190
1191 class si_MInst_sisi_hl_s1<string opc, Intrinsic IntID>
1192   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1193              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):<<1")),
1194              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1195
1196 class si_MInst_sisi_ll<string opc, Intrinsic IntID>
1197   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1198              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L)")),
1199              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1200
1201 class si_MInst_sisi_ll_s1<string opc, Intrinsic IntID>
1202   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1203              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):<<1")),
1204              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1205
1206 class si_MInst_sisi_up<string opc, Intrinsic IntID>
1207   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1208              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1209              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1210
1211 class di_MInst_didi<string opc, Intrinsic IntID>
1212   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1213              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1214              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1215                                            DoubleRegs:$src2))]>;
1216
1217 class di_MInst_didi_conj<string opc, Intrinsic IntID>
1218   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1219              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*)")),
1220              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1221                                            DoubleRegs:$src2))]>;
1222
1223 class di_MInst_sisi_s1_sat_conj<string opc, Intrinsic IntID>
1224   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1225              !strconcat("$dst = ", !strconcat(opc ,
1226                                               "($src1, $src2*):<<1:sat")),
1227              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1228
1229 class di_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1230   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1231              !strconcat("$dst = ", !strconcat(opc ,
1232                                               "($src1, $src2):<<1:rnd:sat")),
1233              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1234                                            DoubleRegs:$src2))]>;
1235
1236 class di_MInst_didi_sat<string opc, Intrinsic IntID>
1237   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1238              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1239              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1240                                            DoubleRegs:$src2))]>;
1241
1242 class di_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1243   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1244              !strconcat("$dst = ", !strconcat(opc ,
1245                                               "($src1, $src2):rnd:sat")),
1246              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1247                                            DoubleRegs:$src2))]>;
1248
1249 class si_SInst_sisi_sat<string opc, Intrinsic IntID>
1250   : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1251           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1252           [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1253
1254 class si_SInst_didi_sat<string opc, Intrinsic IntID>
1255   : SInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1256           !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1257           [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1258
1259 class si_SInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
1260   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
1261              !strconcat("$dst = ", !strconcat(opc ,
1262                                               "($src1, $src2):<<1:rnd:sat")),
1263              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
1264
1265 class si_MInst_sisi_s1_rnd_sat<string opc, Intrinsic IntID>
1266   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1267              !strconcat("$dst = ", !strconcat(opc ,
1268                                               "($src1, $src2):<<1:rnd:sat")),
1269              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1270
1271 class si_MInst_sisi_l_s1_rnd_sat<string opc, Intrinsic IntID>
1272   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1273              !strconcat("$dst = ", !strconcat(opc ,
1274                                               "($src1, $src2.L):<<1:rnd:sat")),
1275              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1276
1277 class si_MInst_sisi_h_s1_rnd_sat<string opc, Intrinsic IntID>
1278   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1279              !strconcat("$dst = ", !strconcat(opc ,
1280                                               "($src1, $src2.H):<<1:rnd:sat")),
1281              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1282
1283 class si_MInst_sisi_rnd_sat_conj<string opc, Intrinsic IntID>
1284   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1285              !strconcat("$dst = ", !strconcat(opc ,
1286                                               "($src1, $src2*):rnd:sat")),
1287              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1288
1289 class si_MInst_sisi_s1_rnd_sat_conj<string opc, Intrinsic IntID>
1290   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1291              !strconcat("$dst = ", !strconcat(opc ,
1292                                               "($src1, $src2*):<<1:rnd:sat")),
1293              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1294
1295 class si_MInst_sisi_rnd_sat<string opc, Intrinsic IntID>
1296   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1297              !strconcat("$dst = ", !strconcat(opc ,
1298                                               "($src1, $src2):rnd:sat")),
1299              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1300
1301 class si_MInst_sisi_rnd<string opc, Intrinsic IntID>
1302   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1303              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd")),
1304              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1305
1306 class si_MInst_sisisi_xacc<string opc, Intrinsic IntID>
1307   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1308                                         IntRegs:$src3),
1309              !strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
1310              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1311                                         IntRegs:$src3))],
1312              "$dst2 = $dst">;
1313
1314 class si_MInst_sisisi_acc<string opc, Intrinsic IntID>
1315   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1316                                         IntRegs:$src3),
1317              !strconcat("$dst += ", !strconcat(opc , "($src2, $src3)")),
1318              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1319                                         IntRegs:$src3))],
1320              "$dst2 = $dst">;
1321
1322 class si_MInst_sisisi_nac<string opc, Intrinsic IntID>
1323   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1324                                         IntRegs:$src3),
1325              !strconcat("$dst -= ", !strconcat(opc , "($src2, $src3)")),
1326              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1327                                         IntRegs:$src3))],
1328              "$dst2 = $dst">;
1329
1330 class si_MInst_sisis8_acc<string opc, Intrinsic IntID>
1331   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1332                                         s8Imm:$src3),
1333              !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1334              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1335                                         imm:$src3))],
1336              "$dst2 = $dst">;
1337
1338 class si_MInst_sisis8_nac<string opc, Intrinsic IntID>
1339   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1340                                         s8Imm:$src3),
1341              !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1342              [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1343                                         imm:$src3))],
1344              "$dst2 = $dst">;
1345
1346 class si_MInst_sisiu4u5<string opc, Intrinsic IntID>
1347   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1348                                         u4Imm:$src2, u5Imm:$src3),
1349                !strconcat("$dst = ", !strconcat(opc ,
1350                                                 "($src1, #$src2, #$src3)")),
1351                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1352                                           imm:$src2, imm:$src3))],
1353                "$dst2 = $dst">;
1354
1355 class si_MInst_sisiu8_acc<string opc, Intrinsic IntID>
1356   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1357                                         u8Imm:$src3),
1358                !strconcat("$dst += ", !strconcat(opc , "($src2, #$src3)")),
1359                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1360                                           imm:$src3))],
1361                "$dst2 = $dst">;
1362
1363 class si_MInst_sisiu8_nac<string opc, Intrinsic IntID>
1364   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src2,
1365                                         u8Imm:$src3),
1366                !strconcat("$dst -= ", !strconcat(opc , "($src2, #$src3)")),
1367                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src2,
1368                                           imm:$src3))],
1369                "$dst2 = $dst">;
1370
1371 class si_MInst_sisisi_acc_hh<string opc, Intrinsic IntID>
1372   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1373                                         IntRegs:$src2),
1374                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1375                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1376                                           IntRegs:$src2))],
1377                "$dst2 = $dst">;
1378
1379 class si_MInst_sisisi_acc_sat_lh<string opc, Intrinsic IntID>
1380   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1381                                         IntRegs:$src2),
1382                !strconcat("$dst += ", !strconcat(opc ,
1383                                                  "($src1.L, $src2.H):sat")),
1384                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1385                                           IntRegs:$src2))],
1386                "$dst2 = $dst">;
1387
1388 class si_MInst_sisisi_acc_sat_lh_s1<string opc, Intrinsic IntID>
1389   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1390                                         IntRegs:$src2),
1391                !strconcat("$dst += ", !strconcat(opc ,
1392                                                  "($src1.L, $src2.H):<<1:sat")),
1393                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1394                                           IntRegs:$src2))],
1395                "$dst2 = $dst">;
1396
1397 class si_MInst_sisisi_acc_sat_hh<string opc, Intrinsic IntID>
1398   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1399                                         IntRegs:$src2),
1400                !strconcat("$dst += ", !strconcat(opc ,
1401                                                  "($src1.H, $src2.H):sat")),
1402                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1403                                           IntRegs:$src2))],
1404                "$dst2 = $dst">;
1405
1406 class si_MInst_sisisi_acc_sat_hh_s1<string opc, Intrinsic IntID>
1407   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1408                                         IntRegs:$src2),
1409                !strconcat("$dst += ", !strconcat(opc ,
1410                                                  "($src1.H, $src2.H):<<1:sat")),
1411                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1412                                           IntRegs:$src2))],
1413                "$dst2 = $dst">;
1414
1415 class si_MInst_sisisi_acc_hh_s1<string opc, Intrinsic IntID>
1416   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1417                                         IntRegs:$src2),
1418                !strconcat("$dst += ", !strconcat(opc ,
1419                                                  "($src1.H, $src2.H):<<1")),
1420                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1421                                           IntRegs:$src2))],
1422                "$dst2 = $dst">;
1423
1424 class si_MInst_sisisi_nac_hh<string opc, Intrinsic IntID>
1425   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1426                                         IntRegs:$src2),
1427                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
1428                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1429                                           IntRegs:$src2))],
1430                "$dst2 = $dst">;
1431
1432 class si_MInst_sisisi_nac_sat_hh_s1<string opc, Intrinsic IntID>
1433   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1434                                         IntRegs:$src2),
1435                !strconcat("$dst -= ", !strconcat(opc ,
1436                                                  "($src1.H, $src2.H):<<1:sat")),
1437                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1438                                           IntRegs:$src2))],
1439                "$dst2 = $dst">;
1440
1441 class si_MInst_sisisi_nac_sat_hh<string opc, Intrinsic IntID>
1442   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1443                                         IntRegs:$src2),
1444                !strconcat("$dst -= ", !strconcat(opc ,
1445                                                  "($src1.H, $src2.H):sat")),
1446                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1447                                           IntRegs:$src2))],
1448                "$dst2 = $dst">;
1449
1450 class si_MInst_sisisi_nac_sat_hl_s1<string opc, Intrinsic IntID>
1451   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1452                                         IntRegs:$src2),
1453                !strconcat("$dst -= ", !strconcat(opc ,
1454                                                  "($src1.H, $src2.L):<<1:sat")),
1455                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1456                                           IntRegs:$src2))],
1457                "$dst2 = $dst">;
1458
1459 class si_MInst_sisisi_nac_sat_hl<string opc, Intrinsic IntID>
1460   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1461                                         IntRegs:$src2),
1462                !strconcat("$dst -= ", !strconcat(opc ,
1463                                                  "($src1.H, $src2.L):sat")),
1464                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1465                                           IntRegs:$src2))],
1466                "$dst2 = $dst">;
1467
1468 class si_MInst_sisisi_nac_sat_lh_s1<string opc, Intrinsic IntID>
1469   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1470                                         IntRegs:$src2),
1471                !strconcat("$dst -= ", !strconcat(opc ,
1472                                                  "($src1.L, $src2.H):<<1:sat")),
1473                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1474                                           IntRegs:$src2))],
1475                "$dst2 = $dst">;
1476
1477 class si_MInst_sisisi_nac_sat_lh<string opc, Intrinsic IntID>
1478   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1479                                         IntRegs:$src2),
1480                !strconcat("$dst -= ", !strconcat(opc ,
1481                                                  "($src1.L, $src2.H):sat")),
1482                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1483                                           IntRegs:$src2))],
1484                "$dst2 = $dst">;
1485
1486 class si_MInst_sisisi_nac_sat_ll_s1<string opc, Intrinsic IntID>
1487   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1488                                         IntRegs:$src2),
1489                !strconcat("$dst -= ", !strconcat(opc ,
1490                                                  "($src1.L, $src2.L):<<1:sat")),
1491                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1492                                           IntRegs:$src2))],
1493                "$dst2 = $dst">;
1494
1495 class si_MInst_sisisi_nac_sat_ll<string opc, Intrinsic IntID>
1496   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1497                                         IntRegs:$src2),
1498                !strconcat("$dst -= ", !strconcat(opc ,
1499                                                  "($src1.L, $src2.L):sat")),
1500                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1501                                           IntRegs:$src2))],
1502                "$dst2 = $dst">;
1503
1504 class si_MInst_sisisi_nac_hh_s1<string opc, Intrinsic IntID>
1505   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1506                                         IntRegs:$src2),
1507                !strconcat("$dst -= ", !strconcat(opc ,
1508                                                  "($src1.H, $src2.H):<<1")),
1509                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1510                                           IntRegs:$src2))],
1511                "$dst2 = $dst">;
1512
1513 class si_MInst_sisisi_acc_hl<string opc, Intrinsic IntID>
1514   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1515                                         IntRegs:$src2),
1516                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1517                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1518                                           IntRegs:$src2))],
1519                "$dst2 = $dst">;
1520
1521 class si_MInst_sisisi_acc_hl_s1<string opc, Intrinsic IntID>
1522   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1523                                         IntRegs:$src2),
1524                !strconcat("$dst += ", !strconcat(opc ,
1525                                                  "($src1.H, $src2.L):<<1")),
1526                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1527                                           IntRegs:$src2))],
1528                "$dst2 = $dst">;
1529
1530 class si_MInst_sisisi_nac_hl<string opc, Intrinsic IntID>
1531   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1532                                         IntRegs:$src2),
1533                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
1534                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1535                                           IntRegs:$src2))],
1536                "$dst2 = $dst">;
1537
1538 class si_MInst_sisisi_nac_hl_s1<string opc, Intrinsic IntID>
1539   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1540                                         IntRegs:$src2),
1541                !strconcat("$dst -= ", !strconcat(opc ,
1542                                                  "($src1.H, $src2.L):<<1")),
1543                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1544                                           IntRegs:$src2))],
1545                "$dst2 = $dst">;
1546
1547 class si_MInst_sisisi_acc_lh<string opc, Intrinsic IntID>
1548   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1549                                         IntRegs:$src2),
1550                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1551                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1552                                           IntRegs:$src2))],
1553                "$dst2 = $dst">;
1554
1555 class si_MInst_sisisi_acc_lh_s1<string opc, Intrinsic IntID>
1556   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1557                                         IntRegs:$src2),
1558                !strconcat("$dst += ", !strconcat(opc ,
1559                                                  "($src1.L, $src2.H):<<1")),
1560                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1561                                           IntRegs:$src2))],
1562                "$dst2 = $dst">;
1563
1564 class si_MInst_sisisi_nac_lh<string opc, Intrinsic IntID>
1565   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1566                                         IntRegs:$src2),
1567                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
1568                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1569                                           IntRegs:$src2))],
1570                "$dst2 = $dst">;
1571
1572 class si_MInst_sisisi_nac_lh_s1<string opc, Intrinsic IntID>
1573   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1574                                         IntRegs:$src2),
1575                !strconcat("$dst -= ", !strconcat(opc ,
1576                                                  "($src1.L, $src2.H):<<1")),
1577                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1578                                           IntRegs:$src2))],
1579                "$dst2 = $dst">;
1580
1581 class si_MInst_sisisi_acc_ll<string opc, Intrinsic IntID>
1582   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1583                                         IntRegs:$src2),
1584                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
1585                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1586                                           IntRegs:$src2))],
1587                "$dst2 = $dst">;
1588
1589 class si_MInst_sisisi_acc_ll_s1<string opc, Intrinsic IntID>
1590   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1591                                         IntRegs:$src2),
1592                !strconcat("$dst += ", !strconcat(opc ,
1593                                                  "($src1.L, $src2.L):<<1")),
1594                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1595                                           IntRegs:$src2))],
1596                "$dst2 = $dst">;
1597
1598 class si_MInst_sisisi_acc_sat_ll_s1<string opc, Intrinsic IntID>
1599   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1600                                         IntRegs:$src2),
1601                !strconcat("$dst += ", !strconcat(opc ,
1602                                                  "($src1.L, $src2.L):<<1:sat")),
1603                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1604                                           IntRegs:$src2))],
1605                "$dst2 = $dst">;
1606
1607 class si_MInst_sisisi_acc_sat_hl_s1<string opc, Intrinsic IntID>
1608   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1609                                         IntRegs:$src2),
1610                !strconcat("$dst += ", !strconcat(opc ,
1611                                                  "($src1.H, $src2.L):<<1:sat")),
1612                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1613                                           IntRegs:$src2))],
1614                "$dst2 = $dst">;
1615
1616 class si_MInst_sisisi_acc_sat_ll<string opc, Intrinsic IntID>
1617   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1618                                         IntRegs:$src2),
1619                !strconcat("$dst += ", !strconcat(opc ,
1620                                                  "($src1.L, $src2.L):sat")),
1621                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1622                                           IntRegs:$src2))],
1623                "$dst2 = $dst">;
1624
1625 class si_MInst_sisisi_acc_sat_hl<string opc, Intrinsic IntID>
1626   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1627                                         IntRegs:$src2),
1628                !strconcat("$dst += ", !strconcat(opc ,
1629                                                  "($src1.H, $src2.L):sat")),
1630                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1631                                           IntRegs:$src2))],
1632                "$dst2 = $dst">;
1633
1634 class si_MInst_sisisi_nac_ll<string opc, Intrinsic IntID>
1635   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1636                                         IntRegs:$src2),
1637                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
1638                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1639                                           IntRegs:$src2))],
1640                "$dst2 = $dst">;
1641
1642 class si_MInst_sisisi_nac_ll_s1<string opc, Intrinsic IntID>
1643   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1644                                         IntRegs:$src2),
1645                !strconcat("$dst -= ", !strconcat(opc ,
1646                                                  "($src1.L, $src2.L):<<1")),
1647                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1648                                           IntRegs:$src2))],
1649                "$dst2 = $dst">;
1650
1651 class si_MInst_sisisi_nac_hh_sat<string opc, Intrinsic IntID>
1652   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1653                                         IntRegs:$src2),
1654                !strconcat("$dst -= ", !strconcat(opc ,
1655                                                  "($src1.H, $src2.H):sat")),
1656                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1657                                           IntRegs:$src2))],
1658                "$dst2 = $dst">;
1659
1660 class si_MInst_sisisi_nac_hh_s1_sat<string opc, Intrinsic IntID>
1661   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1662                                         IntRegs:$src2),
1663                !strconcat("$dst -= ", !strconcat(opc ,
1664                                                  "($src1.H, $src2.H):<<1:sat")),
1665                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1666                                           IntRegs:$src2))],
1667                "$dst2 = $dst">;
1668
1669 class si_MInst_sisisi_nac_hl_sat<string opc, Intrinsic IntID>
1670   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1671                                         IntRegs:$src2),
1672                !strconcat("$dst -= ", !strconcat(opc ,
1673                                                  "($src1.H, $src2.L):sat")),
1674                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1675                                           IntRegs:$src2))],
1676                "$dst2 = $dst">;
1677
1678 class si_MInst_sisisi_nac_hl_s1_sat<string opc, Intrinsic IntID>
1679   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1680                                         IntRegs:$src2),
1681                !strconcat("$dst -= ", !strconcat(opc ,
1682                                                  "($src1.H, $src2.L):<<1:sat")),
1683                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1684                                           IntRegs:$src2))],
1685                "$dst2 = $dst">;
1686
1687 class si_MInst_sisisi_nac_lh_sat<string opc, Intrinsic IntID>
1688   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1689                                         IntRegs:$src2),
1690                !strconcat("$dst -= ", !strconcat(opc ,
1691                                                  "($src1.L, $src2.H):sat")),
1692                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1693                                           IntRegs:$src2))],
1694                "$dst2 = $dst">;
1695
1696 class si_MInst_sisisi_nac_lh_s1_sat<string opc, Intrinsic IntID>
1697   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1698                                         IntRegs:$src2),
1699                !strconcat("$dst -= ", !strconcat(opc ,
1700                                                  "($src1.L, $src2.H):<<1:sat")),
1701                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1702                                           IntRegs:$src2))],
1703                "$dst2 = $dst">;
1704
1705 class si_MInst_sisisi_nac_ll_sat<string opc, Intrinsic IntID>
1706   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1707                                         IntRegs:$src2),
1708                !strconcat("$dst -= ", !strconcat(opc ,
1709                                                  "($src1.L, $src2.L):sat")),
1710                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1711                                           IntRegs:$src2))],
1712                "$dst2 = $dst">;
1713
1714 class si_MInst_sisisi_nac_ll_s1_sat<string opc, Intrinsic IntID>
1715   : MInst_acc<(outs IntRegs:$dst), (ins IntRegs:$dst2, IntRegs:$src1,
1716                                         IntRegs:$src2),
1717                !strconcat("$dst -= ", !strconcat(opc ,
1718                                                  "($src1.L, $src2.L):<<1:sat")),
1719                [(set IntRegs:$dst, (IntID IntRegs:$dst2, IntRegs:$src1,
1720                                           IntRegs:$src2))],
1721                "$dst2 = $dst">;
1722
1723 class di_ALU32_sisi<string opc, Intrinsic IntID>
1724   : ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1725              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1726              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1727
1728 class di_MInst_sisi<string opc, Intrinsic IntID>
1729   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1730              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
1731              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1732
1733 class di_MInst_sisi_sat<string opc, Intrinsic IntID>
1734   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1735              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):sat")),
1736              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1737
1738 class di_MInst_sisi_sat_conj<string opc, Intrinsic IntID>
1739   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1740              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2*):sat")),
1741              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1742
1743 class di_MInst_sisi_s1_sat<string opc, Intrinsic IntID>
1744   : MInst<(outs DoubleRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1745              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1746              [(set DoubleRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1747
1748 class di_MInst_didi_s1_sat<string opc, Intrinsic IntID>
1749   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1750              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
1751              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1,
1752                                            DoubleRegs:$src2))]>;
1753
1754 class si_MInst_didi_s1_rnd_sat<string opc, Intrinsic IntID>
1755   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1756              !strconcat("$dst = ", !strconcat(opc ,
1757                                               "($src1, $src2):<<1:rnd:sat")),
1758              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1759
1760 class si_MInst_didi_rnd_sat<string opc, Intrinsic IntID>
1761   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
1762              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):rnd:sat")),
1763              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
1764
1765 class si_MInst_sisi_sat_hh<string opc, Intrinsic IntID>
1766   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1767              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.H):sat")),
1768              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1769
1770 class si_MInst_sisi_sat_hh_s1<string opc, Intrinsic IntID>
1771   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1772                !strconcat("$dst = ", !strconcat(opc ,
1773                                                 "($src1.H, $src2.H):<<1:sat")),
1774                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1775
1776 class si_MInst_sisi_sat_hl<string opc, Intrinsic IntID>
1777   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1778              !strconcat("$dst = ", !strconcat(opc , "($src1.H, $src2.L):sat")),
1779              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1780
1781 class si_MInst_sisi_sat_hl_s1<string opc, Intrinsic IntID>
1782   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1783                !strconcat("$dst = ", !strconcat(opc ,
1784                                                 "($src1.H, $src2.L):<<1:sat")),
1785                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1786
1787 class si_MInst_sisi_sat_lh<string opc, Intrinsic IntID>
1788   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1789              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.H):sat")),
1790              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1791
1792 class si_MInst_sisi_sat_lh_s1<string opc, Intrinsic IntID>
1793   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1794                !strconcat("$dst = ", !strconcat(opc ,
1795                                                 "($src1.L, $src2.H):<<1:sat")),
1796                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1797
1798 class si_MInst_sisi_sat_ll<string opc, Intrinsic IntID>
1799   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1800              !strconcat("$dst = ", !strconcat(opc , "($src1.L, $src2.L):sat")),
1801              [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1802
1803 class si_MInst_sisi_sat_ll_s1<string opc, Intrinsic IntID>
1804   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1805                !strconcat("$dst = ", !strconcat(opc ,
1806                                                 "($src1.L, $src2.L):<<1:sat")),
1807                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1808
1809 class si_MInst_sisi_sat_rnd_hh<string opc, Intrinsic IntID>
1810   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1811                !strconcat("$dst = ", !strconcat(opc ,
1812                                                 "($src1.H, $src2.H):rnd:sat")),
1813                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1814
1815 class si_MInst_sisi_rnd_hh<string opc, Intrinsic IntID>
1816   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1817                !strconcat("$dst = ", !strconcat(opc ,
1818                                                 "($src1.H, $src2.H):rnd")),
1819                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1820
1821 class si_MInst_sisi_rnd_hh_s1<string opc, Intrinsic IntID>
1822   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1823                !strconcat("$dst = ", !strconcat(opc ,
1824                                                 "($src1.H, $src2.H):<<1:rnd")),
1825                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1826
1827 class si_MInst_sisi_sat_rnd_hh_s1<string opc, Intrinsic IntID>
1828   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1829                !strconcat("$dst = ",
1830                           !strconcat(opc ,
1831                                      "($src1.H, $src2.H):<<1:rnd:sat")),
1832                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1833
1834 class si_MInst_sisi_rnd_hl<string opc, Intrinsic IntID>
1835   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1836                !strconcat("$dst = ",
1837                           !strconcat(opc , "($src1.H, $src2.L):rnd")),
1838                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1839
1840 class si_MInst_sisi_rnd_hl_s1<string opc, Intrinsic IntID>
1841   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1842                !strconcat("$dst = ",
1843                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd")),
1844                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1845
1846 class si_MInst_sisi_sat_rnd_hl<string opc, Intrinsic IntID>
1847   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1848                !strconcat("$dst = ",
1849                           !strconcat(opc , "($src1.H, $src2.L):rnd:sat")),
1850                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1851
1852 class si_MInst_sisi_sat_rnd_hl_s1<string opc, Intrinsic IntID>
1853   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1854                !strconcat("$dst = ",
1855                           !strconcat(opc , "($src1.H, $src2.L):<<1:rnd:sat")),
1856                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1857
1858 class si_MInst_sisi_rnd_lh<string opc, Intrinsic IntID>
1859   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1860                !strconcat("$dst = ",
1861                           !strconcat(opc , "($src1.L, $src2.H):rnd")),
1862                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1863
1864 class si_MInst_sisi_sat_rnd_lh<string opc, Intrinsic IntID>
1865   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1866                !strconcat("$dst = ",
1867                           !strconcat(opc , "($src1.L, $src2.H):rnd:sat")),
1868                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1869
1870 class si_MInst_sisi_sat_rnd_lh_s1<string opc, Intrinsic IntID>
1871   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1872                !strconcat("$dst = ",
1873                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd:sat")),
1874                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1875
1876 class si_MInst_sisi_rnd_lh_s1<string opc, Intrinsic IntID>
1877   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1878                !strconcat("$dst = ",
1879                           !strconcat(opc , "($src1.L, $src2.H):<<1:rnd")),
1880                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1881
1882 class si_MInst_sisi_sat_rnd_ll<string opc, Intrinsic IntID>
1883   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1884                !strconcat("$dst = ",
1885                           !strconcat(opc , "($src1.L, $src2.L):rnd:sat")),
1886                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1887
1888 class si_MInst_sisi_sat_rnd_ll_s1<string opc, Intrinsic IntID>
1889   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1890                !strconcat("$dst = ",
1891                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd:sat")),
1892                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1893
1894 class si_MInst_sisi_rnd_ll<string opc, Intrinsic IntID>
1895   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1896                !strconcat("$dst = ",
1897                           !strconcat(opc , "($src1.L, $src2.L):rnd")),
1898                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1899
1900 class si_MInst_sisi_rnd_ll_s1<string opc, Intrinsic IntID>
1901   : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
1902                !strconcat("$dst = ",
1903                           !strconcat(opc , "($src1.L, $src2.L):<<1:rnd")),
1904                [(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
1905
1906 class di_MInst_dididi_acc_sat<string opc, Intrinsic IntID>
1907   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1908                                            DoubleRegs:$src1, DoubleRegs:$src2),
1909                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2):sat")),
1910                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1911                                              DoubleRegs:$src1,
1912                                              DoubleRegs:$src2))],
1913                "$dst2 = $dst">;
1914
1915 class di_MInst_dididi_acc_rnd_sat<string opc, Intrinsic IntID>
1916   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1917                                            DoubleRegs:$src2),
1918                !strconcat("$dst += ",
1919                           !strconcat(opc , "($src1, $src2):rnd:sat")),
1920                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1921                                              DoubleRegs:$src1,
1922                                              DoubleRegs:$src2))],
1923                "$dst2 = $dst">;
1924
1925 class di_MInst_dididi_acc_s1<string opc, Intrinsic IntID>
1926   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1927                                            DoubleRegs:$src1,
1928                                            DoubleRegs:$src2),
1929                !strconcat("$dst += ",
1930                           !strconcat(opc , "($src1, $src2):<<1")),
1931                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1932                                              DoubleRegs:$src1,
1933                                              DoubleRegs:$src2))],
1934                "$dst2 = $dst">;
1935
1936
1937 class di_MInst_dididi_acc_s1_sat<string opc, Intrinsic IntID>
1938   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2,
1939                                            DoubleRegs:$src1,
1940                                            DoubleRegs:$src2),
1941                !strconcat("$dst += ",
1942                           !strconcat(opc , "($src1, $src2):<<1:sat")),
1943                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1944                                              DoubleRegs:$src1,
1945                                              DoubleRegs:$src2))],
1946                "$dst2 = $dst">;
1947
1948 class di_MInst_dididi_acc_s1_rnd_sat<string opc, Intrinsic IntID>
1949   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1950                                            DoubleRegs:$src2),
1951                !strconcat("$dst += ",
1952                           !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
1953                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1954                                              DoubleRegs:$src1,
1955                                              DoubleRegs:$src2))],
1956                "$dst2 = $dst">;
1957
1958 class di_MInst_dididi_acc<string opc, Intrinsic IntID>
1959   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1960                                            DoubleRegs:$src2),
1961                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")),
1962                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1963                                              DoubleRegs:$src1,
1964                                              DoubleRegs:$src2))],
1965                "$dst2 = $dst">;
1966
1967 class di_MInst_dididi_acc_conj<string opc, Intrinsic IntID>
1968   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
1969                                            DoubleRegs:$src2),
1970                !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")),
1971                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
1972                                              DoubleRegs:$src1,
1973                                              DoubleRegs:$src2))],
1974                "$dst2 = $dst">;
1975
1976 class di_MInst_disisi_acc_hh<string opc, Intrinsic IntID>
1977   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1978                                            IntRegs:$src2),
1979                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.H)")),
1980                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1981                                              IntRegs:$src2))],
1982                "$dst2 = $dst">;
1983
1984 class di_MInst_disisi_acc_hl<string opc, Intrinsic IntID>
1985   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1986                                            IntRegs:$src2),
1987                !strconcat("$dst += ", !strconcat(opc , "($src1.H, $src2.L)")),
1988                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1989                                              IntRegs:$src2))],
1990                "$dst2 = $dst">;
1991
1992 class di_MInst_disisi_acc_lh<string opc, Intrinsic IntID>
1993   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
1994                                            IntRegs:$src2),
1995                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.H)")),
1996                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
1997                                              IntRegs:$src2))],
1998                "$dst2 = $dst">;
1999
2000 class di_MInst_disisi_acc_ll<string opc, Intrinsic IntID>
2001   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2002                                            IntRegs:$src2),
2003                !strconcat("$dst += ", !strconcat(opc , "($src1.L, $src2.L)")),
2004                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2005                                              IntRegs:$src2))],
2006                "$dst2 = $dst">;
2007
2008 class di_MInst_disisi_acc_hh_s1<string opc, Intrinsic IntID>
2009   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2010                                            IntRegs:$src2),
2011                !strconcat("$dst += ",
2012                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2013                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2014                                              IntRegs:$src2))],
2015                "$dst2 = $dst">;
2016
2017 class di_MInst_disisi_acc_hl_s1<string opc, Intrinsic IntID>
2018   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2019                                            IntRegs:$src2),
2020                !strconcat("$dst += ",
2021                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2022                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2023                                              IntRegs:$src2))],
2024                "$dst2 = $dst">;
2025
2026 class di_MInst_disisi_acc_lh_s1<string opc, Intrinsic IntID>
2027   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2028                                            IntRegs:$src2),
2029                !strconcat("$dst += ",
2030                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2031                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2032                                              IntRegs:$src2))],
2033                "$dst2 = $dst">;
2034
2035 class di_MInst_disisi_acc_ll_s1<string opc, Intrinsic IntID>
2036   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2037                                            IntRegs:$src2),
2038                !strconcat("$dst += ",
2039                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2040                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2041                                              IntRegs:$src2))],
2042                "$dst2 = $dst">;
2043
2044 class di_MInst_disisi_nac_hh<string opc, Intrinsic IntID>
2045   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2046                                            IntRegs:$src2),
2047                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.H)")),
2048                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2049                                              IntRegs:$src2))],
2050                "$dst2 = $dst">;
2051
2052 class di_MInst_disisi_nac_hl<string opc, Intrinsic IntID>
2053   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2054                                            IntRegs:$src2),
2055                !strconcat("$dst -= ", !strconcat(opc , "($src1.H, $src2.L)")),
2056                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2057                                              IntRegs:$src2))],
2058                "$dst2 = $dst">;
2059
2060 class di_MInst_disisi_nac_lh<string opc, Intrinsic IntID>
2061   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2062                                            IntRegs:$src2),
2063                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.H)")),
2064                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2065                                              IntRegs:$src2))],
2066                "$dst2 = $dst">;
2067
2068 class di_MInst_disisi_nac_ll<string opc, Intrinsic IntID>
2069   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2070                                            IntRegs:$src2),
2071                !strconcat("$dst -= ", !strconcat(opc , "($src1.L, $src2.L)")),
2072                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2073                                              IntRegs:$src2))],
2074                "$dst2 = $dst">;
2075
2076 class di_MInst_disisi_nac_hh_s1<string opc, Intrinsic IntID>
2077   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2078                                            IntRegs:$src2),
2079                !strconcat("$dst -= ",
2080                           !strconcat(opc , "($src1.H, $src2.H):<<1")),
2081                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2082                                              IntRegs:$src2))],
2083                "$dst2 = $dst">;
2084
2085 class di_MInst_disisi_nac_hl_s1<string opc, Intrinsic IntID>
2086   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2087                                            IntRegs:$src2),
2088                !strconcat("$dst -= ",
2089                           !strconcat(opc , "($src1.H, $src2.L):<<1")),
2090                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2091                                              IntRegs:$src2))],
2092                "$dst2 = $dst">;
2093
2094 class di_MInst_disisi_nac_lh_s1<string opc, Intrinsic IntID>
2095   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2096                                            IntRegs:$src2),
2097                !strconcat("$dst -= ",
2098                           !strconcat(opc , "($src1.L, $src2.H):<<1")),
2099                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2100                                              IntRegs:$src2))],
2101                "$dst2 = $dst">;
2102
2103 class di_MInst_disisi_nac_ll_s1<string opc, Intrinsic IntID>
2104   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2105                                            IntRegs:$src2),
2106                !strconcat("$dst -= ",
2107                           !strconcat(opc , "($src1.L, $src2.L):<<1")),
2108                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2109                                              IntRegs:$src2))],
2110                "$dst2 = $dst">;
2111
2112 class di_MInst_disisi_acc_s1_sat<string opc, Intrinsic IntID>
2113   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1,
2114                                            IntRegs:$src2),
2115                !strconcat("$dst += ",
2116                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2117                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, IntRegs:$src1,
2118                                              IntRegs:$src2))],
2119                "$dst2 = $dst">;
2120
2121 class di_MInst_disi_s1_sat<string opc, Intrinsic IntID>
2122   : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2123              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2):<<1:sat")),
2124              [(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2125
2126 class di_MInst_didisi_acc_s1_sat<string opc, Intrinsic IntID>
2127   : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
2128                                            IntRegs:$src2),
2129                !strconcat("$dst += ",
2130                           !strconcat(opc , "($src1, $src2):<<1:sat")),
2131                [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2,
2132                                              DoubleRegs:$src1,
2133                                              IntRegs:$src2))],
2134                "$dst2 = $dst">;
2135
2136 class si_MInst_disi_s1_rnd_sat<string opc, Intrinsic IntID>
2137   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, IntRegs:$src2),
2138              !strconcat("$dst = ",
2139                         !strconcat(opc , "($src1, $src2):<<1:rnd:sat")),
2140              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, IntRegs:$src2))]>;
2141
2142 class si_MInst_didi<string opc, Intrinsic IntID>
2143   : MInst<(outs IntRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
2144              !strconcat("$dst = ", !strconcat(opc , "($src1, $src2)")),
2145              [(set IntRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
2146
2147 //
2148 // LDInst classes.
2149 //
2150 let mayLoad = 1, hasSideEffects = 0 in
2151 class di_LDInstPI_diu4<string opc, Intrinsic IntID>
2152   : LDInstPI<(outs IntRegs:$dst, DoubleRegs:$dst2),
2153            (ins IntRegs:$src1, IntRegs:$src2, CtrRegs:$src3, s4Imm:$offset),
2154            "$dst2 = memd($src1++#$offset:circ($src3))",
2155            [],
2156            "$src1 = $dst">;
2157
2158 /********************************************************************
2159 *            ALU32/PERM                                             *
2160 *********************************************************************/
2161
2162 // ALU32 / PERM / Combine.
2163 def HEXAGON_A2_combinew:
2164   di_ALU32_sisi                   <"combine",  int_hexagon_A2_combinew>;
2165 def HEXAGON_A2_combine_hh:
2166   si_MInst_sisi_hh                <"combine",  int_hexagon_A2_combine_hh>;
2167 def HEXAGON_A2_combine_lh:
2168   si_MInst_sisi_lh                <"combine",  int_hexagon_A2_combine_lh>;
2169 def HEXAGON_A2_combine_hl:
2170   si_MInst_sisi_hl                <"combine",  int_hexagon_A2_combine_hl>;
2171 def HEXAGON_A2_combine_ll:
2172   si_MInst_sisi_ll                <"combine",  int_hexagon_A2_combine_ll>;
2173 def HEXAGON_A2_combineii:
2174   di_MInst_s8s8                   <"combine",  int_hexagon_A2_combineii>;
2175
2176 // ALU32 / PERM / Mux.
2177 def HEXAGON_C2_mux:
2178   si_ALU32_qisisi                 <"mux",      int_hexagon_C2_mux>;
2179
2180 // ALU32 / PERM / Shift halfword.
2181 def HEXAGON_A2_aslh:
2182   si_ALU32_si                     <"aslh",     int_hexagon_A2_aslh>;
2183 def HEXAGON_A2_asrh:
2184   si_ALU32_si                     <"asrh",     int_hexagon_A2_asrh>;
2185 def SI_to_SXTHI_asrh:
2186   si_ALU32_si                     <"asrh",     int_hexagon_SI_to_SXTHI_asrh>;
2187
2188 // ALU32 / PERM / Sign/zero extend.
2189 def HEXAGON_A2_sxth:
2190   si_ALU32_si                     <"sxth",     int_hexagon_A2_sxth>;
2191 def HEXAGON_A2_sxtb:
2192   si_ALU32_si                     <"sxtb",     int_hexagon_A2_sxtb>;
2193 def HEXAGON_A2_zxth:
2194   si_ALU32_si                     <"zxth",     int_hexagon_A2_zxth>;
2195 def HEXAGON_A2_zxtb:
2196   si_ALU32_si                     <"zxtb",     int_hexagon_A2_zxtb>;
2197
2198 /********************************************************************
2199 *            ALU32/PRED                                             *
2200 *********************************************************************/
2201
2202 // ALU32 / PRED / Compare.
2203 def HEXAGON_C2_cmpeq:
2204   qi_ALU32_sisi                   <"cmp.eq",   int_hexagon_C2_cmpeq>;
2205 def HEXAGON_C2_cmpeqi:
2206   qi_ALU32_sis10                  <"cmp.eq",   int_hexagon_C2_cmpeqi>;
2207 def HEXAGON_C2_cmpgei:
2208   qi_ALU32_sis8                   <"cmp.ge",   int_hexagon_C2_cmpgei>;
2209 def HEXAGON_C2_cmpgeui:
2210   qi_ALU32_siu8                   <"cmp.geu",  int_hexagon_C2_cmpgeui>;
2211 def HEXAGON_C2_cmpgt:
2212   qi_ALU32_sisi                   <"cmp.gt",   int_hexagon_C2_cmpgt>;
2213 def HEXAGON_C2_cmpgti:
2214   qi_ALU32_sis10                  <"cmp.gt",   int_hexagon_C2_cmpgti>;
2215 def HEXAGON_C2_cmpgtu:
2216   qi_ALU32_sisi                   <"cmp.gtu",  int_hexagon_C2_cmpgtu>;
2217 def HEXAGON_C2_cmpgtui:
2218   qi_ALU32_siu9                   <"cmp.gtu",  int_hexagon_C2_cmpgtui>;
2219 def HEXAGON_C2_cmplt:
2220   qi_ALU32_sisi                   <"cmp.lt",   int_hexagon_C2_cmplt>;
2221 def HEXAGON_C2_cmpltu:
2222   qi_ALU32_sisi                   <"cmp.ltu",  int_hexagon_C2_cmpltu>;
2223
2224 /********************************************************************
2225 *            ALU32/VH                                               *
2226 *********************************************************************/
2227
2228 // ALU32 / VH / Vector add halfwords.
2229 // Rd32=vadd[u]h(Rs32,Rt32:sat]
2230 def HEXAGON_A2_svaddh:
2231   si_ALU32_sisi                   <"vaddh",    int_hexagon_A2_svaddh>;
2232 def HEXAGON_A2_svaddhs:
2233   si_ALU32_sisi_sat               <"vaddh",    int_hexagon_A2_svaddhs>;
2234 def HEXAGON_A2_svadduhs:
2235   si_ALU32_sisi_sat               <"vadduh",   int_hexagon_A2_svadduhs>;
2236
2237 // ALU32 / VH / Vector average halfwords.
2238 def HEXAGON_A2_svavgh:
2239   si_ALU32_sisi                   <"vavgh",    int_hexagon_A2_svavgh>;
2240 def HEXAGON_A2_svavghs:
2241   si_ALU32_sisi_rnd               <"vavgh",    int_hexagon_A2_svavghs>;
2242 def HEXAGON_A2_svnavgh:
2243   si_ALU32_sisi                   <"vnavgh",   int_hexagon_A2_svnavgh>;
2244
2245 // ALU32 / VH / Vector subtract halfwords.
2246 def HEXAGON_A2_svsubh:
2247   si_ALU32_sisi                   <"vsubh",    int_hexagon_A2_svsubh>;
2248 def HEXAGON_A2_svsubhs:
2249   si_ALU32_sisi_sat               <"vsubh",    int_hexagon_A2_svsubhs>;
2250 def HEXAGON_A2_svsubuhs:
2251   si_ALU32_sisi_sat               <"vsubuh",   int_hexagon_A2_svsubuhs>;
2252
2253 /********************************************************************
2254 *            ALU64/ALU                                              *
2255 *********************************************************************/
2256
2257 // ALU64 / ALU / Add.
2258 def HEXAGON_A2_addp:
2259   di_ALU64_didi                   <"add",      int_hexagon_A2_addp>;
2260 def HEXAGON_A2_addsat:
2261   si_ALU64_sisi_sat               <"add",      int_hexagon_A2_addsat>;
2262
2263 // ALU64 / ALU / Add halfword.
2264 // Even though the definition says hl, it should be lh -
2265 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2266 def HEXAGON_A2_addh_l16_hl:
2267   si_ALU64_sisi_l16_lh            <"add",      int_hexagon_A2_addh_l16_hl>;
2268 def HEXAGON_A2_addh_l16_ll:
2269   si_ALU64_sisi_l16_ll            <"add",      int_hexagon_A2_addh_l16_ll>;
2270
2271 def HEXAGON_A2_addh_l16_sat_hl:
2272   si_ALU64_sisi_l16_sat_lh        <"add",      int_hexagon_A2_addh_l16_sat_hl>;
2273 def HEXAGON_A2_addh_l16_sat_ll:
2274   si_ALU64_sisi_l16_sat_ll        <"add",      int_hexagon_A2_addh_l16_sat_ll>;
2275
2276 def HEXAGON_A2_addh_h16_hh:
2277   si_ALU64_sisi_h16_hh            <"add",      int_hexagon_A2_addh_h16_hh>;
2278 def HEXAGON_A2_addh_h16_hl:
2279   si_ALU64_sisi_h16_hl            <"add",      int_hexagon_A2_addh_h16_hl>;
2280 def HEXAGON_A2_addh_h16_lh:
2281   si_ALU64_sisi_h16_lh            <"add",      int_hexagon_A2_addh_h16_lh>;
2282 def HEXAGON_A2_addh_h16_ll:
2283   si_ALU64_sisi_h16_ll            <"add",      int_hexagon_A2_addh_h16_ll>;
2284
2285 def HEXAGON_A2_addh_h16_sat_hh:
2286   si_ALU64_sisi_h16_sat_hh        <"add",      int_hexagon_A2_addh_h16_sat_hh>;
2287 def HEXAGON_A2_addh_h16_sat_hl:
2288   si_ALU64_sisi_h16_sat_hl        <"add",      int_hexagon_A2_addh_h16_sat_hl>;
2289 def HEXAGON_A2_addh_h16_sat_lh:
2290   si_ALU64_sisi_h16_sat_lh        <"add",      int_hexagon_A2_addh_h16_sat_lh>;
2291 def HEXAGON_A2_addh_h16_sat_ll:
2292   si_ALU64_sisi_h16_sat_ll        <"add",      int_hexagon_A2_addh_h16_sat_ll>;
2293
2294 // ALU64 / ALU / Compare.
2295 def HEXAGON_C2_cmpeqp:
2296   qi_ALU64_didi                   <"cmp.eq",   int_hexagon_C2_cmpeqp>;
2297 def HEXAGON_C2_cmpgtp:
2298   qi_ALU64_didi                   <"cmp.gt",   int_hexagon_C2_cmpgtp>;
2299 def HEXAGON_C2_cmpgtup:
2300   qi_ALU64_didi                   <"cmp.gtu",  int_hexagon_C2_cmpgtup>;
2301
2302 // ALU64 / ALU / Logical operations.
2303 def HEXAGON_A2_andp:
2304   di_ALU64_didi                   <"and",      int_hexagon_A2_andp>;
2305 def HEXAGON_A2_orp:
2306   di_ALU64_didi                   <"or",       int_hexagon_A2_orp>;
2307 def HEXAGON_A2_xorp:
2308   di_ALU64_didi                   <"xor",      int_hexagon_A2_xorp>;
2309
2310 // ALU64 / ALU / Maximum.
2311 def HEXAGON_A2_max:
2312   si_ALU64_sisi                   <"max",      int_hexagon_A2_max>;
2313 def HEXAGON_A2_maxu:
2314   si_ALU64_sisi                   <"maxu",     int_hexagon_A2_maxu>;
2315
2316 // ALU64 / ALU / Minimum.
2317 def HEXAGON_A2_min:
2318   si_ALU64_sisi                   <"min",      int_hexagon_A2_min>;
2319 def HEXAGON_A2_minu:
2320   si_ALU64_sisi                   <"minu",     int_hexagon_A2_minu>;
2321
2322 // ALU64 / ALU / Subtract.
2323 def HEXAGON_A2_subp:
2324   di_ALU64_didi                   <"sub",      int_hexagon_A2_subp>;
2325 def HEXAGON_A2_subsat:
2326   si_ALU64_sisi_sat               <"sub",      int_hexagon_A2_subsat>;
2327
2328 // ALU64 / ALU / Subtract halfword.
2329 // Even though the definition says hl, it should be lh -
2330 //so DON'T change the class " si_ALU64_sisi_l16_lh " it inherits.
2331 def HEXAGON_A2_subh_l16_hl:
2332   si_ALU64_sisi_l16_lh            <"sub",      int_hexagon_A2_subh_l16_hl>;
2333 def HEXAGON_A2_subh_l16_ll:
2334   si_ALU64_sisi_l16_ll            <"sub",      int_hexagon_A2_subh_l16_ll>;
2335
2336 def HEXAGON_A2_subh_l16_sat_hl:
2337   si_ALU64_sisi_l16_sat_lh        <"sub",      int_hexagon_A2_subh_l16_sat_hl>;
2338 def HEXAGON_A2_subh_l16_sat_ll:
2339   si_ALU64_sisi_l16_sat_ll        <"sub",      int_hexagon_A2_subh_l16_sat_ll>;
2340
2341 def HEXAGON_A2_subh_h16_hh:
2342   si_ALU64_sisi_h16_hh            <"sub",      int_hexagon_A2_subh_h16_hh>;
2343 def HEXAGON_A2_subh_h16_hl:
2344   si_ALU64_sisi_h16_hl            <"sub",      int_hexagon_A2_subh_h16_hl>;
2345 def HEXAGON_A2_subh_h16_lh:
2346   si_ALU64_sisi_h16_lh            <"sub",      int_hexagon_A2_subh_h16_lh>;
2347 def HEXAGON_A2_subh_h16_ll:
2348   si_ALU64_sisi_h16_ll            <"sub",      int_hexagon_A2_subh_h16_ll>;
2349
2350 def HEXAGON_A2_subh_h16_sat_hh:
2351   si_ALU64_sisi_h16_sat_hh        <"sub",      int_hexagon_A2_subh_h16_sat_hh>;
2352 def HEXAGON_A2_subh_h16_sat_hl:
2353   si_ALU64_sisi_h16_sat_hl        <"sub",      int_hexagon_A2_subh_h16_sat_hl>;
2354 def HEXAGON_A2_subh_h16_sat_lh:
2355   si_ALU64_sisi_h16_sat_lh        <"sub",      int_hexagon_A2_subh_h16_sat_lh>;
2356 def HEXAGON_A2_subh_h16_sat_ll:
2357   si_ALU64_sisi_h16_sat_ll        <"sub",      int_hexagon_A2_subh_h16_sat_ll>;
2358
2359 // ALU64 / ALU / Transfer register.
2360 def HEXAGON_A2_tfrp:
2361   di_ALU64_di                     <"",         int_hexagon_A2_tfrp>;
2362
2363 /********************************************************************
2364 *            ALU64/BIT                                              *
2365 *********************************************************************/
2366
2367 // ALU64 / BIT / Masked parity.
2368 def HEXAGON_S2_parityp:
2369   si_ALU64_didi                   <"parity",   int_hexagon_S2_parityp>;
2370
2371 /********************************************************************
2372 *            ALU64/PERM                                             *
2373 *********************************************************************/
2374
2375 // ALU64 / PERM / Vector pack high and low halfwords.
2376 def HEXAGON_S2_packhl:
2377   di_ALU64_sisi                   <"packhl",   int_hexagon_S2_packhl>;
2378
2379 /********************************************************************
2380 *            ALU64/VB                                               *
2381 *********************************************************************/
2382
2383 // ALU64 / VB / Vector add unsigned bytes.
2384 def HEXAGON_A2_vaddub:
2385   di_ALU64_didi                   <"vaddub",   int_hexagon_A2_vaddub>;
2386 def HEXAGON_A2_vaddubs:
2387   di_ALU64_didi_sat               <"vaddub",   int_hexagon_A2_vaddubs>;
2388
2389 // ALU64 / VB / Vector average unsigned bytes.
2390 def HEXAGON_A2_vavgub:
2391   di_ALU64_didi                   <"vavgub",   int_hexagon_A2_vavgub>;
2392 def HEXAGON_A2_vavgubr:
2393   di_ALU64_didi_rnd               <"vavgub",   int_hexagon_A2_vavgubr>;
2394
2395 // ALU64 / VB / Vector compare unsigned bytes.
2396 def HEXAGON_A2_vcmpbeq:
2397   qi_ALU64_didi                   <"vcmpb.eq", int_hexagon_A2_vcmpbeq>;
2398 def HEXAGON_A2_vcmpbgtu:
2399   qi_ALU64_didi                   <"vcmpb.gtu",int_hexagon_A2_vcmpbgtu>;
2400
2401 // ALU64 / VB / Vector maximum/minimum unsigned bytes.
2402 def HEXAGON_A2_vmaxub:
2403   di_ALU64_didi                   <"vmaxub",   int_hexagon_A2_vmaxub>;
2404 def HEXAGON_A2_vminub:
2405   di_ALU64_didi                   <"vminub",   int_hexagon_A2_vminub>;
2406
2407 // ALU64 / VB / Vector subtract unsigned bytes.
2408 def HEXAGON_A2_vsubub:
2409   di_ALU64_didi                   <"vsubub",   int_hexagon_A2_vsubub>;
2410 def HEXAGON_A2_vsububs:
2411   di_ALU64_didi_sat               <"vsubub",   int_hexagon_A2_vsububs>;
2412
2413 // ALU64 / VB / Vector mux.
2414 def HEXAGON_C2_vmux:
2415   di_ALU64_qididi                 <"vmux",     int_hexagon_C2_vmux>;
2416
2417
2418 /********************************************************************
2419 *            ALU64/VH                                               *
2420 *********************************************************************/
2421
2422 // ALU64 / VH / Vector add halfwords.
2423 // Rdd64=vadd[u]h(Rss64,Rtt64:sat]
2424 def HEXAGON_A2_vaddh:
2425   di_ALU64_didi                   <"vaddh",    int_hexagon_A2_vaddh>;
2426 def HEXAGON_A2_vaddhs:
2427   di_ALU64_didi_sat               <"vaddh",    int_hexagon_A2_vaddhs>;
2428 def HEXAGON_A2_vadduhs:
2429   di_ALU64_didi_sat               <"vadduh",   int_hexagon_A2_vadduhs>;
2430
2431 // ALU64 / VH / Vector average halfwords.
2432 // Rdd64=v[n]avg[u]h(Rss64,Rtt64:rnd/:crnd][:sat]
2433 def HEXAGON_A2_vavgh:
2434   di_ALU64_didi                   <"vavgh",    int_hexagon_A2_vavgh>;
2435 def HEXAGON_A2_vavghcr:
2436   di_ALU64_didi_crnd              <"vavgh",    int_hexagon_A2_vavghcr>;
2437 def HEXAGON_A2_vavghr:
2438   di_ALU64_didi_rnd               <"vavgh",    int_hexagon_A2_vavghr>;
2439 def HEXAGON_A2_vavguh:
2440   di_ALU64_didi                   <"vavguh",   int_hexagon_A2_vavguh>;
2441 def HEXAGON_A2_vavguhr:
2442   di_ALU64_didi_rnd               <"vavguh",   int_hexagon_A2_vavguhr>;
2443 def HEXAGON_A2_vnavgh:
2444   di_ALU64_didi                   <"vnavgh",   int_hexagon_A2_vnavgh>;
2445 def HEXAGON_A2_vnavghcr:
2446   di_ALU64_didi_crnd_sat          <"vnavgh",   int_hexagon_A2_vnavghcr>;
2447 def HEXAGON_A2_vnavghr:
2448   di_ALU64_didi_rnd_sat           <"vnavgh",   int_hexagon_A2_vnavghr>;
2449
2450 // ALU64 / VH / Vector compare halfwords.
2451 def HEXAGON_A2_vcmpheq:
2452   qi_ALU64_didi                   <"vcmph.eq", int_hexagon_A2_vcmpheq>;
2453 def HEXAGON_A2_vcmphgt:
2454   qi_ALU64_didi                   <"vcmph.gt", int_hexagon_A2_vcmphgt>;
2455 def HEXAGON_A2_vcmphgtu:
2456   qi_ALU64_didi                   <"vcmph.gtu",int_hexagon_A2_vcmphgtu>;
2457
2458 // ALU64 / VH / Vector maximum halfwords.
2459 def HEXAGON_A2_vmaxh:
2460   di_ALU64_didi                   <"vmaxh",    int_hexagon_A2_vmaxh>;
2461 def HEXAGON_A2_vmaxuh:
2462   di_ALU64_didi                   <"vmaxuh",   int_hexagon_A2_vmaxuh>;
2463
2464 // ALU64 / VH / Vector minimum halfwords.
2465 def HEXAGON_A2_vminh:
2466   di_ALU64_didi                   <"vminh",    int_hexagon_A2_vminh>;
2467 def HEXAGON_A2_vminuh:
2468   di_ALU64_didi                   <"vminuh",   int_hexagon_A2_vminuh>;
2469
2470 // ALU64 / VH / Vector subtract halfwords.
2471 def HEXAGON_A2_vsubh:
2472   di_ALU64_didi                   <"vsubh",    int_hexagon_A2_vsubh>;
2473 def HEXAGON_A2_vsubhs:
2474   di_ALU64_didi_sat               <"vsubh",    int_hexagon_A2_vsubhs>;
2475 def HEXAGON_A2_vsubuhs:
2476   di_ALU64_didi_sat               <"vsubuh",   int_hexagon_A2_vsubuhs>;
2477
2478
2479 /********************************************************************
2480 *            ALU64/VW                                               *
2481 *********************************************************************/
2482
2483 // ALU64 / VW / Vector add words.
2484 // Rdd32=vaddw(Rss32,Rtt32)[:sat]
2485 def HEXAGON_A2_vaddw:
2486   di_ALU64_didi                   <"vaddw",    int_hexagon_A2_vaddw>;
2487 def HEXAGON_A2_vaddws:
2488   di_ALU64_didi_sat               <"vaddw",   int_hexagon_A2_vaddws>;
2489
2490 // ALU64 / VW / Vector average words.
2491 def HEXAGON_A2_vavguw:
2492   di_ALU64_didi                   <"vavguw",   int_hexagon_A2_vavguw>;
2493 def HEXAGON_A2_vavguwr:
2494   di_ALU64_didi_rnd               <"vavguw",   int_hexagon_A2_vavguwr>;
2495 def HEXAGON_A2_vavgw:
2496   di_ALU64_didi                   <"vavgw",    int_hexagon_A2_vavgw>;
2497 def HEXAGON_A2_vavgwcr:
2498   di_ALU64_didi_crnd              <"vavgw",    int_hexagon_A2_vavgwcr>;
2499 def HEXAGON_A2_vavgwr:
2500   di_ALU64_didi_rnd               <"vavgw",    int_hexagon_A2_vavgwr>;
2501 def HEXAGON_A2_vnavgw:
2502   di_ALU64_didi                   <"vnavgw",   int_hexagon_A2_vnavgw>;
2503 def HEXAGON_A2_vnavgwcr:
2504   di_ALU64_didi_crnd_sat          <"vnavgw",   int_hexagon_A2_vnavgwcr>;
2505 def HEXAGON_A2_vnavgwr:
2506   di_ALU64_didi_rnd_sat           <"vnavgw",   int_hexagon_A2_vnavgwr>;
2507
2508 // ALU64 / VW / Vector compare words.
2509 def HEXAGON_A2_vcmpweq:
2510   qi_ALU64_didi                   <"vcmpw.eq", int_hexagon_A2_vcmpweq>;
2511 def HEXAGON_A2_vcmpwgt:
2512   qi_ALU64_didi                   <"vcmpw.gt", int_hexagon_A2_vcmpwgt>;
2513 def HEXAGON_A2_vcmpwgtu:
2514   qi_ALU64_didi                   <"vcmpw.gtu",int_hexagon_A2_vcmpwgtu>;
2515
2516 // ALU64 / VW / Vector maximum words.
2517 def HEXAGON_A2_vmaxw:
2518   di_ALU64_didi                   <"vmaxw",    int_hexagon_A2_vmaxw>;
2519 def HEXAGON_A2_vmaxuw:
2520   di_ALU64_didi                   <"vmaxuw",   int_hexagon_A2_vmaxuw>;
2521
2522 // ALU64 / VW / Vector minimum words.
2523 def HEXAGON_A2_vminw:
2524   di_ALU64_didi                   <"vminw",    int_hexagon_A2_vminw>;
2525 def HEXAGON_A2_vminuw:
2526   di_ALU64_didi                   <"vminuw",   int_hexagon_A2_vminuw>;
2527
2528 // ALU64 / VW / Vector subtract words.
2529 def HEXAGON_A2_vsubw:
2530   di_ALU64_didi                   <"vsubw",    int_hexagon_A2_vsubw>;
2531 def HEXAGON_A2_vsubws:
2532   di_ALU64_didi_sat               <"vsubw",    int_hexagon_A2_vsubws>;
2533
2534
2535 /********************************************************************
2536 *            CR                                                     *
2537 *********************************************************************/
2538
2539 // CR / Logical reductions on predicates.
2540 def HEXAGON_C2_all8:
2541   qi_SInst_qi                     <"all8",     int_hexagon_C2_all8>;
2542 def HEXAGON_C2_any8:
2543   qi_SInst_qi                     <"any8",     int_hexagon_C2_any8>;
2544
2545 // CR / Logical operations on predicates.
2546 def HEXAGON_C2_pxfer_map:
2547   qi_SInst_qi_pxfer               <"",         int_hexagon_C2_pxfer_map>;
2548 def HEXAGON_C2_and:
2549   qi_SInst_qiqi                   <"and",      int_hexagon_C2_and>;
2550 def HEXAGON_C2_andn:
2551   qi_SInst_qiqi_neg               <"and",      int_hexagon_C2_andn>;
2552 def HEXAGON_C2_not:
2553   qi_SInst_qi                     <"not",      int_hexagon_C2_not>;
2554 def HEXAGON_C2_or:
2555   qi_SInst_qiqi                   <"or",       int_hexagon_C2_or>;
2556 def HEXAGON_C2_orn:
2557   qi_SInst_qiqi_neg               <"or",       int_hexagon_C2_orn>;
2558 def HEXAGON_C2_xor:
2559   qi_SInst_qiqi                   <"xor",      int_hexagon_C2_xor>;
2560
2561
2562 /********************************************************************
2563 *            MTYPE/ALU                                              *
2564 *********************************************************************/
2565
2566 // MTYPE / ALU / Add and accumulate.
2567 def HEXAGON_M2_acci:
2568   si_MInst_sisisi_acc             <"add",      int_hexagon_M2_acci>;
2569 def HEXAGON_M2_accii:
2570   si_MInst_sisis8_acc             <"add",      int_hexagon_M2_accii>;
2571 def HEXAGON_M2_nacci:
2572   si_MInst_sisisi_nac             <"add",      int_hexagon_M2_nacci>;
2573 def HEXAGON_M2_naccii:
2574   si_MInst_sisis8_nac             <"add",      int_hexagon_M2_naccii>;
2575
2576 // MTYPE / ALU / Subtract and accumulate.
2577 def HEXAGON_M2_subacc:
2578   si_MInst_sisisi_acc             <"sub",      int_hexagon_M2_subacc>;
2579
2580 // MTYPE / ALU / Vector absolute difference.
2581 def HEXAGON_M2_vabsdiffh:
2582   di_MInst_didi                   <"vabsdiffh",int_hexagon_M2_vabsdiffh>;
2583 def HEXAGON_M2_vabsdiffw:
2584   di_MInst_didi                   <"vabsdiffw",int_hexagon_M2_vabsdiffw>;
2585
2586 // MTYPE / ALU / XOR and xor with destination.
2587 def HEXAGON_M2_xor_xacc:
2588   si_MInst_sisisi_xacc            <"xor",      int_hexagon_M2_xor_xacc>;
2589
2590
2591 /********************************************************************
2592 *            MTYPE/COMPLEX                                          *
2593 *********************************************************************/
2594
2595 // MTYPE / COMPLEX / Complex multiply.
2596 // Rdd[-+]=cmpy(Rs, Rt:<<1]:sat
2597 def HEXAGON_M2_cmpys_s1:
2598   di_MInst_sisi_s1_sat            <"cmpy",     int_hexagon_M2_cmpys_s1>;
2599 def HEXAGON_M2_cmpys_s0:
2600   di_MInst_sisi_sat               <"cmpy",     int_hexagon_M2_cmpys_s0>;
2601 def HEXAGON_M2_cmpysc_s1:
2602   di_MInst_sisi_s1_sat_conj       <"cmpy",     int_hexagon_M2_cmpysc_s1>;
2603 def HEXAGON_M2_cmpysc_s0:
2604   di_MInst_sisi_sat_conj          <"cmpy",     int_hexagon_M2_cmpysc_s0>;
2605
2606 def HEXAGON_M2_cmacs_s1:
2607   di_MInst_disisi_acc_s1_sat      <"cmpy",     int_hexagon_M2_cmacs_s1>;
2608 def HEXAGON_M2_cmacs_s0:
2609   di_MInst_disisi_acc_sat         <"cmpy",     int_hexagon_M2_cmacs_s0>;
2610 def HEXAGON_M2_cmacsc_s1:
2611   di_MInst_disisi_acc_s1_sat_conj <"cmpy",     int_hexagon_M2_cmacsc_s1>;
2612 def HEXAGON_M2_cmacsc_s0:
2613   di_MInst_disisi_acc_sat_conj    <"cmpy",     int_hexagon_M2_cmacsc_s0>;
2614
2615 def HEXAGON_M2_cnacs_s1:
2616   di_MInst_disisi_nac_s1_sat      <"cmpy",     int_hexagon_M2_cnacs_s1>;
2617 def HEXAGON_M2_cnacs_s0:
2618   di_MInst_disisi_nac_sat         <"cmpy",     int_hexagon_M2_cnacs_s0>;
2619 def HEXAGON_M2_cnacsc_s1:
2620   di_MInst_disisi_nac_s1_sat_conj <"cmpy",     int_hexagon_M2_cnacsc_s1>;
2621 def HEXAGON_M2_cnacsc_s0:
2622   di_MInst_disisi_nac_sat_conj    <"cmpy",     int_hexagon_M2_cnacsc_s0>;
2623
2624 // MTYPE / COMPLEX / Complex multiply real or imaginary.
2625 def HEXAGON_M2_cmpyr_s0:
2626   di_MInst_sisi                   <"cmpyr",    int_hexagon_M2_cmpyr_s0>;
2627 def HEXAGON_M2_cmacr_s0:
2628   di_MInst_disisi_acc             <"cmpyr",    int_hexagon_M2_cmacr_s0>;
2629
2630 def HEXAGON_M2_cmpyi_s0:
2631   di_MInst_sisi                   <"cmpyi",    int_hexagon_M2_cmpyi_s0>;
2632 def HEXAGON_M2_cmaci_s0:
2633   di_MInst_disisi_acc             <"cmpyi",    int_hexagon_M2_cmaci_s0>;
2634
2635 // MTYPE / COMPLEX / Complex multiply with round and pack.
2636 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
2637 def HEXAGON_M2_cmpyrs_s0:
2638   si_MInst_sisi_rnd_sat           <"cmpy",     int_hexagon_M2_cmpyrs_s0>;
2639 def HEXAGON_M2_cmpyrs_s1:
2640   si_MInst_sisi_s1_rnd_sat        <"cmpy",     int_hexagon_M2_cmpyrs_s1>;
2641
2642 def HEXAGON_M2_cmpyrsc_s0:
2643   si_MInst_sisi_rnd_sat_conj      <"cmpy",     int_hexagon_M2_cmpyrsc_s0>;
2644 def HEXAGON_M2_cmpyrsc_s1:
2645   si_MInst_sisi_s1_rnd_sat_conj   <"cmpy",     int_hexagon_M2_cmpyrsc_s1>;
2646
2647 //MTYPE / COMPLEX / Vector complex multiply real or imaginary.
2648 def HEXAGON_M2_vcmpy_s0_sat_i:
2649   di_MInst_didi_sat               <"vcmpyi",   int_hexagon_M2_vcmpy_s0_sat_i>;
2650 def HEXAGON_M2_vcmpy_s1_sat_i:
2651   di_MInst_didi_s1_sat            <"vcmpyi",   int_hexagon_M2_vcmpy_s1_sat_i>;
2652
2653 def HEXAGON_M2_vcmpy_s0_sat_r:
2654   di_MInst_didi_sat               <"vcmpyr",   int_hexagon_M2_vcmpy_s0_sat_r>;
2655 def HEXAGON_M2_vcmpy_s1_sat_r:
2656   di_MInst_didi_s1_sat            <"vcmpyr",   int_hexagon_M2_vcmpy_s1_sat_r>;
2657
2658 def HEXAGON_M2_vcmac_s0_sat_i:
2659   di_MInst_dididi_acc_sat         <"vcmpyi",   int_hexagon_M2_vcmac_s0_sat_i>;
2660 def HEXAGON_M2_vcmac_s0_sat_r:
2661   di_MInst_dididi_acc_sat         <"vcmpyr",   int_hexagon_M2_vcmac_s0_sat_r>;
2662
2663 //MTYPE / COMPLEX / Vector reduce complex multiply real or imaginary.
2664 def HEXAGON_M2_vrcmpyi_s0:
2665   di_MInst_didi                   <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0>;
2666 def HEXAGON_M2_vrcmpyr_s0:
2667   di_MInst_didi                   <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0>;
2668
2669 def HEXAGON_M2_vrcmpyi_s0c:
2670   di_MInst_didi_conj              <"vrcmpyi",  int_hexagon_M2_vrcmpyi_s0c>;
2671 def HEXAGON_M2_vrcmpyr_s0c:
2672   di_MInst_didi_conj              <"vrcmpyr",  int_hexagon_M2_vrcmpyr_s0c>;
2673
2674 def HEXAGON_M2_vrcmaci_s0:
2675   di_MInst_dididi_acc             <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0>;
2676 def HEXAGON_M2_vrcmacr_s0:
2677   di_MInst_dididi_acc             <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0>;
2678
2679 def HEXAGON_M2_vrcmaci_s0c:
2680   di_MInst_dididi_acc_conj        <"vrcmpyi",  int_hexagon_M2_vrcmaci_s0c>;
2681 def HEXAGON_M2_vrcmacr_s0c:
2682   di_MInst_dididi_acc_conj        <"vrcmpyr",  int_hexagon_M2_vrcmacr_s0c>;
2683
2684
2685 /********************************************************************
2686 *            MTYPE/MPYH                                             *
2687 *********************************************************************/
2688
2689 // MTYPE / MPYH / Multiply and use lower result.
2690 //def HEXAGON_M2_mpysmi:
2691 //FIXME: Hexagon_M2_mpysmi should really by of the type si_MInst_sim9,
2692 // not si_MInst_sis9 - but for now, we will use s9.
2693 // def Hexagon_M2_mpysmi:
2694 //  si_MInst_sim9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2695 def Hexagon_M2_mpysmi:
2696   si_MInst_sis9                   <"mpyi",     int_hexagon_M2_mpysmi>;
2697 def HEXAGON_M2_mpyi:
2698   si_MInst_sisi                   <"mpyi",     int_hexagon_M2_mpyi>;
2699 def HEXAGON_M2_mpyui:
2700   si_MInst_sisi                   <"mpyui",    int_hexagon_M2_mpyui>;
2701 def HEXAGON_M2_macsip:
2702   si_MInst_sisiu8_acc             <"mpyi",     int_hexagon_M2_macsip>;
2703 def HEXAGON_M2_maci:
2704   si_MInst_sisisi_acc             <"mpyi",     int_hexagon_M2_maci>;
2705 def HEXAGON_M2_macsin:
2706   si_MInst_sisiu8_nac             <"mpyi",     int_hexagon_M2_macsin>;
2707
2708 // MTYPE / MPYH / Multiply word by half (32x16).
2709 //Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat]
2710 //Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat]
2711 def HEXAGON_M2_mmpyl_rs1:
2712   di_MInst_didi_s1_rnd_sat        <"vmpyweh",  int_hexagon_M2_mmpyl_rs1>;
2713 def HEXAGON_M2_mmpyl_s1:
2714   di_MInst_didi_s1_sat            <"vmpyweh",  int_hexagon_M2_mmpyl_s1>;
2715 def HEXAGON_M2_mmpyl_rs0:
2716   di_MInst_didi_rnd_sat           <"vmpyweh",  int_hexagon_M2_mmpyl_rs0>;
2717 def HEXAGON_M2_mmpyl_s0:
2718   di_MInst_didi_sat               <"vmpyweh",  int_hexagon_M2_mmpyl_s0>;
2719 def HEXAGON_M2_mmpyh_rs1:
2720   di_MInst_didi_s1_rnd_sat        <"vmpywoh",  int_hexagon_M2_mmpyh_rs1>;
2721 def HEXAGON_M2_mmpyh_s1:
2722   di_MInst_didi_s1_sat            <"vmpywoh",  int_hexagon_M2_mmpyh_s1>;
2723 def HEXAGON_M2_mmpyh_rs0:
2724   di_MInst_didi_rnd_sat           <"vmpywoh",  int_hexagon_M2_mmpyh_rs0>;
2725 def HEXAGON_M2_mmpyh_s0:
2726   di_MInst_didi_sat               <"vmpywoh",  int_hexagon_M2_mmpyh_s0>;
2727 def HEXAGON_M2_mmacls_rs1:
2728   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweh",  int_hexagon_M2_mmacls_rs1>;
2729 def HEXAGON_M2_mmacls_s1:
2730   di_MInst_dididi_acc_s1_sat      <"vmpyweh",  int_hexagon_M2_mmacls_s1>;
2731 def HEXAGON_M2_mmacls_rs0:
2732   di_MInst_dididi_acc_rnd_sat     <"vmpyweh",  int_hexagon_M2_mmacls_rs0>;
2733 def HEXAGON_M2_mmacls_s0:
2734   di_MInst_dididi_acc_sat         <"vmpyweh",  int_hexagon_M2_mmacls_s0>;
2735 def HEXAGON_M2_mmachs_rs1:
2736   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywoh",  int_hexagon_M2_mmachs_rs1>;
2737 def HEXAGON_M2_mmachs_s1:
2738   di_MInst_dididi_acc_s1_sat      <"vmpywoh",  int_hexagon_M2_mmachs_s1>;
2739 def HEXAGON_M2_mmachs_rs0:
2740   di_MInst_dididi_acc_rnd_sat     <"vmpywoh",  int_hexagon_M2_mmachs_rs0>;
2741 def HEXAGON_M2_mmachs_s0:
2742   di_MInst_dididi_acc_sat         <"vmpywoh",  int_hexagon_M2_mmachs_s0>;
2743
2744 // MTYPE / MPYH / Multiply word by unsigned half (32x16).
2745 //Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat]
2746 //Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat]
2747 def HEXAGON_M2_mmpyul_rs1:
2748   di_MInst_didi_s1_rnd_sat        <"vmpyweuh", int_hexagon_M2_mmpyul_rs1>;
2749 def HEXAGON_M2_mmpyul_s1:
2750   di_MInst_didi_s1_sat            <"vmpyweuh", int_hexagon_M2_mmpyul_s1>;
2751 def HEXAGON_M2_mmpyul_rs0:
2752   di_MInst_didi_rnd_sat           <"vmpyweuh", int_hexagon_M2_mmpyul_rs0>;
2753 def HEXAGON_M2_mmpyul_s0:
2754   di_MInst_didi_sat               <"vmpyweuh", int_hexagon_M2_mmpyul_s0>;
2755 def HEXAGON_M2_mmpyuh_rs1:
2756   di_MInst_didi_s1_rnd_sat        <"vmpywouh", int_hexagon_M2_mmpyuh_rs1>;
2757 def HEXAGON_M2_mmpyuh_s1:
2758   di_MInst_didi_s1_sat            <"vmpywouh", int_hexagon_M2_mmpyuh_s1>;
2759 def HEXAGON_M2_mmpyuh_rs0:
2760   di_MInst_didi_rnd_sat           <"vmpywouh", int_hexagon_M2_mmpyuh_rs0>;
2761 def HEXAGON_M2_mmpyuh_s0:
2762   di_MInst_didi_sat               <"vmpywouh", int_hexagon_M2_mmpyuh_s0>;
2763 def HEXAGON_M2_mmaculs_rs1:
2764   di_MInst_dididi_acc_s1_rnd_sat  <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>;
2765 def HEXAGON_M2_mmaculs_s1:
2766   di_MInst_dididi_acc_s1_sat      <"vmpyweuh", int_hexagon_M2_mmaculs_s1>;
2767 def HEXAGON_M2_mmaculs_rs0:
2768   di_MInst_dididi_acc_rnd_sat     <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>;
2769 def HEXAGON_M2_mmaculs_s0:
2770   di_MInst_dididi_acc_sat         <"vmpyweuh", int_hexagon_M2_mmaculs_s0>;
2771 def HEXAGON_M2_mmacuhs_rs1:
2772   di_MInst_dididi_acc_s1_rnd_sat  <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>;
2773 def HEXAGON_M2_mmacuhs_s1:
2774   di_MInst_dididi_acc_s1_sat      <"vmpywouh", int_hexagon_M2_mmacuhs_s1>;
2775 def HEXAGON_M2_mmacuhs_rs0:
2776   di_MInst_dididi_acc_rnd_sat     <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>;
2777 def HEXAGON_M2_mmacuhs_s0:
2778   di_MInst_dididi_acc_sat         <"vmpywouh", int_hexagon_M2_mmacuhs_s0>;
2779
2780 // MTYPE / MPYH / Multiply and use upper result.
2781 def HEXAGON_M2_hmmpyh_rs1:
2782   si_MInst_sisi_h_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyh_rs1>;
2783 def HEXAGON_M2_hmmpyl_rs1:
2784   si_MInst_sisi_l_s1_rnd_sat      <"mpy",      int_hexagon_M2_hmmpyl_rs1>;
2785 def HEXAGON_M2_mpy_up:
2786   si_MInst_sisi                   <"mpy",      int_hexagon_M2_mpy_up>;
2787 def HEXAGON_M2_dpmpyss_rnd_s0:
2788   si_MInst_sisi_rnd               <"mpy",      int_hexagon_M2_dpmpyss_rnd_s0>;
2789 def HEXAGON_M2_mpyu_up:
2790   si_MInst_sisi                   <"mpyu",     int_hexagon_M2_mpyu_up>;
2791
2792 // MTYPE / MPYH / Multiply and use full result.
2793 def HEXAGON_M2_dpmpyuu_s0:
2794   di_MInst_sisi                   <"mpyu",     int_hexagon_M2_dpmpyuu_s0>;
2795 def HEXAGON_M2_dpmpyuu_acc_s0:
2796   di_MInst_disisi_acc             <"mpyu",     int_hexagon_M2_dpmpyuu_acc_s0>;
2797 def HEXAGON_M2_dpmpyuu_nac_s0:
2798   di_MInst_disisi_nac             <"mpyu",     int_hexagon_M2_dpmpyuu_nac_s0>;
2799 def HEXAGON_M2_dpmpyss_s0:
2800   di_MInst_sisi                   <"mpy",      int_hexagon_M2_dpmpyss_s0>;
2801 def HEXAGON_M2_dpmpyss_acc_s0:
2802   di_MInst_disisi_acc             <"mpy",      int_hexagon_M2_dpmpyss_acc_s0>;
2803 def HEXAGON_M2_dpmpyss_nac_s0:
2804   di_MInst_disisi_nac             <"mpy",      int_hexagon_M2_dpmpyss_nac_s0>;
2805
2806 /********************************************************************
2807 *            MTYPE/VB                                               *
2808 *********************************************************************/
2809
2810 // MTYPE / VB / Vector reduce add unsigned bytes.
2811 def HEXAGON_A2_vraddub:
2812   di_MInst_didi                   <"vraddub", int_hexagon_A2_vraddub>;
2813 def HEXAGON_A2_vraddub_acc:
2814   di_MInst_dididi_acc             <"vraddub", int_hexagon_A2_vraddub_acc>;
2815
2816 // MTYPE / VB / Vector sum of absolute differences unsigned bytes.
2817 def HEXAGON_A2_vrsadub:
2818   di_MInst_didi                   <"vrsadub", int_hexagon_A2_vrsadub>;
2819 def HEXAGON_A2_vrsadub_acc:
2820   di_MInst_dididi_acc             <"vrsadub", int_hexagon_A2_vrsadub_acc>;
2821
2822 /********************************************************************
2823 *            MTYPE/VH                                               *
2824 *********************************************************************/
2825
2826 // MTYPE / VH / Vector dual multiply.
2827 def HEXAGON_M2_vdmpys_s1:
2828   di_MInst_didi_s1_sat            <"vdmpy",   int_hexagon_M2_vdmpys_s1>;
2829 def HEXAGON_M2_vdmpys_s0:
2830   di_MInst_didi_sat               <"vdmpy",   int_hexagon_M2_vdmpys_s0>;
2831 def HEXAGON_M2_vdmacs_s1:
2832   di_MInst_dididi_acc_s1_sat      <"vdmpy",   int_hexagon_M2_vdmacs_s1>;
2833 def HEXAGON_M2_vdmacs_s0:
2834   di_MInst_dididi_acc_sat         <"vdmpy",   int_hexagon_M2_vdmacs_s0>;
2835
2836 // MTYPE / VH / Vector dual multiply with round and pack.
2837 def HEXAGON_M2_vdmpyrs_s0:
2838   si_MInst_didi_rnd_sat           <"vdmpy",   int_hexagon_M2_vdmpyrs_s0>;
2839 def HEXAGON_M2_vdmpyrs_s1:
2840   si_MInst_didi_s1_rnd_sat        <"vdmpy",   int_hexagon_M2_vdmpyrs_s1>;
2841
2842 // MTYPE / VH / Vector multiply even halfwords.
2843 def HEXAGON_M2_vmpy2es_s1:
2844   di_MInst_didi_s1_sat            <"vmpyeh",  int_hexagon_M2_vmpy2es_s1>;
2845 def HEXAGON_M2_vmpy2es_s0:
2846   di_MInst_didi_sat               <"vmpyeh",  int_hexagon_M2_vmpy2es_s0>;
2847 def HEXAGON_M2_vmac2es:
2848   di_MInst_dididi_acc             <"vmpyeh",  int_hexagon_M2_vmac2es>;
2849 def HEXAGON_M2_vmac2es_s1:
2850   di_MInst_dididi_acc_s1_sat      <"vmpyeh",  int_hexagon_M2_vmac2es_s1>;
2851 def HEXAGON_M2_vmac2es_s0:
2852   di_MInst_dididi_acc_sat         <"vmpyeh",  int_hexagon_M2_vmac2es_s0>;
2853
2854 // MTYPE / VH / Vector multiply halfwords.
2855 def HEXAGON_M2_vmpy2s_s0:
2856   di_MInst_sisi_sat               <"vmpyh",   int_hexagon_M2_vmpy2s_s0>;
2857 def HEXAGON_M2_vmpy2s_s1:
2858   di_MInst_sisi_s1_sat            <"vmpyh",   int_hexagon_M2_vmpy2s_s1>;
2859 def HEXAGON_M2_vmac2:
2860   di_MInst_disisi_acc             <"vmpyh",   int_hexagon_M2_vmac2>;
2861 def HEXAGON_M2_vmac2s_s0:
2862   di_MInst_disisi_acc_sat         <"vmpyh",   int_hexagon_M2_vmac2s_s0>;
2863 def HEXAGON_M2_vmac2s_s1:
2864   di_MInst_disisi_acc_s1_sat      <"vmpyh",   int_hexagon_M2_vmac2s_s1>;
2865
2866 // MTYPE / VH / Vector multiply halfwords with round and pack.
2867 def HEXAGON_M2_vmpy2s_s0pack:
2868   si_MInst_sisi_rnd_sat           <"vmpyh",   int_hexagon_M2_vmpy2s_s0pack>;
2869 def HEXAGON_M2_vmpy2s_s1pack:
2870   si_MInst_sisi_s1_rnd_sat        <"vmpyh",   int_hexagon_M2_vmpy2s_s1pack>;
2871
2872 // MTYPE / VH / Vector reduce multiply halfwords.
2873 // Rxx32+=vrmpyh(Rss32,Rtt32)
2874 def HEXAGON_M2_vrmpy_s0:
2875   di_MInst_didi                   <"vrmpyh",  int_hexagon_M2_vrmpy_s0>;
2876 def HEXAGON_M2_vrmac_s0:
2877   di_MInst_dididi_acc             <"vrmpyh",  int_hexagon_M2_vrmac_s0>;
2878
2879
2880 /********************************************************************
2881 *            STYPE/ALU                                              *
2882 *********************************************************************/
2883
2884 // STYPE / ALU / Absolute value.
2885 def HEXAGON_A2_abs:
2886   si_SInst_si                     <"abs",     int_hexagon_A2_abs>;
2887 def HEXAGON_A2_absp:
2888   di_SInst_di                     <"abs",     int_hexagon_A2_absp>;
2889 def HEXAGON_A2_abssat:
2890   si_SInst_si_sat                 <"abs",     int_hexagon_A2_abssat>;
2891
2892 // STYPE / ALU / Logical Not.
2893 def HEXAGON_A2_notp:
2894   di_SInst_di                     <"not",     int_hexagon_A2_notp>;
2895
2896 // STYPE / ALU / Sign extend word to doubleword.
2897 def HEXAGON_A2_sxtw:
2898   di_SInst_si                     <"sxtw",     int_hexagon_A2_sxtw>;
2899
2900
2901 /********************************************************************
2902 *            STYPE/BIT                                              *
2903 *********************************************************************/
2904
2905 // STYPE / BIT / Count leading.
2906 def HEXAGON_S2_cl0:
2907   si_SInst_si                     <"cl0",     int_hexagon_S2_cl0>;
2908 def HEXAGON_S2_cl0p:
2909   si_SInst_di                     <"cl0",     int_hexagon_S2_cl0p>;
2910 def HEXAGON_S2_cl1:
2911   si_SInst_si                     <"cl1",     int_hexagon_S2_cl1>;
2912 def HEXAGON_S2_cl1p:
2913   si_SInst_di                     <"cl1",     int_hexagon_S2_cl1p>;
2914 def HEXAGON_S2_clb:
2915   si_SInst_si                     <"clb",     int_hexagon_S2_clb>;
2916 def HEXAGON_S2_clbp:
2917   si_SInst_di                     <"clb",     int_hexagon_S2_clbp>;
2918 def HEXAGON_S2_clbnorm:
2919   si_SInst_si                     <"normamt", int_hexagon_S2_clbnorm>;
2920
2921 // STYPE / BIT / Count trailing.
2922 def HEXAGON_S2_ct0:
2923   si_SInst_si                     <"ct0",     int_hexagon_S2_ct0>;
2924 def HEXAGON_S2_ct1:
2925   si_SInst_si                     <"ct1",     int_hexagon_S2_ct1>;
2926
2927 // STYPE / BIT / Compare bit mask.
2928 def Hexagon_C2_bitsclr:
2929   qi_SInst_sisi                   <"bitsclr", int_hexagon_C2_bitsclr>;
2930 def Hexagon_C2_bitsclri:
2931   qi_SInst_siu6                   <"bitsclr", int_hexagon_C2_bitsclri>;
2932 def Hexagon_C2_bitsset:
2933   qi_SInst_sisi                   <"bitsset", int_hexagon_C2_bitsset>;
2934
2935 // STYPE / BIT / Extract unsigned.
2936 // Rd[d][32/64]=extractu(Rs[s],Rt[t],[imm])
2937 def HEXAGON_S2_extractu:
2938   si_SInst_siu5u5                 <"extractu",int_hexagon_S2_extractu>;
2939 def HEXAGON_S2_extractu_rp:
2940   si_SInst_sidi                   <"extractu",int_hexagon_S2_extractu_rp>;
2941 def HEXAGON_S2_extractup:
2942   di_SInst_diu6u6                 <"extractu",int_hexagon_S2_extractup>;
2943 def HEXAGON_S2_extractup_rp:
2944   di_SInst_didi                   <"extractu",int_hexagon_S2_extractup_rp>;
2945
2946 // STYPE / BIT / Insert bitfield.
2947 def Hexagon_S2_insert:
2948   si_SInst_sisiu5u5               <"insert",  int_hexagon_S2_insert>;
2949 def Hexagon_S2_insert_rp:
2950   si_SInst_sisidi                 <"insert",  int_hexagon_S2_insert_rp>;
2951 def Hexagon_S2_insertp:
2952   di_SInst_didiu6u6               <"insert",  int_hexagon_S2_insertp>;
2953 def Hexagon_S2_insertp_rp:
2954   di_SInst_dididi                 <"insert",  int_hexagon_S2_insertp_rp>;
2955
2956 // STYPE / BIT / Innterleave/deinterleave.
2957 def Hexagon_S2_interleave:
2958   di_SInst_di                     <"interleave", int_hexagon_S2_interleave>;
2959 def Hexagon_S2_deinterleave:
2960   di_SInst_di                     <"deinterleave", int_hexagon_S2_deinterleave>;
2961
2962 // STYPE / BIT / Linear feedback-shift Iteration.
2963 def Hexagon_S2_lfsp:
2964   di_SInst_didi                   <"lfs",     int_hexagon_S2_lfsp>;
2965
2966 // STYPE / BIT / Bit reverse.
2967 def Hexagon_S2_brev:
2968   si_SInst_si                     <"brev",    int_hexagon_S2_brev>;
2969
2970 // STYPE / BIT / Set/Clear/Toggle Bit.
2971 def HEXAGON_S2_setbit_i:
2972   si_SInst_siu5                   <"setbit",  int_hexagon_S2_setbit_i>;
2973 def HEXAGON_S2_togglebit_i:
2974   si_SInst_siu5                   <"togglebit", int_hexagon_S2_togglebit_i>;
2975 def HEXAGON_S2_clrbit_i:
2976   si_SInst_siu5                   <"clrbit",  int_hexagon_S2_clrbit_i>;
2977 def HEXAGON_S2_setbit_r:
2978   si_SInst_sisi                   <"setbit",  int_hexagon_S2_setbit_r>;
2979 def HEXAGON_S2_togglebit_r:
2980   si_SInst_sisi                   <"togglebit", int_hexagon_S2_togglebit_r>;
2981 def HEXAGON_S2_clrbit_r:
2982   si_SInst_sisi                   <"clrbit",  int_hexagon_S2_clrbit_r>;
2983
2984 // STYPE / BIT / Test Bit.
2985 def HEXAGON_S2_tstbit_i:
2986   qi_SInst_siu5                   <"tstbit",  int_hexagon_S2_tstbit_i>;
2987 def HEXAGON_S2_tstbit_r:
2988   qi_SInst_sisi                   <"tstbit",  int_hexagon_S2_tstbit_r>;
2989
2990
2991 /********************************************************************
2992 *            STYPE/COMPLEX                                          *
2993 *********************************************************************/
2994
2995 // STYPE / COMPLEX / Vector Complex conjugate.
2996 def HEXAGON_A2_vconj:
2997   di_SInst_di_sat                 <"vconj",   int_hexagon_A2_vconj>;
2998
2999 // STYPE / COMPLEX / Vector Complex rotate.
3000 def HEXAGON_S2_vcrotate:
3001   di_SInst_disi                   <"vcrotate",int_hexagon_S2_vcrotate>;
3002
3003
3004 /********************************************************************
3005 *            STYPE/PERM                                             *
3006 *********************************************************************/
3007
3008 // STYPE / PERM / Saturate.
3009 def HEXAGON_A2_sat:
3010   si_SInst_di                     <"sat",     int_hexagon_A2_sat>;
3011 def HEXAGON_A2_satb:
3012   si_SInst_si                     <"satb",    int_hexagon_A2_satb>;
3013 def HEXAGON_A2_sath:
3014   si_SInst_si                     <"sath",    int_hexagon_A2_sath>;
3015 def HEXAGON_A2_satub:
3016   si_SInst_si                     <"satub",   int_hexagon_A2_satub>;
3017 def HEXAGON_A2_satuh:
3018   si_SInst_si                     <"satuh",   int_hexagon_A2_satuh>;
3019
3020 // STYPE / PERM / Swizzle bytes.
3021 def HEXAGON_A2_swiz:
3022   si_SInst_si                     <"swiz",    int_hexagon_A2_swiz>;
3023
3024 // STYPE / PERM / Vector align.
3025 // Need custom lowering
3026 def HEXAGON_S2_valignib:
3027   di_SInst_didiu3                 <"valignb", int_hexagon_S2_valignib>;
3028 def HEXAGON_S2_valignrb:
3029   di_SInst_didiqi                 <"valignb", int_hexagon_S2_valignrb>;
3030
3031 // STYPE / PERM / Vector round and pack.
3032 def HEXAGON_S2_vrndpackwh:
3033   si_SInst_di                     <"vrndwh",  int_hexagon_S2_vrndpackwh>;
3034 def HEXAGON_S2_vrndpackwhs:
3035   si_SInst_di_sat                 <"vrndwh",  int_hexagon_S2_vrndpackwhs>;
3036
3037 // STYPE / PERM / Vector saturate and pack.
3038 def HEXAGON_S2_svsathb:
3039   si_SInst_si                     <"vsathb",  int_hexagon_S2_svsathb>;
3040 def HEXAGON_S2_vsathb:
3041   si_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb>;
3042 def HEXAGON_S2_svsathub:
3043   si_SInst_si                     <"vsathub", int_hexagon_S2_svsathub>;
3044 def HEXAGON_S2_vsathub:
3045   si_SInst_di                     <"vsathub", int_hexagon_S2_vsathub>;
3046 def HEXAGON_S2_vsatwh:
3047   si_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh>;
3048 def HEXAGON_S2_vsatwuh:
3049   si_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh>;
3050
3051 // STYPE / PERM / Vector saturate without pack.
3052 def HEXAGON_S2_vsathb_nopack:
3053   di_SInst_di                     <"vsathb",  int_hexagon_S2_vsathb_nopack>;
3054 def HEXAGON_S2_vsathub_nopack:
3055   di_SInst_di                     <"vsathub", int_hexagon_S2_vsathub_nopack>;
3056 def HEXAGON_S2_vsatwh_nopack:
3057   di_SInst_di                     <"vsatwh",  int_hexagon_S2_vsatwh_nopack>;
3058 def HEXAGON_S2_vsatwuh_nopack:
3059   di_SInst_di                     <"vsatwuh", int_hexagon_S2_vsatwuh_nopack>;
3060
3061 // STYPE / PERM / Vector shuffle.
3062 def HEXAGON_S2_shuffeb:
3063   di_SInst_didi                   <"shuffeb", int_hexagon_S2_shuffeb>;
3064 def HEXAGON_S2_shuffeh:
3065   di_SInst_didi                   <"shuffeh", int_hexagon_S2_shuffeh>;
3066 def HEXAGON_S2_shuffob:
3067   di_SInst_didi                   <"shuffob", int_hexagon_S2_shuffob>;
3068 def HEXAGON_S2_shuffoh:
3069   di_SInst_didi                   <"shuffoh", int_hexagon_S2_shuffoh>;
3070
3071 // STYPE / PERM / Vector splat bytes.
3072 def HEXAGON_S2_vsplatrb:
3073   si_SInst_si                     <"vsplatb", int_hexagon_S2_vsplatrb>;
3074
3075 // STYPE / PERM / Vector splat halfwords.
3076 def HEXAGON_S2_vsplatrh:
3077   di_SInst_si                     <"vsplath", int_hexagon_S2_vsplatrh>;
3078
3079 // STYPE / PERM / Vector splice.
3080 def Hexagon_S2_vsplicerb:
3081   di_SInst_didiqi                 <"vspliceb",int_hexagon_S2_vsplicerb>;
3082 def Hexagon_S2_vspliceib:
3083   di_SInst_didiu3                 <"vspliceb",int_hexagon_S2_vspliceib>;
3084
3085 // STYPE / PERM / Sign extend.
3086 def HEXAGON_S2_vsxtbh:
3087   di_SInst_si                     <"vsxtbh",  int_hexagon_S2_vsxtbh>;
3088 def HEXAGON_S2_vsxthw:
3089   di_SInst_si                     <"vsxthw",  int_hexagon_S2_vsxthw>;
3090
3091 // STYPE / PERM / Truncate.
3092 def HEXAGON_S2_vtrunehb:
3093   si_SInst_di                     <"vtrunehb",int_hexagon_S2_vtrunehb>;
3094 def HEXAGON_S2_vtrunohb:
3095   si_SInst_di                     <"vtrunohb",int_hexagon_S2_vtrunohb>;
3096 def HEXAGON_S2_vtrunewh:
3097   di_SInst_didi                   <"vtrunewh",int_hexagon_S2_vtrunewh>;
3098 def HEXAGON_S2_vtrunowh:
3099   di_SInst_didi                   <"vtrunowh",int_hexagon_S2_vtrunowh>;
3100
3101 // STYPE / PERM / Zero extend.
3102 def HEXAGON_S2_vzxtbh:
3103   di_SInst_si                     <"vzxtbh",  int_hexagon_S2_vzxtbh>;
3104 def HEXAGON_S2_vzxthw:
3105   di_SInst_si                     <"vzxthw",  int_hexagon_S2_vzxthw>;
3106
3107
3108 /********************************************************************
3109 *            STYPE/PRED                                             *
3110 *********************************************************************/
3111
3112 // STYPE / PRED / Mask generate from predicate.
3113 def HEXAGON_C2_mask:
3114   di_SInst_qi                     <"mask",   int_hexagon_C2_mask>;
3115
3116 // STYPE / PRED / Predicate transfer.
3117 def HEXAGON_C2_tfrpr:
3118   si_SInst_qi                     <"",       int_hexagon_C2_tfrpr>;
3119 def HEXAGON_C2_tfrrp:
3120   qi_SInst_si                     <"",       int_hexagon_C2_tfrrp>;
3121
3122 // STYPE / PRED / Viterbi pack even and odd predicate bits.
3123 def HEXAGON_C2_vitpack:
3124   si_SInst_qiqi                   <"vitpack",int_hexagon_C2_vitpack>;
3125
3126
3127 /********************************************************************
3128 *            STYPE/SHIFT                                            *
3129 *********************************************************************/
3130
3131 // STYPE / SHIFT / Shift by immediate.
3132 def HEXAGON_S2_asl_i_r:
3133   si_SInst_siu5                   <"asl",     int_hexagon_S2_asl_i_r>;
3134 def HEXAGON_S2_asr_i_r:
3135   si_SInst_siu5                   <"asr",     int_hexagon_S2_asr_i_r>;
3136 def HEXAGON_S2_lsr_i_r:
3137   si_SInst_siu5                   <"lsr",     int_hexagon_S2_lsr_i_r>;
3138 def HEXAGON_S2_asl_i_p:
3139   di_SInst_diu6                   <"asl",     int_hexagon_S2_asl_i_p>;
3140 def HEXAGON_S2_asr_i_p:
3141   di_SInst_diu6                   <"asr",     int_hexagon_S2_asr_i_p>;
3142 def HEXAGON_S2_lsr_i_p:
3143   di_SInst_diu6                   <"lsr",     int_hexagon_S2_lsr_i_p>;
3144
3145 // STYPE / SHIFT / Shift by immediate and accumulate.
3146 def HEXAGON_S2_asl_i_r_acc:
3147   si_SInst_sisiu5_acc             <"asl",     int_hexagon_S2_asl_i_r_acc>;
3148 def HEXAGON_S2_asr_i_r_acc:
3149   si_SInst_sisiu5_acc             <"asr",     int_hexagon_S2_asr_i_r_acc>;
3150 def HEXAGON_S2_lsr_i_r_acc:
3151   si_SInst_sisiu5_acc             <"lsr",     int_hexagon_S2_lsr_i_r_acc>;
3152 def HEXAGON_S2_asl_i_r_nac:
3153   si_SInst_sisiu5_nac             <"asl",     int_hexagon_S2_asl_i_r_nac>;
3154 def HEXAGON_S2_asr_i_r_nac:
3155   si_SInst_sisiu5_nac             <"asr",     int_hexagon_S2_asr_i_r_nac>;
3156 def HEXAGON_S2_lsr_i_r_nac:
3157   si_SInst_sisiu5_nac             <"lsr",     int_hexagon_S2_lsr_i_r_nac>;
3158 def HEXAGON_S2_asl_i_p_acc:
3159   di_SInst_didiu6_acc             <"asl",     int_hexagon_S2_asl_i_p_acc>;
3160 def HEXAGON_S2_asr_i_p_acc:
3161   di_SInst_didiu6_acc             <"asr",     int_hexagon_S2_asr_i_p_acc>;
3162 def HEXAGON_S2_lsr_i_p_acc:
3163   di_SInst_didiu6_acc             <"lsr",     int_hexagon_S2_lsr_i_p_acc>;
3164 def HEXAGON_S2_asl_i_p_nac:
3165   di_SInst_didiu6_nac             <"asl",     int_hexagon_S2_asl_i_p_nac>;
3166 def HEXAGON_S2_asr_i_p_nac:
3167   di_SInst_didiu6_nac             <"asr",     int_hexagon_S2_asr_i_p_nac>;
3168 def HEXAGON_S2_lsr_i_p_nac:
3169   di_SInst_didiu6_nac             <"lsr",     int_hexagon_S2_lsr_i_p_nac>;
3170
3171 // STYPE / SHIFT / Shift by immediate and add.
3172 def HEXAGON_S2_addasl_rrri:
3173   si_SInst_sisiu3                 <"addasl",  int_hexagon_S2_addasl_rrri>;
3174
3175 // STYPE / SHIFT / Shift by immediate and logical.
3176 def HEXAGON_S2_asl_i_r_and:
3177   si_SInst_sisiu5_and             <"asl",     int_hexagon_S2_asl_i_r_and>;
3178 def HEXAGON_S2_asr_i_r_and:
3179   si_SInst_sisiu5_and             <"asr",     int_hexagon_S2_asr_i_r_and>;
3180 def HEXAGON_S2_lsr_i_r_and:
3181   si_SInst_sisiu5_and             <"lsr",     int_hexagon_S2_lsr_i_r_and>;
3182
3183 def HEXAGON_S2_asl_i_r_xacc:
3184   si_SInst_sisiu5_xor             <"asl",     int_hexagon_S2_asl_i_r_xacc>;
3185 def HEXAGON_S2_lsr_i_r_xacc:
3186   si_SInst_sisiu5_xor             <"lsr",     int_hexagon_S2_lsr_i_r_xacc>;
3187
3188 def HEXAGON_S2_asl_i_r_or:
3189   si_SInst_sisiu5_or              <"asl",     int_hexagon_S2_asl_i_r_or>;
3190 def HEXAGON_S2_asr_i_r_or:
3191   si_SInst_sisiu5_or              <"asr",     int_hexagon_S2_asr_i_r_or>;
3192 def HEXAGON_S2_lsr_i_r_or:
3193   si_SInst_sisiu5_or              <"lsr",     int_hexagon_S2_lsr_i_r_or>;
3194
3195 def HEXAGON_S2_asl_i_p_and:
3196   di_SInst_didiu6_and             <"asl",     int_hexagon_S2_asl_i_p_and>;
3197 def HEXAGON_S2_asr_i_p_and:
3198   di_SInst_didiu6_and             <"asr",     int_hexagon_S2_asr_i_p_and>;
3199 def HEXAGON_S2_lsr_i_p_and:
3200   di_SInst_didiu6_and             <"lsr",     int_hexagon_S2_lsr_i_p_and>;
3201
3202 def HEXAGON_S2_asl_i_p_xacc:
3203   di_SInst_didiu6_xor             <"asl",     int_hexagon_S2_asl_i_p_xacc>;
3204 def HEXAGON_S2_lsr_i_p_xacc:
3205   di_SInst_didiu6_xor             <"lsr",     int_hexagon_S2_lsr_i_p_xacc>;
3206
3207 def HEXAGON_S2_asl_i_p_or:
3208   di_SInst_didiu6_or              <"asl",     int_hexagon_S2_asl_i_p_or>;
3209 def HEXAGON_S2_asr_i_p_or:
3210   di_SInst_didiu6_or              <"asr",     int_hexagon_S2_asr_i_p_or>;
3211 def HEXAGON_S2_lsr_i_p_or:
3212   di_SInst_didiu6_or              <"lsr",     int_hexagon_S2_lsr_i_p_or>;
3213
3214 // STYPE / SHIFT / Shift right by immediate with rounding.
3215 def HEXAGON_S2_asr_i_r_rnd:
3216   si_SInst_siu5_rnd               <"asr",     int_hexagon_S2_asr_i_r_rnd>;
3217 def HEXAGON_S2_asr_i_r_rnd_goodsyntax:
3218   si_SInst_siu5              <"asrrnd",  int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
3219
3220 // STYPE / SHIFT / Shift left by immediate with saturation.
3221 def HEXAGON_S2_asl_i_r_sat:
3222   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_i_r_sat>;
3223
3224 // STYPE / SHIFT / Shift by register.
3225 def HEXAGON_S2_asl_r_r:
3226   si_SInst_sisi                   <"asl",     int_hexagon_S2_asl_r_r>;
3227 def HEXAGON_S2_asr_r_r:
3228   si_SInst_sisi                   <"asr",     int_hexagon_S2_asr_r_r>;
3229 def HEXAGON_S2_lsl_r_r:
3230   si_SInst_sisi                   <"lsl",     int_hexagon_S2_lsl_r_r>;
3231 def HEXAGON_S2_lsr_r_r:
3232   si_SInst_sisi                   <"lsr",     int_hexagon_S2_lsr_r_r>;
3233 def HEXAGON_S2_asl_r_p:
3234   di_SInst_disi                   <"asl",     int_hexagon_S2_asl_r_p>;
3235 def HEXAGON_S2_asr_r_p:
3236   di_SInst_disi                   <"asr",     int_hexagon_S2_asr_r_p>;
3237 def HEXAGON_S2_lsl_r_p:
3238   di_SInst_disi                   <"lsl",     int_hexagon_S2_lsl_r_p>;
3239 def HEXAGON_S2_lsr_r_p:
3240   di_SInst_disi                   <"lsr",     int_hexagon_S2_lsr_r_p>;
3241
3242 // STYPE / SHIFT / Shift by register and accumulate.
3243 def HEXAGON_S2_asl_r_r_acc:
3244   si_SInst_sisisi_acc             <"asl",     int_hexagon_S2_asl_r_r_acc>;
3245 def HEXAGON_S2_asr_r_r_acc:
3246   si_SInst_sisisi_acc             <"asr",     int_hexagon_S2_asr_r_r_acc>;
3247 def HEXAGON_S2_lsl_r_r_acc:
3248   si_SInst_sisisi_acc             <"lsl",     int_hexagon_S2_lsl_r_r_acc>;
3249 def HEXAGON_S2_lsr_r_r_acc:
3250   si_SInst_sisisi_acc             <"lsr",     int_hexagon_S2_lsr_r_r_acc>;
3251 def HEXAGON_S2_asl_r_p_acc:
3252   di_SInst_didisi_acc             <"asl",     int_hexagon_S2_asl_r_p_acc>;
3253 def HEXAGON_S2_asr_r_p_acc:
3254   di_SInst_didisi_acc             <"asr",     int_hexagon_S2_asr_r_p_acc>;
3255 def HEXAGON_S2_lsl_r_p_acc:
3256   di_SInst_didisi_acc             <"lsl",     int_hexagon_S2_lsl_r_p_acc>;
3257 def HEXAGON_S2_lsr_r_p_acc:
3258   di_SInst_didisi_acc             <"lsr",     int_hexagon_S2_lsr_r_p_acc>;
3259
3260 def HEXAGON_S2_asl_r_r_nac:
3261   si_SInst_sisisi_nac             <"asl",     int_hexagon_S2_asl_r_r_nac>;
3262 def HEXAGON_S2_asr_r_r_nac:
3263   si_SInst_sisisi_nac             <"asr",     int_hexagon_S2_asr_r_r_nac>;
3264 def HEXAGON_S2_lsl_r_r_nac:
3265   si_SInst_sisisi_nac             <"lsl",     int_hexagon_S2_lsl_r_r_nac>;
3266 def HEXAGON_S2_lsr_r_r_nac:
3267   si_SInst_sisisi_nac             <"lsr",     int_hexagon_S2_lsr_r_r_nac>;
3268 def HEXAGON_S2_asl_r_p_nac:
3269   di_SInst_didisi_nac             <"asl",     int_hexagon_S2_asl_r_p_nac>;
3270 def HEXAGON_S2_asr_r_p_nac:
3271   di_SInst_didisi_nac             <"asr",     int_hexagon_S2_asr_r_p_nac>;
3272 def HEXAGON_S2_lsl_r_p_nac:
3273   di_SInst_didisi_nac             <"lsl",     int_hexagon_S2_lsl_r_p_nac>;
3274 def HEXAGON_S2_lsr_r_p_nac:
3275   di_SInst_didisi_nac             <"lsr",     int_hexagon_S2_lsr_r_p_nac>;
3276
3277 // STYPE / SHIFT / Shift by register and logical.
3278 def HEXAGON_S2_asl_r_r_and:
3279   si_SInst_sisisi_and             <"asl",     int_hexagon_S2_asl_r_r_and>;
3280 def HEXAGON_S2_asr_r_r_and:
3281   si_SInst_sisisi_and             <"asr",     int_hexagon_S2_asr_r_r_and>;
3282 def HEXAGON_S2_lsl_r_r_and:
3283   si_SInst_sisisi_and             <"lsl",     int_hexagon_S2_lsl_r_r_and>;
3284 def HEXAGON_S2_lsr_r_r_and:
3285   si_SInst_sisisi_and             <"lsr",     int_hexagon_S2_lsr_r_r_and>;
3286
3287 def HEXAGON_S2_asl_r_r_or:
3288   si_SInst_sisisi_or              <"asl",     int_hexagon_S2_asl_r_r_or>;
3289 def HEXAGON_S2_asr_r_r_or:
3290   si_SInst_sisisi_or              <"asr",     int_hexagon_S2_asr_r_r_or>;
3291 def HEXAGON_S2_lsl_r_r_or:
3292   si_SInst_sisisi_or              <"lsl",     int_hexagon_S2_lsl_r_r_or>;
3293 def HEXAGON_S2_lsr_r_r_or:
3294   si_SInst_sisisi_or              <"lsr",     int_hexagon_S2_lsr_r_r_or>;
3295
3296 def HEXAGON_S2_asl_r_p_and:
3297   di_SInst_didisi_and             <"asl",     int_hexagon_S2_asl_r_p_and>;
3298 def HEXAGON_S2_asr_r_p_and:
3299   di_SInst_didisi_and             <"asr",     int_hexagon_S2_asr_r_p_and>;
3300 def HEXAGON_S2_lsl_r_p_and:
3301   di_SInst_didisi_and             <"lsl",     int_hexagon_S2_lsl_r_p_and>;
3302 def HEXAGON_S2_lsr_r_p_and:
3303   di_SInst_didisi_and             <"lsr",     int_hexagon_S2_lsr_r_p_and>;
3304
3305 def HEXAGON_S2_asl_r_p_or:
3306   di_SInst_didisi_or              <"asl",     int_hexagon_S2_asl_r_p_or>;
3307 def HEXAGON_S2_asr_r_p_or:
3308   di_SInst_didisi_or              <"asr",     int_hexagon_S2_asr_r_p_or>;
3309 def HEXAGON_S2_lsl_r_p_or:
3310   di_SInst_didisi_or              <"lsl",     int_hexagon_S2_lsl_r_p_or>;
3311 def HEXAGON_S2_lsr_r_p_or:
3312   di_SInst_didisi_or              <"lsr",     int_hexagon_S2_lsr_r_p_or>;
3313
3314 // STYPE / SHIFT / Shift by register with saturation.
3315 def HEXAGON_S2_asl_r_r_sat:
3316   si_SInst_sisi_sat               <"asl",     int_hexagon_S2_asl_r_r_sat>;
3317 def HEXAGON_S2_asr_r_r_sat:
3318   si_SInst_sisi_sat               <"asr",     int_hexagon_S2_asr_r_r_sat>;
3319
3320 // STYPE / SHIFT / Table Index.
3321 def Hexagon_S2_tableidxb_goodsyntax:
3322   si_MInst_sisiu4u5          <"tableidxb",int_hexagon_S2_tableidxb_goodsyntax>;
3323 def Hexagon_S2_tableidxd_goodsyntax:
3324   si_MInst_sisiu4u5          <"tableidxd",int_hexagon_S2_tableidxd_goodsyntax>;
3325 def Hexagon_S2_tableidxh_goodsyntax:
3326   si_MInst_sisiu4u5          <"tableidxh",int_hexagon_S2_tableidxh_goodsyntax>;
3327 def Hexagon_S2_tableidxw_goodsyntax:
3328   si_MInst_sisiu4u5          <"tableidxw",int_hexagon_S2_tableidxw_goodsyntax>;
3329
3330
3331 /********************************************************************
3332 *            STYPE/VH                                               *
3333 *********************************************************************/
3334
3335 // STYPE / VH / Vector absolute value halfwords.
3336 // Rdd64=vabsh(Rss64)
3337 def HEXAGON_A2_vabsh:
3338   di_SInst_di                     <"vabsh",   int_hexagon_A2_vabsh>;
3339 def HEXAGON_A2_vabshsat:
3340   di_SInst_di_sat                 <"vabsh",   int_hexagon_A2_vabshsat>;
3341
3342 // STYPE / VH / Vector shift halfwords by immediate.
3343 // Rdd64=v[asl/asr/lsr]h(Rss64,Rt32)
3344 def HEXAGON_S2_asl_i_vh:
3345   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_i_vh>;
3346 def HEXAGON_S2_asr_i_vh:
3347   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_i_vh>;
3348 def HEXAGON_S2_lsr_i_vh:
3349   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_i_vh>;
3350
3351 // STYPE / VH / Vector shift halfwords by register.
3352 // Rdd64=v[asl/asr/lsl/lsr]w(Rss64,Rt32)
3353 def HEXAGON_S2_asl_r_vh:
3354   di_SInst_disi                   <"vaslh",   int_hexagon_S2_asl_r_vh>;
3355 def HEXAGON_S2_asr_r_vh:
3356   di_SInst_disi                   <"vasrh",   int_hexagon_S2_asr_r_vh>;
3357 def HEXAGON_S2_lsl_r_vh:
3358   di_SInst_disi                   <"vlslh",   int_hexagon_S2_lsl_r_vh>;
3359 def HEXAGON_S2_lsr_r_vh:
3360   di_SInst_disi                   <"vlsrh",   int_hexagon_S2_lsr_r_vh>;
3361
3362
3363 /********************************************************************
3364 *            STYPE/VW                                               *
3365 *********************************************************************/
3366
3367 // STYPE / VW / Vector absolute value words.
3368 def HEXAGON_A2_vabsw:
3369   di_SInst_di                     <"vabsw",   int_hexagon_A2_vabsw>;
3370 def HEXAGON_A2_vabswsat:
3371   di_SInst_di_sat                 <"vabsw",   int_hexagon_A2_vabswsat>;
3372
3373 // STYPE / VW / Vector shift words by immediate.
3374 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3375 def HEXAGON_S2_asl_i_vw:
3376   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_i_vw>;
3377 def HEXAGON_S2_asr_i_vw:
3378   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_i_vw>;
3379 def HEXAGON_S2_lsr_i_vw:
3380   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_i_vw>;
3381
3382 // STYPE / VW / Vector shift words by register.
3383 // Rdd64=v[asl/vsl]w(Rss64,Rt32)
3384 def HEXAGON_S2_asl_r_vw:
3385   di_SInst_disi                   <"vaslw",   int_hexagon_S2_asl_r_vw>;
3386 def HEXAGON_S2_asr_r_vw:
3387   di_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_vw>;
3388 def HEXAGON_S2_lsl_r_vw:
3389   di_SInst_disi                   <"vlslw",   int_hexagon_S2_lsl_r_vw>;
3390 def HEXAGON_S2_lsr_r_vw:
3391   di_SInst_disi                   <"vlsrw",   int_hexagon_S2_lsr_r_vw>;
3392
3393 // STYPE / VW / Vector shift words with truncate and pack.
3394 def HEXAGON_S2_asr_r_svw_trun:
3395   si_SInst_disi                   <"vasrw",   int_hexagon_S2_asr_r_svw_trun>;
3396 def HEXAGON_S2_asr_i_svw_trun:
3397   si_SInst_diu5                   <"vasrw",   int_hexagon_S2_asr_i_svw_trun>;
3398
3399 // LD / Circular loads.
3400 def HEXAGON_circ_ldd:
3401   di_LDInstPI_diu4                <"circ_ldd", int_hexagon_circ_ldd>;
3402
3403 include "HexagonIntrinsicsV3.td"
3404 include "HexagonIntrinsicsV4.td"
3405 include "HexagonIntrinsicsV5.td"