lib/Target/Hexagon/HexagonIntrinsics.td

   1 //===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 // This is populated based on the following specs:
  10 // Hexagon V2 Architecture
  11 // Application-Level Specification
  12 // 80-V9418-8 Rev. B
  13 // March 4, 2008
  14 //===----------------------------------------------------------------------===//
  15
  16 class T_I_pat <InstHexagon MI, Intrinsic IntID>
  17   : Pat <(IntID imm:$Is),
  18          (MI imm:$Is)>;
  19
  20 class T_R_pat <InstHexagon MI, Intrinsic IntID>
  21   : Pat <(IntID I32:$Rs),
  22          (MI I32:$Rs)>;
  23
  24 class T_P_pat <InstHexagon MI, Intrinsic IntID>
  25   : Pat <(IntID I64:$Rs),
  26          (MI DoubleRegs:$Rs)>;
  27
  28 class T_II_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  29   : Pat<(IntID Imm1:$Is, Imm2:$It),
  30         (MI Imm1:$Is, Imm2:$It)>;
  31
  32 class T_RI_pat <InstHexagon MI, Intrinsic IntID, PatLeaf ImmPred = PatLeaf<(i32 imm)>>
  33   : Pat<(IntID I32:$Rs, ImmPred:$It),
  34         (MI I32:$Rs, ImmPred:$It)>;
  35
  36 class T_IR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred = PatLeaf<(i32 imm)>>
  37   : Pat<(IntID ImmPred:$Is, I32:$Rt),
  38         (MI ImmPred:$Is, I32:$Rt)>;
  39
  40 class T_PI_pat <InstHexagon MI, Intrinsic IntID>
  41   : Pat<(IntID I64:$Rs, imm:$It),
  42         (MI DoubleRegs:$Rs, imm:$It)>;
  43
  44 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
  45   : Pat<(IntID I32:$Rs, I64:$Rt),
  46         (MI I32:$Rs, DoubleRegs:$Rt)>;
  47
  48 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
  49   : Pat <(IntID I32:$Rs, I32:$Rt),
  50          (MI I32:$Rs, I32:$Rt)>;
  51
  52 class T_PP_pat <InstHexagon MI, Intrinsic IntID>
  53   : Pat <(IntID I64:$Rs, I64:$Rt),
  54          (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
  55
  56 class T_QII_pat <InstHexagon MI, Intrinsic IntID, PatFrag Imm1, PatFrag Imm2>
  57   : Pat <(IntID (i32 PredRegs:$Ps), Imm1:$Is, Imm2:$It),
  58          (MI PredRegs:$Ps, Imm1:$Is, Imm2:$It)>;
  59
  60 class T_QRI_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  61   : Pat <(IntID (i32 PredRegs:$Ps), I32:$Rs, ImmPred:$Is),
  62          (MI PredRegs:$Ps, I32:$Rs, ImmPred:$Is)>;
  63
  64 class T_QIR_pat <InstHexagon MI, Intrinsic IntID, PatFrag ImmPred>
  65   : Pat <(IntID (i32 PredRegs:$Ps), ImmPred:$Is, I32:$Rs),
  66          (MI PredRegs:$Ps, ImmPred:$Is, I32:$Rs)>;
  67
  68 class T_RRI_pat <InstHexagon MI, Intrinsic IntID>
  69   : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
  70          (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
  71
  72 class T_RII_pat <InstHexagon MI, Intrinsic IntID>
  73   : Pat <(IntID I32:$Rs, imm:$It, imm:$Iu),
  74          (MI I32:$Rs, imm:$It, imm:$Iu)>;
  75
  76 class T_IRI_pat <InstHexagon MI, Intrinsic IntID>
  77   : Pat <(IntID imm:$It, I32:$Rs, imm:$Iu),
  78          (MI imm:$It, I32:$Rs, imm:$Iu)>;
  79
  80 class T_IRR_pat <InstHexagon MI, Intrinsic IntID>
  81   : Pat <(IntID imm:$Is, I32:$Rs, I32:$Rt),
  82          (MI imm:$Is, I32:$Rs, I32:$Rt)>;
  83
  84 class T_RIR_pat <InstHexagon MI, Intrinsic IntID>
  85   : Pat <(IntID I32:$Rs, imm:$Is, I32:$Rt),
  86          (MI I32:$Rs, imm:$Is, I32:$Rt)>;
  87
  88 class T_RRR_pat <InstHexagon MI, Intrinsic IntID>
  89   : Pat <(IntID I32:$Rs, I32:$Rt, I32:$Ru),
  90          (MI I32:$Rs, I32:$Rt, I32:$Ru)>;
  91
  92 class T_PPI_pat <InstHexagon MI, Intrinsic IntID>
  93   : Pat <(IntID I64:$Rs, I64:$Rt, imm:$Iu),
  94          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, imm:$Iu)>;
  95
  96 class T_PII_pat <InstHexagon MI, Intrinsic IntID>
  97   : Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
  98          (MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
  99
 100 class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
 101   : Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
 102          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
 103
 104 class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
 105   : Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
 106          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
 107
 108 class T_PRR_pat <InstHexagon MI, Intrinsic IntID>
 109   : Pat <(IntID I64:$Rs, I32:$Rt, I32:$Ru),
 110          (MI DoubleRegs:$Rs, I32:$Rt, I32:$Ru)>;
 111
 112 class T_PPQ_pat <InstHexagon MI, Intrinsic IntID>
 113   : Pat <(IntID I64:$Rs, I64:$Rt, (i32 PredRegs:$Ru)),
 114          (MI DoubleRegs:$Rs, DoubleRegs:$Rt, PredRegs:$Ru)>;
 115
 116 class T_PR_pat <InstHexagon MI, Intrinsic IntID>
 117   : Pat <(IntID I64:$Rs, I32:$Rt),
 118          (MI DoubleRegs:$Rs, I32:$Rt)>;
 119
 120 class T_D_pat <InstHexagon MI, Intrinsic IntID>
 121   : Pat<(IntID (F64:$Rs)),
 122         (MI (F64:$Rs))>;
 123
 124 class T_DI_pat <InstHexagon MI, Intrinsic IntID,
 125                 PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 126   : Pat<(IntID F64:$Rs, ImmPred:$It),
 127         (MI F64:$Rs, ImmPred:$It)>;
 128
 129 class T_F_pat <InstHexagon MI, Intrinsic IntID>
 130   : Pat<(IntID F32:$Rs),
 131         (MI F32:$Rs)>;
 132
 133 class T_FI_pat <InstHexagon MI, Intrinsic IntID,
 134                  PatLeaf ImmPred = PatLeaf<(i32 imm)>>
 135   : Pat<(IntID F32:$Rs, ImmPred:$It),
 136         (MI F32:$Rs, ImmPred:$It)>;
 137
 138 class T_FF_pat <InstHexagon MI, Intrinsic IntID>
 139   : Pat<(IntID F32:$Rs, F32:$Rt),
 140         (MI F32:$Rs, F32:$Rt)>;
 141
 142 class T_DD_pat <InstHexagon MI, Intrinsic IntID>
 143   : Pat<(IntID F64:$Rs, F64:$Rt),
 144         (MI F64:$Rs, F64:$Rt)>;
 145
 146 class T_FFF_pat <InstHexagon MI, Intrinsic IntID>
 147   : Pat<(IntID F32:$Rs, F32:$Rt, F32:$Ru),
 148         (MI F32:$Rs, F32:$Rt, F32:$Ru)>;
 149
 150 class T_FFFQ_pat <InstHexagon MI, Intrinsic IntID>
 151   : Pat <(IntID F32:$Rs, F32:$Rt, F32:$Ru, (i32 PredRegs:$Rx)),
 152          (MI F32:$Rs, F32:$Rt, F32:$Ru, PredRegs:$Rx)>;
 153
 154 //===----------------------------------------------------------------------===//
 155 // MPYS / Multipy signed/unsigned halfwords
 156 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
 157 //===----------------------------------------------------------------------===//
 158
 159 def : T_RR_pat <M2_mpy_ll_s1, int_hexagon_M2_mpy_ll_s1>;
 160 def : T_RR_pat <M2_mpy_ll_s0, int_hexagon_M2_mpy_ll_s0>;
 161 def : T_RR_pat <M2_mpy_lh_s1, int_hexagon_M2_mpy_lh_s1>;
 162 def : T_RR_pat <M2_mpy_lh_s0, int_hexagon_M2_mpy_lh_s0>;
 163 def : T_RR_pat <M2_mpy_hl_s1, int_hexagon_M2_mpy_hl_s1>;
 164 def : T_RR_pat <M2_mpy_hl_s0, int_hexagon_M2_mpy_hl_s0>;
 165 def : T_RR_pat <M2_mpy_hh_s1, int_hexagon_M2_mpy_hh_s1>;
 166 def : T_RR_pat <M2_mpy_hh_s0, int_hexagon_M2_mpy_hh_s0>;
 167
 168 def : T_RR_pat <M2_mpyu_ll_s1, int_hexagon_M2_mpyu_ll_s1>;
 169 def : T_RR_pat <M2_mpyu_ll_s0, int_hexagon_M2_mpyu_ll_s0>;
 170 def : T_RR_pat <M2_mpyu_lh_s1, int_hexagon_M2_mpyu_lh_s1>;
 171 def : T_RR_pat <M2_mpyu_lh_s0, int_hexagon_M2_mpyu_lh_s0>;
 172 def : T_RR_pat <M2_mpyu_hl_s1, int_hexagon_M2_mpyu_hl_s1>;
 173 def : T_RR_pat <M2_mpyu_hl_s0, int_hexagon_M2_mpyu_hl_s0>;
 174 def : T_RR_pat <M2_mpyu_hh_s1, int_hexagon_M2_mpyu_hh_s1>;
 175 def : T_RR_pat <M2_mpyu_hh_s0, int_hexagon_M2_mpyu_hh_s0>;
 176
 177 def : T_RR_pat <M2_mpy_sat_ll_s1, int_hexagon_M2_mpy_sat_ll_s1>;
 178 def : T_RR_pat <M2_mpy_sat_ll_s0, int_hexagon_M2_mpy_sat_ll_s0>;
 179 def : T_RR_pat <M2_mpy_sat_lh_s1, int_hexagon_M2_mpy_sat_lh_s1>;
 180 def : T_RR_pat <M2_mpy_sat_lh_s0, int_hexagon_M2_mpy_sat_lh_s0>;
 181 def : T_RR_pat <M2_mpy_sat_hl_s1, int_hexagon_M2_mpy_sat_hl_s1>;
 182 def : T_RR_pat <M2_mpy_sat_hl_s0, int_hexagon_M2_mpy_sat_hl_s0>;
 183 def : T_RR_pat <M2_mpy_sat_hh_s1, int_hexagon_M2_mpy_sat_hh_s1>;
 184 def : T_RR_pat <M2_mpy_sat_hh_s0, int_hexagon_M2_mpy_sat_hh_s0>;
 185
 186 def : T_RR_pat <M2_mpy_rnd_ll_s1, int_hexagon_M2_mpy_rnd_ll_s1>;
 187 def : T_RR_pat <M2_mpy_rnd_ll_s0, int_hexagon_M2_mpy_rnd_ll_s0>;
 188 def : T_RR_pat <M2_mpy_rnd_lh_s1, int_hexagon_M2_mpy_rnd_lh_s1>;
 189 def : T_RR_pat <M2_mpy_rnd_lh_s0, int_hexagon_M2_mpy_rnd_lh_s0>;
 190 def : T_RR_pat <M2_mpy_rnd_hl_s1, int_hexagon_M2_mpy_rnd_hl_s1>;
 191 def : T_RR_pat <M2_mpy_rnd_hl_s0, int_hexagon_M2_mpy_rnd_hl_s0>;
 192 def : T_RR_pat <M2_mpy_rnd_hh_s1, int_hexagon_M2_mpy_rnd_hh_s1>;
 193 def : T_RR_pat <M2_mpy_rnd_hh_s0, int_hexagon_M2_mpy_rnd_hh_s0>;
 194
 195 def : T_RR_pat <M2_mpy_sat_rnd_ll_s1, int_hexagon_M2_mpy_sat_rnd_ll_s1>;
 196 def : T_RR_pat <M2_mpy_sat_rnd_ll_s0, int_hexagon_M2_mpy_sat_rnd_ll_s0>;
 197 def : T_RR_pat <M2_mpy_sat_rnd_lh_s1, int_hexagon_M2_mpy_sat_rnd_lh_s1>;
 198 def : T_RR_pat <M2_mpy_sat_rnd_lh_s0, int_hexagon_M2_mpy_sat_rnd_lh_s0>;
 199 def : T_RR_pat <M2_mpy_sat_rnd_hl_s1, int_hexagon_M2_mpy_sat_rnd_hl_s1>;
 200 def : T_RR_pat <M2_mpy_sat_rnd_hl_s0, int_hexagon_M2_mpy_sat_rnd_hl_s0>;
 201 def : T_RR_pat <M2_mpy_sat_rnd_hh_s1, int_hexagon_M2_mpy_sat_rnd_hh_s1>;
 202 def : T_RR_pat <M2_mpy_sat_rnd_hh_s0, int_hexagon_M2_mpy_sat_rnd_hh_s0>;
 203
 204
 205 //===----------------------------------------------------------------------===//
 206 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 207 // result from the accumulator.
 208 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 209 //===----------------------------------------------------------------------===//
 210
 211 def : T_RRR_pat <M2_mpy_acc_ll_s1, int_hexagon_M2_mpy_acc_ll_s1>;
 212 def : T_RRR_pat <M2_mpy_acc_ll_s0, int_hexagon_M2_mpy_acc_ll_s0>;
 213 def : T_RRR_pat <M2_mpy_acc_lh_s1, int_hexagon_M2_mpy_acc_lh_s1>;
 214 def : T_RRR_pat <M2_mpy_acc_lh_s0, int_hexagon_M2_mpy_acc_lh_s0>;
 215 def : T_RRR_pat <M2_mpy_acc_hl_s1, int_hexagon_M2_mpy_acc_hl_s1>;
 216 def : T_RRR_pat <M2_mpy_acc_hl_s0, int_hexagon_M2_mpy_acc_hl_s0>;
 217 def : T_RRR_pat <M2_mpy_acc_hh_s1, int_hexagon_M2_mpy_acc_hh_s1>;
 218 def : T_RRR_pat <M2_mpy_acc_hh_s0, int_hexagon_M2_mpy_acc_hh_s0>;
 219
 220 def : T_RRR_pat <M2_mpyu_acc_ll_s1, int_hexagon_M2_mpyu_acc_ll_s1>;
 221 def : T_RRR_pat <M2_mpyu_acc_ll_s0, int_hexagon_M2_mpyu_acc_ll_s0>;
 222 def : T_RRR_pat <M2_mpyu_acc_lh_s1, int_hexagon_M2_mpyu_acc_lh_s1>;
 223 def : T_RRR_pat <M2_mpyu_acc_lh_s0, int_hexagon_M2_mpyu_acc_lh_s0>;
 224 def : T_RRR_pat <M2_mpyu_acc_hl_s1, int_hexagon_M2_mpyu_acc_hl_s1>;
 225 def : T_RRR_pat <M2_mpyu_acc_hl_s0, int_hexagon_M2_mpyu_acc_hl_s0>;
 226 def : T_RRR_pat <M2_mpyu_acc_hh_s1, int_hexagon_M2_mpyu_acc_hh_s1>;
 227 def : T_RRR_pat <M2_mpyu_acc_hh_s0, int_hexagon_M2_mpyu_acc_hh_s0>;
 228
 229 def : T_RRR_pat <M2_mpy_nac_ll_s1, int_hexagon_M2_mpy_nac_ll_s1>;
 230 def : T_RRR_pat <M2_mpy_nac_ll_s0, int_hexagon_M2_mpy_nac_ll_s0>;
 231 def : T_RRR_pat <M2_mpy_nac_lh_s1, int_hexagon_M2_mpy_nac_lh_s1>;
 232 def : T_RRR_pat <M2_mpy_nac_lh_s0, int_hexagon_M2_mpy_nac_lh_s0>;
 233 def : T_RRR_pat <M2_mpy_nac_hl_s1, int_hexagon_M2_mpy_nac_hl_s1>;
 234 def : T_RRR_pat <M2_mpy_nac_hl_s0, int_hexagon_M2_mpy_nac_hl_s0>;
 235 def : T_RRR_pat <M2_mpy_nac_hh_s1, int_hexagon_M2_mpy_nac_hh_s1>;
 236 def : T_RRR_pat <M2_mpy_nac_hh_s0, int_hexagon_M2_mpy_nac_hh_s0>;
 237
 238 def : T_RRR_pat <M2_mpyu_nac_ll_s1, int_hexagon_M2_mpyu_nac_ll_s1>;
 239 def : T_RRR_pat <M2_mpyu_nac_ll_s0, int_hexagon_M2_mpyu_nac_ll_s0>;
 240 def : T_RRR_pat <M2_mpyu_nac_lh_s1, int_hexagon_M2_mpyu_nac_lh_s1>;
 241 def : T_RRR_pat <M2_mpyu_nac_lh_s0, int_hexagon_M2_mpyu_nac_lh_s0>;
 242 def : T_RRR_pat <M2_mpyu_nac_hl_s1, int_hexagon_M2_mpyu_nac_hl_s1>;
 243 def : T_RRR_pat <M2_mpyu_nac_hl_s0, int_hexagon_M2_mpyu_nac_hl_s0>;
 244 def : T_RRR_pat <M2_mpyu_nac_hh_s1, int_hexagon_M2_mpyu_nac_hh_s1>;
 245 def : T_RRR_pat <M2_mpyu_nac_hh_s0, int_hexagon_M2_mpyu_nac_hh_s0>;
 246
 247 def : T_RRR_pat <M2_mpy_acc_sat_ll_s1, int_hexagon_M2_mpy_acc_sat_ll_s1>;
 248 def : T_RRR_pat <M2_mpy_acc_sat_ll_s0, int_hexagon_M2_mpy_acc_sat_ll_s0>;
 249 def : T_RRR_pat <M2_mpy_acc_sat_lh_s1, int_hexagon_M2_mpy_acc_sat_lh_s1>;
 250 def : T_RRR_pat <M2_mpy_acc_sat_lh_s0, int_hexagon_M2_mpy_acc_sat_lh_s0>;
 251 def : T_RRR_pat <M2_mpy_acc_sat_hl_s1, int_hexagon_M2_mpy_acc_sat_hl_s1>;
 252 def : T_RRR_pat <M2_mpy_acc_sat_hl_s0, int_hexagon_M2_mpy_acc_sat_hl_s0>;
 253 def : T_RRR_pat <M2_mpy_acc_sat_hh_s1, int_hexagon_M2_mpy_acc_sat_hh_s1>;
 254 def : T_RRR_pat <M2_mpy_acc_sat_hh_s0, int_hexagon_M2_mpy_acc_sat_hh_s0>;
 255
 256 def : T_RRR_pat <M2_mpy_nac_sat_ll_s1, int_hexagon_M2_mpy_nac_sat_ll_s1>;
 257 def : T_RRR_pat <M2_mpy_nac_sat_ll_s0, int_hexagon_M2_mpy_nac_sat_ll_s0>;
 258 def : T_RRR_pat <M2_mpy_nac_sat_lh_s1, int_hexagon_M2_mpy_nac_sat_lh_s1>;
 259 def : T_RRR_pat <M2_mpy_nac_sat_lh_s0, int_hexagon_M2_mpy_nac_sat_lh_s0>;
 260 def : T_RRR_pat <M2_mpy_nac_sat_hl_s1, int_hexagon_M2_mpy_nac_sat_hl_s1>;
 261 def : T_RRR_pat <M2_mpy_nac_sat_hl_s0, int_hexagon_M2_mpy_nac_sat_hl_s0>;
 262 def : T_RRR_pat <M2_mpy_nac_sat_hh_s1, int_hexagon_M2_mpy_nac_sat_hh_s1>;
 263 def : T_RRR_pat <M2_mpy_nac_sat_hh_s0, int_hexagon_M2_mpy_nac_sat_hh_s0>;
 264
 265
 266 //===----------------------------------------------------------------------===//
 267 // Multiply signed/unsigned halfwords with and without saturation and rounding
 268 // into a 64-bits destination register.
 269 //===----------------------------------------------------------------------===//
 270
 271 def : T_RR_pat <M2_mpyd_hh_s0, int_hexagon_M2_mpyd_hh_s0>;
 272 def : T_RR_pat <M2_mpyd_hl_s0, int_hexagon_M2_mpyd_hl_s0>;
 273 def : T_RR_pat <M2_mpyd_lh_s0, int_hexagon_M2_mpyd_lh_s0>;
 274 def : T_RR_pat <M2_mpyd_ll_s0, int_hexagon_M2_mpyd_ll_s0>;
 275 def : T_RR_pat <M2_mpyd_hh_s1, int_hexagon_M2_mpyd_hh_s1>;
 276 def : T_RR_pat <M2_mpyd_hl_s1, int_hexagon_M2_mpyd_hl_s1>;
 277 def : T_RR_pat <M2_mpyd_lh_s1, int_hexagon_M2_mpyd_lh_s1>;
 278 def : T_RR_pat <M2_mpyd_ll_s1, int_hexagon_M2_mpyd_ll_s1>;
 279
 280 def : T_RR_pat <M2_mpyd_rnd_hh_s0, int_hexagon_M2_mpyd_rnd_hh_s0>;
 281 def : T_RR_pat <M2_mpyd_rnd_hl_s0, int_hexagon_M2_mpyd_rnd_hl_s0>;
 282 def : T_RR_pat <M2_mpyd_rnd_lh_s0, int_hexagon_M2_mpyd_rnd_lh_s0>;
 283 def : T_RR_pat <M2_mpyd_rnd_ll_s0, int_hexagon_M2_mpyd_rnd_ll_s0>;
 284 def : T_RR_pat <M2_mpyd_rnd_hh_s1, int_hexagon_M2_mpyd_rnd_hh_s1>;
 285 def : T_RR_pat <M2_mpyd_rnd_hl_s1, int_hexagon_M2_mpyd_rnd_hl_s1>;
 286 def : T_RR_pat <M2_mpyd_rnd_lh_s1, int_hexagon_M2_mpyd_rnd_lh_s1>;
 287 def : T_RR_pat <M2_mpyd_rnd_ll_s1, int_hexagon_M2_mpyd_rnd_ll_s1>;
 288
 289 def : T_RR_pat <M2_mpyud_hh_s0, int_hexagon_M2_mpyud_hh_s0>;
 290 def : T_RR_pat <M2_mpyud_hl_s0, int_hexagon_M2_mpyud_hl_s0>;
 291 def : T_RR_pat <M2_mpyud_lh_s0, int_hexagon_M2_mpyud_lh_s0>;
 292 def : T_RR_pat <M2_mpyud_ll_s0, int_hexagon_M2_mpyud_ll_s0>;
 293 def : T_RR_pat <M2_mpyud_hh_s1, int_hexagon_M2_mpyud_hh_s1>;
 294 def : T_RR_pat <M2_mpyud_hl_s1, int_hexagon_M2_mpyud_hl_s1>;
 295 def : T_RR_pat <M2_mpyud_lh_s1, int_hexagon_M2_mpyud_lh_s1>;
 296 def : T_RR_pat <M2_mpyud_ll_s1, int_hexagon_M2_mpyud_ll_s1>;
 297
 298 //===----------------------------------------------------------------------===//
 299 // MPYS / Multipy signed/unsigned halfwords and add/subtract the
 300 // result from the 64-bit destination register.
 301 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
 302 //===----------------------------------------------------------------------===//
 303
 304 def : T_PRR_pat <M2_mpyd_acc_hh_s0, int_hexagon_M2_mpyd_acc_hh_s0>;
 305 def : T_PRR_pat <M2_mpyd_acc_hl_s0, int_hexagon_M2_mpyd_acc_hl_s0>;
 306 def : T_PRR_pat <M2_mpyd_acc_lh_s0, int_hexagon_M2_mpyd_acc_lh_s0>;
 307 def : T_PRR_pat <M2_mpyd_acc_ll_s0, int_hexagon_M2_mpyd_acc_ll_s0>;
 308
 309 def : T_PRR_pat <M2_mpyd_acc_hh_s1, int_hexagon_M2_mpyd_acc_hh_s1>;
 310 def : T_PRR_pat <M2_mpyd_acc_hl_s1, int_hexagon_M2_mpyd_acc_hl_s1>;
 311 def : T_PRR_pat <M2_mpyd_acc_lh_s1, int_hexagon_M2_mpyd_acc_lh_s1>;
 312 def : T_PRR_pat <M2_mpyd_acc_ll_s1, int_hexagon_M2_mpyd_acc_ll_s1>;
 313
 314 def : T_PRR_pat <M2_mpyd_nac_hh_s0, int_hexagon_M2_mpyd_nac_hh_s0>;
 315 def : T_PRR_pat <M2_mpyd_nac_hl_s0, int_hexagon_M2_mpyd_nac_hl_s0>;
 316 def : T_PRR_pat <M2_mpyd_nac_lh_s0, int_hexagon_M2_mpyd_nac_lh_s0>;
 317 def : T_PRR_pat <M2_mpyd_nac_ll_s0, int_hexagon_M2_mpyd_nac_ll_s0>;
 318
 319 def : T_PRR_pat <M2_mpyd_nac_hh_s1, int_hexagon_M2_mpyd_nac_hh_s1>;
 320 def : T_PRR_pat <M2_mpyd_nac_hl_s1, int_hexagon_M2_mpyd_nac_hl_s1>;
 321 def : T_PRR_pat <M2_mpyd_nac_lh_s1, int_hexagon_M2_mpyd_nac_lh_s1>;
 322 def : T_PRR_pat <M2_mpyd_nac_ll_s1, int_hexagon_M2_mpyd_nac_ll_s1>;
 323
 324 def : T_PRR_pat <M2_mpyud_acc_hh_s0, int_hexagon_M2_mpyud_acc_hh_s0>;
 325 def : T_PRR_pat <M2_mpyud_acc_hl_s0, int_hexagon_M2_mpyud_acc_hl_s0>;
 326 def : T_PRR_pat <M2_mpyud_acc_lh_s0, int_hexagon_M2_mpyud_acc_lh_s0>;
 327 def : T_PRR_pat <M2_mpyud_acc_ll_s0, int_hexagon_M2_mpyud_acc_ll_s0>;
 328
 329 def : T_PRR_pat <M2_mpyud_acc_hh_s1, int_hexagon_M2_mpyud_acc_hh_s1>;
 330 def : T_PRR_pat <M2_mpyud_acc_hl_s1, int_hexagon_M2_mpyud_acc_hl_s1>;
 331 def : T_PRR_pat <M2_mpyud_acc_lh_s1, int_hexagon_M2_mpyud_acc_lh_s1>;
 332 def : T_PRR_pat <M2_mpyud_acc_ll_s1, int_hexagon_M2_mpyud_acc_ll_s1>;
 333
 334 def : T_PRR_pat <M2_mpyud_nac_hh_s0, int_hexagon_M2_mpyud_nac_hh_s0>;
 335 def : T_PRR_pat <M2_mpyud_nac_hl_s0, int_hexagon_M2_mpyud_nac_hl_s0>;
 336 def : T_PRR_pat <M2_mpyud_nac_lh_s0, int_hexagon_M2_mpyud_nac_lh_s0>;
 337 def : T_PRR_pat <M2_mpyud_nac_ll_s0, int_hexagon_M2_mpyud_nac_ll_s0>;
 338
 339 def : T_PRR_pat <M2_mpyud_nac_hh_s1, int_hexagon_M2_mpyud_nac_hh_s1>;
 340 def : T_PRR_pat <M2_mpyud_nac_hl_s1, int_hexagon_M2_mpyud_nac_hl_s1>;
 341 def : T_PRR_pat <M2_mpyud_nac_lh_s1, int_hexagon_M2_mpyud_nac_lh_s1>;
 342 def : T_PRR_pat <M2_mpyud_nac_ll_s1, int_hexagon_M2_mpyud_nac_ll_s1>;
 343
 344 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
 345 def : T_PP_pat <M2_vcmpy_s1_sat_i, int_hexagon_M2_vcmpy_s1_sat_i>;
 346 def : T_PP_pat <M2_vcmpy_s0_sat_i, int_hexagon_M2_vcmpy_s0_sat_i>;
 347
 348 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
 349 def : T_PP_pat <M2_vcmpy_s1_sat_r, int_hexagon_M2_vcmpy_s1_sat_r>;
 350 def : T_PP_pat <M2_vcmpy_s0_sat_r, int_hexagon_M2_vcmpy_s0_sat_r>;
 351
 352 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
 353 def : T_PP_pat <M2_vdmpys_s1, int_hexagon_M2_vdmpys_s1>;
 354 def : T_PP_pat <M2_vdmpys_s0, int_hexagon_M2_vdmpys_s0>;
 355
 356 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
 357 def : T_PP_pat <M2_vmpy2es_s1, int_hexagon_M2_vmpy2es_s1>;
 358 def : T_PP_pat <M2_vmpy2es_s0, int_hexagon_M2_vmpy2es_s0>;
 359
 360 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
 361 def : T_PP_pat <M2_mmpyh_s0,  int_hexagon_M2_mmpyh_s0>;
 362 def : T_PP_pat <M2_mmpyh_s1,  int_hexagon_M2_mmpyh_s1>;
 363 def : T_PP_pat <M2_mmpyh_rs0, int_hexagon_M2_mmpyh_rs0>;
 364 def : T_PP_pat <M2_mmpyh_rs1, int_hexagon_M2_mmpyh_rs1>;
 365
 366 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
 367 def : T_PP_pat <M2_mmpyl_s0,  int_hexagon_M2_mmpyl_s0>;
 368 def : T_PP_pat <M2_mmpyl_s1,  int_hexagon_M2_mmpyl_s1>;
 369 def : T_PP_pat <M2_mmpyl_rs0, int_hexagon_M2_mmpyl_rs0>;
 370 def : T_PP_pat <M2_mmpyl_rs1, int_hexagon_M2_mmpyl_rs1>;
 371
 372 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
 373 def : T_PP_pat <M2_mmpyuh_s0,  int_hexagon_M2_mmpyuh_s0>;
 374 def : T_PP_pat <M2_mmpyuh_s1,  int_hexagon_M2_mmpyuh_s1>;
 375 def : T_PP_pat <M2_mmpyuh_rs0, int_hexagon_M2_mmpyuh_rs0>;
 376 def : T_PP_pat <M2_mmpyuh_rs1, int_hexagon_M2_mmpyuh_rs1>;
 377
 378 //Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat
 379 def : T_PP_pat <M2_mmpyul_s0,  int_hexagon_M2_mmpyul_s0>;
 380 def : T_PP_pat <M2_mmpyul_s1,  int_hexagon_M2_mmpyul_s1>;
 381 def : T_PP_pat <M2_mmpyul_rs0, int_hexagon_M2_mmpyul_rs0>;
 382 def : T_PP_pat <M2_mmpyul_rs1, int_hexagon_M2_mmpyul_rs1>;
 383
 384 // Vector reduce add unsigned bytes: Rdd32[+]=vrmpybu(Rss32,Rtt32)
 385 def : T_PP_pat  <A2_vraddub,     int_hexagon_A2_vraddub>;
 386 def : T_PPP_pat <A2_vraddub_acc, int_hexagon_A2_vraddub_acc>;
 387
 388 // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
 389 def : T_PP_pat  <A2_vrsadub,     int_hexagon_A2_vrsadub>;
 390 def : T_PPP_pat <A2_vrsadub_acc, int_hexagon_A2_vrsadub_acc>;
 391
 392 // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
 393 def : T_PP_pat <M2_vabsdiffh, int_hexagon_M2_vabsdiffh>;
 394
 395 // Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss)
 396 def : T_PP_pat <M2_vabsdiffw, int_hexagon_M2_vabsdiffw>;
 397
 398 // Vector reduce complex multiply real or imaginary:
 399 // Rdd[+]=vrcmpy[ir](Rss,Rtt[*])
 400 def : T_PP_pat  <M2_vrcmpyi_s0,  int_hexagon_M2_vrcmpyi_s0>;
 401 def : T_PP_pat  <M2_vrcmpyi_s0c, int_hexagon_M2_vrcmpyi_s0c>;
 402 def : T_PPP_pat <M2_vrcmaci_s0,  int_hexagon_M2_vrcmaci_s0>;
 403 def : T_PPP_pat <M2_vrcmaci_s0c, int_hexagon_M2_vrcmaci_s0c>;
 404
 405 def : T_PP_pat  <M2_vrcmpyr_s0,  int_hexagon_M2_vrcmpyr_s0>;
 406 def : T_PP_pat  <M2_vrcmpyr_s0c, int_hexagon_M2_vrcmpyr_s0c>;
 407 def : T_PPP_pat <M2_vrcmacr_s0,  int_hexagon_M2_vrcmacr_s0>;
 408 def : T_PPP_pat <M2_vrcmacr_s0c, int_hexagon_M2_vrcmacr_s0c>;
 409
 410 // Vector reduce halfwords
 411 // Rdd[+]=vrmpyh(Rss,Rtt)
 412 def : T_PP_pat  <M2_vrmpy_s0, int_hexagon_M2_vrmpy_s0>;
 413 def : T_PPP_pat <M2_vrmac_s0, int_hexagon_M2_vrmac_s0>;
 414
 415 //===----------------------------------------------------------------------===//
 416 // Vector Multipy with accumulation
 417 //===----------------------------------------------------------------------===//
 418
 419 // Vector multiply word by signed half with accumulation
 420 // Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat
 421 def : T_PPP_pat <M2_mmacls_s1, int_hexagon_M2_mmacls_s1>;
 422 def : T_PPP_pat <M2_mmacls_s0, int_hexagon_M2_mmacls_s0>;
 423 def : T_PPP_pat <M2_mmacls_rs1, int_hexagon_M2_mmacls_rs1>;
 424 def : T_PPP_pat <M2_mmacls_rs0, int_hexagon_M2_mmacls_rs0>;
 425 def : T_PPP_pat <M2_mmachs_s1, int_hexagon_M2_mmachs_s1>;
 426 def : T_PPP_pat <M2_mmachs_s0, int_hexagon_M2_mmachs_s0>;
 427 def : T_PPP_pat <M2_mmachs_rs1, int_hexagon_M2_mmachs_rs1>;
 428 def : T_PPP_pat <M2_mmachs_rs0, int_hexagon_M2_mmachs_rs0>;
 429
 430 // Vector multiply word by unsigned half with accumulation
 431 // Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat
 432 def : T_PPP_pat <M2_mmaculs_s1, int_hexagon_M2_mmaculs_s1>;
 433 def : T_PPP_pat <M2_mmaculs_s0, int_hexagon_M2_mmaculs_s0>;
 434 def : T_PPP_pat <M2_mmaculs_rs1, int_hexagon_M2_mmaculs_rs1>;
 435 def : T_PPP_pat <M2_mmaculs_rs0, int_hexagon_M2_mmaculs_rs0>;
 436 def : T_PPP_pat <M2_mmacuhs_s1, int_hexagon_M2_mmacuhs_s1>;
 437 def : T_PPP_pat <M2_mmacuhs_s0, int_hexagon_M2_mmacuhs_s0>;
 438 def : T_PPP_pat <M2_mmacuhs_rs1, int_hexagon_M2_mmacuhs_rs1>;
 439 def : T_PPP_pat <M2_mmacuhs_rs0, int_hexagon_M2_mmacuhs_rs0>;
 440
 441 // Vector multiply even halfwords with accumulation
 442 // Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat]
 443 def : T_PPP_pat <M2_vmac2es, int_hexagon_M2_vmac2es>;
 444 def : T_PPP_pat <M2_vmac2es_s1, int_hexagon_M2_vmac2es_s1>;
 445 def : T_PPP_pat <M2_vmac2es_s0, int_hexagon_M2_vmac2es_s0>;
 446
 447 // Vector dual multiply with accumulation
 448 // Rxx+=vdmpy(Rss,Rtt)[:sat]
 449 def : T_PPP_pat <M2_vdmacs_s1, int_hexagon_M2_vdmacs_s1>;
 450 def : T_PPP_pat <M2_vdmacs_s0, int_hexagon_M2_vdmacs_s0>;
 451
 452 // Vector complex multiply real or imaginary with accumulation
 453 // Rxx+=vcmpy[ir](Rss,Rtt):sat
 454 def : T_PPP_pat <M2_vcmac_s0_sat_r, int_hexagon_M2_vcmac_s0_sat_r>;
 455 def : T_PPP_pat <M2_vcmac_s0_sat_i, int_hexagon_M2_vcmac_s0_sat_i>;
 456
 457 //===----------------------------------------------------------------------===//
 458 // Add/Subtract halfword
 459 // Rd=add(Rt.L,Rs.[HL])[:sat]
 460 // Rd=sub(Rt.L,Rs.[HL])[:sat]
 461 // Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16]
 462 // Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16]
 463 //===----------------------------------------------------------------------===//
 464
 465 //Rd=add(Rt.L,Rs.[LH])
 466 def : T_RR_pat <A2_addh_l16_ll,     int_hexagon_A2_addh_l16_ll>;
 467 def : T_RR_pat <A2_addh_l16_hl,     int_hexagon_A2_addh_l16_hl>;
 468
 469 //Rd=add(Rt.L,Rs.[LH]):sat
 470 def : T_RR_pat <A2_addh_l16_sat_ll, int_hexagon_A2_addh_l16_sat_ll>;
 471 def : T_RR_pat <A2_addh_l16_sat_hl, int_hexagon_A2_addh_l16_sat_hl>;
 472
 473 //Rd=sub(Rt.L,Rs.[LH])
 474 def : T_RR_pat <A2_subh_l16_ll,     int_hexagon_A2_subh_l16_ll>;
 475 def : T_RR_pat <A2_subh_l16_hl,     int_hexagon_A2_subh_l16_hl>;
 476
 477 //Rd=sub(Rt.L,Rs.[LH]):sat
 478 def : T_RR_pat <A2_subh_l16_sat_ll, int_hexagon_A2_subh_l16_sat_ll>;
 479 def : T_RR_pat <A2_subh_l16_sat_hl, int_hexagon_A2_subh_l16_sat_hl>;
 480
 481 //Rd=add(Rt.[LH],Rs.[LH]):<<16
 482 def : T_RR_pat <A2_addh_h16_ll,     int_hexagon_A2_addh_h16_ll>;
 483 def : T_RR_pat <A2_addh_h16_lh,     int_hexagon_A2_addh_h16_lh>;
 484 def : T_RR_pat <A2_addh_h16_hl,     int_hexagon_A2_addh_h16_hl>;
 485 def : T_RR_pat <A2_addh_h16_hh,     int_hexagon_A2_addh_h16_hh>;
 486
 487 //Rd=sub(Rt.[LH],Rs.[LH]):<<16
 488 def : T_RR_pat <A2_subh_h16_ll,     int_hexagon_A2_subh_h16_ll>;
 489 def : T_RR_pat <A2_subh_h16_lh,     int_hexagon_A2_subh_h16_lh>;
 490 def : T_RR_pat <A2_subh_h16_hl,     int_hexagon_A2_subh_h16_hl>;
 491 def : T_RR_pat <A2_subh_h16_hh,     int_hexagon_A2_subh_h16_hh>;
 492
 493 //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16
 494 def : T_RR_pat <A2_addh_h16_sat_ll, int_hexagon_A2_addh_h16_sat_ll>;
 495 def : T_RR_pat <A2_addh_h16_sat_lh, int_hexagon_A2_addh_h16_sat_lh>;
 496 def : T_RR_pat <A2_addh_h16_sat_hl, int_hexagon_A2_addh_h16_sat_hl>;
 497 def : T_RR_pat <A2_addh_h16_sat_hh, int_hexagon_A2_addh_h16_sat_hh>;
 498
 499 //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16
 500 def : T_RR_pat <A2_subh_h16_sat_ll, int_hexagon_A2_subh_h16_sat_ll>;
 501 def : T_RR_pat <A2_subh_h16_sat_lh, int_hexagon_A2_subh_h16_sat_lh>;
 502 def : T_RR_pat <A2_subh_h16_sat_hl, int_hexagon_A2_subh_h16_sat_hl>;
 503 def : T_RR_pat <A2_subh_h16_sat_hh, int_hexagon_A2_subh_h16_sat_hh>;
 504
 505 // ALU64 / ALU / min max
 506 def : T_RR_pat<A2_max,  int_hexagon_A2_max>;
 507 def : T_RR_pat<A2_min,  int_hexagon_A2_min>;
 508 def : T_RR_pat<A2_maxu, int_hexagon_A2_maxu>;
 509 def : T_RR_pat<A2_minu, int_hexagon_A2_minu>;
 510
 511 // Shift and accumulate
 512 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 513 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 514 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 515 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 516 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 517 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 518
 519 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 520 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 521 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 522 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 523 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 524 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 525 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 526 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 527
 528 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 529 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 530 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 531 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 532 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 533 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 534
 535 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 536 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 537 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 538 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 539 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 540 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 541 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 542 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 543
 544 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 545 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 546 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 547 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 548 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 549 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 550 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 551 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 552
 553 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 554 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 555 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 556 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 557 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 558 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 559 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 560 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 561
 562 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 563 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 564 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 565 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 566 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 567 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 568 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 569 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 570
 571 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 572 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 573 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 574 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 575 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 576 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 577 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 578 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 579
 580 def : T_RRI_pat <S2_asr_i_r_nac,  int_hexagon_S2_asr_i_r_nac>;
 581 def : T_RRI_pat <S2_lsr_i_r_nac,  int_hexagon_S2_lsr_i_r_nac>;
 582 def : T_RRI_pat <S2_asl_i_r_nac,  int_hexagon_S2_asl_i_r_nac>;
 583 def : T_RRI_pat <S2_asr_i_r_acc,  int_hexagon_S2_asr_i_r_acc>;
 584 def : T_RRI_pat <S2_lsr_i_r_acc,  int_hexagon_S2_lsr_i_r_acc>;
 585 def : T_RRI_pat <S2_asl_i_r_acc,  int_hexagon_S2_asl_i_r_acc>;
 586
 587 def : T_RRI_pat <S2_asr_i_r_and,  int_hexagon_S2_asr_i_r_and>;
 588 def : T_RRI_pat <S2_lsr_i_r_and,  int_hexagon_S2_lsr_i_r_and>;
 589 def : T_RRI_pat <S2_asl_i_r_and,  int_hexagon_S2_asl_i_r_and>;
 590 def : T_RRI_pat <S2_asr_i_r_or,   int_hexagon_S2_asr_i_r_or>;
 591 def : T_RRI_pat <S2_lsr_i_r_or,   int_hexagon_S2_lsr_i_r_or>;
 592 def : T_RRI_pat <S2_asl_i_r_or,   int_hexagon_S2_asl_i_r_or>;
 593 def : T_RRI_pat <S2_lsr_i_r_xacc, int_hexagon_S2_lsr_i_r_xacc>;
 594 def : T_RRI_pat <S2_asl_i_r_xacc, int_hexagon_S2_asl_i_r_xacc>;
 595
 596 def : T_PPI_pat <S2_asr_i_p_nac,  int_hexagon_S2_asr_i_p_nac>;
 597 def : T_PPI_pat <S2_lsr_i_p_nac,  int_hexagon_S2_lsr_i_p_nac>;
 598 def : T_PPI_pat <S2_asl_i_p_nac,  int_hexagon_S2_asl_i_p_nac>;
 599 def : T_PPI_pat <S2_asr_i_p_acc,  int_hexagon_S2_asr_i_p_acc>;
 600 def : T_PPI_pat <S2_lsr_i_p_acc,  int_hexagon_S2_lsr_i_p_acc>;
 601 def : T_PPI_pat <S2_asl_i_p_acc,  int_hexagon_S2_asl_i_p_acc>;
 602
 603 def : T_PPI_pat <S2_asr_i_p_and,  int_hexagon_S2_asr_i_p_and>;
 604 def : T_PPI_pat <S2_lsr_i_p_and,  int_hexagon_S2_lsr_i_p_and>;
 605 def : T_PPI_pat <S2_asl_i_p_and,  int_hexagon_S2_asl_i_p_and>;
 606 def : T_PPI_pat <S2_asr_i_p_or,   int_hexagon_S2_asr_i_p_or>;
 607 def : T_PPI_pat <S2_lsr_i_p_or,   int_hexagon_S2_lsr_i_p_or>;
 608 def : T_PPI_pat <S2_asl_i_p_or,   int_hexagon_S2_asl_i_p_or>;
 609 def : T_PPI_pat <S2_lsr_i_p_xacc, int_hexagon_S2_lsr_i_p_xacc>;
 610 def : T_PPI_pat <S2_asl_i_p_xacc, int_hexagon_S2_asl_i_p_xacc>;
 611
 612 def : T_RRR_pat <S2_asr_r_r_nac,  int_hexagon_S2_asr_r_r_nac>;
 613 def : T_RRR_pat <S2_lsr_r_r_nac,  int_hexagon_S2_lsr_r_r_nac>;
 614 def : T_RRR_pat <S2_asl_r_r_nac,  int_hexagon_S2_asl_r_r_nac>;
 615 def : T_RRR_pat <S2_lsl_r_r_nac,  int_hexagon_S2_lsl_r_r_nac>;
 616 def : T_RRR_pat <S2_asr_r_r_acc,  int_hexagon_S2_asr_r_r_acc>;
 617 def : T_RRR_pat <S2_lsr_r_r_acc,  int_hexagon_S2_lsr_r_r_acc>;
 618 def : T_RRR_pat <S2_asl_r_r_acc,  int_hexagon_S2_asl_r_r_acc>;
 619 def : T_RRR_pat <S2_lsl_r_r_acc,  int_hexagon_S2_lsl_r_r_acc>;
 620
 621 def : T_RRR_pat <S2_asr_r_r_and,  int_hexagon_S2_asr_r_r_and>;
 622 def : T_RRR_pat <S2_lsr_r_r_and,  int_hexagon_S2_lsr_r_r_and>;
 623 def : T_RRR_pat <S2_asl_r_r_and,  int_hexagon_S2_asl_r_r_and>;
 624 def : T_RRR_pat <S2_lsl_r_r_and,  int_hexagon_S2_lsl_r_r_and>;
 625 def : T_RRR_pat <S2_asr_r_r_or,   int_hexagon_S2_asr_r_r_or>;
 626 def : T_RRR_pat <S2_lsr_r_r_or,   int_hexagon_S2_lsr_r_r_or>;
 627 def : T_RRR_pat <S2_asl_r_r_or,   int_hexagon_S2_asl_r_r_or>;
 628 def : T_RRR_pat <S2_lsl_r_r_or,   int_hexagon_S2_lsl_r_r_or>;
 629
 630 def : T_PPR_pat <S2_asr_r_p_nac,  int_hexagon_S2_asr_r_p_nac>;
 631 def : T_PPR_pat <S2_lsr_r_p_nac,  int_hexagon_S2_lsr_r_p_nac>;
 632 def : T_PPR_pat <S2_asl_r_p_nac,  int_hexagon_S2_asl_r_p_nac>;
 633 def : T_PPR_pat <S2_lsl_r_p_nac,  int_hexagon_S2_lsl_r_p_nac>;
 634 def : T_PPR_pat <S2_asr_r_p_acc,  int_hexagon_S2_asr_r_p_acc>;
 635 def : T_PPR_pat <S2_lsr_r_p_acc,  int_hexagon_S2_lsr_r_p_acc>;
 636 def : T_PPR_pat <S2_asl_r_p_acc,  int_hexagon_S2_asl_r_p_acc>;
 637 def : T_PPR_pat <S2_lsl_r_p_acc,  int_hexagon_S2_lsl_r_p_acc>;
 638
 639 def : T_PPR_pat <S2_asr_r_p_and,  int_hexagon_S2_asr_r_p_and>;
 640 def : T_PPR_pat <S2_lsr_r_p_and,  int_hexagon_S2_lsr_r_p_and>;
 641 def : T_PPR_pat <S2_asl_r_p_and,  int_hexagon_S2_asl_r_p_and>;
 642 def : T_PPR_pat <S2_lsl_r_p_and,  int_hexagon_S2_lsl_r_p_and>;
 643 def : T_PPR_pat <S2_asr_r_p_or,   int_hexagon_S2_asr_r_p_or>;
 644 def : T_PPR_pat <S2_lsr_r_p_or,   int_hexagon_S2_lsr_r_p_or>;
 645 def : T_PPR_pat <S2_asl_r_p_or,   int_hexagon_S2_asl_r_p_or>;
 646 def : T_PPR_pat <S2_lsl_r_p_or,   int_hexagon_S2_lsl_r_p_or>;
 647
 648 /********************************************************************
 649 *            ALU32/ALU                                              *
 650 *********************************************************************/
 651 def : T_RR_pat<A2_add,      int_hexagon_A2_add>;
 652 def : T_RI_pat<A2_addi,     int_hexagon_A2_addi>;
 653 def : T_RR_pat<A2_sub,      int_hexagon_A2_sub>;
 654 def : T_IR_pat<A2_subri,    int_hexagon_A2_subri>;
 655 def : T_RR_pat<A2_and,      int_hexagon_A2_and>;
 656 def : T_RI_pat<A2_andir,    int_hexagon_A2_andir>;
 657 def : T_RR_pat<A2_or,       int_hexagon_A2_or>;
 658 def : T_RI_pat<A2_orir,     int_hexagon_A2_orir>;
 659 def : T_RR_pat<A2_xor,      int_hexagon_A2_xor>;
 660 def : T_RR_pat<A2_combinew, int_hexagon_A2_combinew>;
 661
 662 // Assembler mapped from Rd32=not(Rs32) to Rd32=sub(#-1,Rs32)
 663 def : Pat <(int_hexagon_A2_not (I32:$Rs)),
 664            (A2_subri -1, IntRegs:$Rs)>;
 665
 666 // Assembler mapped from Rd32=neg(Rs32) to Rd32=sub(#0,Rs32)
 667 def : Pat <(int_hexagon_A2_neg IntRegs:$Rs),
 668            (A2_subri 0, IntRegs:$Rs)>;
 669
 670 // Transfer immediate
 671 def  : Pat <(int_hexagon_A2_tfril (I32:$Rs), u16_0ImmPred:$Is),
 672             (A2_tfril IntRegs:$Rs, u16_0ImmPred:$Is)>;
 673 def  : Pat <(int_hexagon_A2_tfrih (I32:$Rs), u16_0ImmPred:$Is),
 674             (A2_tfrih IntRegs:$Rs, u16_0ImmPred:$Is)>;
 675
 676 //  Transfer Register/immediate.
 677 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 678 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 679 def : T_I_pat <A2_tfrpi, int_hexagon_A2_tfrpi>;
 680
 681 // Assembler mapped from Rdd32=Rss32 to Rdd32=combine(Rss.H32,Rss.L32)
 682 def : Pat<(int_hexagon_A2_tfrp DoubleRegs:$src),
 683           (A2_combinew (HiReg DoubleRegs:$src), (LoReg DoubleRegs:$src))>;
 684
 685 /********************************************************************
 686 *            ALU32/PERM                                             *
 687 *********************************************************************/
 688 // Combine
 689 def: T_RR_pat<A2_combine_hh, int_hexagon_A2_combine_hh>;
 690 def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
 691 def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
 692 def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
 693
 694 def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s8ExtPred, s8ImmPred>;
 695
 696 def: Pat<(i32 (int_hexagon_C2_mux (I32:$Rp), (I32:$Rs), (I32:$Rt))),
 697          (i32 (C2_mux (C2_tfrrp IntRegs:$Rp), IntRegs:$Rs, IntRegs:$Rt))>;
 698
 699 // Mux
 700 def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s8ExtPred>;
 701 def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s8ExtPred>;
 702 def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s8ExtPred, s8ImmPred>;
 703
 704 // Shift halfword
 705 def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
 706 def : T_R_pat<A2_asrh, int_hexagon_A2_asrh>;
 707 def : T_R_pat<A2_asrh, int_hexagon_SI_to_SXTHI_asrh>;
 708
 709 // Sign/zero extend
 710 def : T_R_pat<A2_sxth, int_hexagon_A2_sxth>;
 711 def : T_R_pat<A2_sxtb, int_hexagon_A2_sxtb>;
 712 def : T_R_pat<A2_zxth, int_hexagon_A2_zxth>;
 713 def : T_R_pat<A2_zxtb, int_hexagon_A2_zxtb>;
 714
 715 /********************************************************************
 716 *            ALU32/PRED                                             *
 717 *********************************************************************/
 718 // Compare
 719 def : T_RR_pat<C2_cmpeq,  int_hexagon_C2_cmpeq>;
 720 def : T_RR_pat<C2_cmpgt,  int_hexagon_C2_cmpgt>;
 721 def : T_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
 722
 723 def : T_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s10ExtPred>;
 724 def : T_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s10ExtPred>;
 725 def : T_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u9ExtPred>;
 726
 727 def : Pat <(i32 (int_hexagon_C2_cmpgei (I32:$src1), s8ExtPred:$src2)),
 728       (i32 (C2_cmpgti (I32:$src1),
 729                       (DEC_CONST_SIGNED s8ExtPred:$src2)))>;
 730
 731 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), u8ExtPred:$src2)),
 732       (i32 (C2_cmpgtui (I32:$src1),
 733                        (DEC_CONST_UNSIGNED u8ExtPred:$src2)))>;
 734
 735 // The instruction, Pd=cmp.geu(Rs, #u8) -> Pd=cmp.eq(Rs,Rs) when #u8 == 0.
 736 def : Pat <(i32 (int_hexagon_C2_cmpgeui (I32:$src1), 0)),
 737       (i32 (C2_cmpeq (I32:$src1), (I32:$src1)))>;
 738
 739 def : Pat <(i32 (int_hexagon_C2_cmplt (I32:$src1),
 740                                       (I32:$src2))),
 741       (i32 (C2_cmpgt (I32:$src2), (I32:$src1)))>;
 742
 743 def : Pat <(i32 (int_hexagon_C2_cmpltu (I32:$src1),
 744                                        (I32:$src2))),
 745       (i32 (C2_cmpgtu (I32:$src2), (I32:$src1)))>;
 746
 747 /********************************************************************
 748 *            ALU32/VH                                               *
 749 *********************************************************************/
 750 // Vector add, subtract, average halfwords
 751 def: T_RR_pat<A2_svaddh,   int_hexagon_A2_svaddh>;
 752 def: T_RR_pat<A2_svaddhs,  int_hexagon_A2_svaddhs>;
 753 def: T_RR_pat<A2_svadduhs, int_hexagon_A2_svadduhs>;
 754
 755 def: T_RR_pat<A2_svsubh,   int_hexagon_A2_svsubh>;
 756 def: T_RR_pat<A2_svsubhs,  int_hexagon_A2_svsubhs>;
 757 def: T_RR_pat<A2_svsubuhs, int_hexagon_A2_svsubuhs>;
 758
 759 def: T_RR_pat<A2_svavgh,   int_hexagon_A2_svavgh>;
 760 def: T_RR_pat<A2_svavghs,  int_hexagon_A2_svavghs>;
 761 def: T_RR_pat<A2_svnavgh,  int_hexagon_A2_svnavgh>;
 762
 763 /********************************************************************
 764 *            ALU64/ALU                                              *
 765 *********************************************************************/
 766 def: T_RR_pat<A2_addsat,   int_hexagon_A2_addsat>;
 767 def: T_RR_pat<A2_subsat,   int_hexagon_A2_subsat>;
 768 def: T_PP_pat<A2_addp,     int_hexagon_A2_addp>;
 769 def: T_PP_pat<A2_subp,     int_hexagon_A2_subp>;
 770
 771 def: T_PP_pat<A2_andp,     int_hexagon_A2_andp>;
 772 def: T_PP_pat<A2_orp,      int_hexagon_A2_orp>;
 773 def: T_PP_pat<A2_xorp,     int_hexagon_A2_xorp>;
 774
 775 def: T_PP_pat<C2_cmpeqp,   int_hexagon_C2_cmpeqp>;
 776 def: T_PP_pat<C2_cmpgtp,   int_hexagon_C2_cmpgtp>;
 777 def: T_PP_pat<C2_cmpgtup,  int_hexagon_C2_cmpgtup>;
 778
 779 def: T_PP_pat<S2_parityp,  int_hexagon_S2_parityp>;
 780 def: T_RR_pat<S2_packhl,   int_hexagon_S2_packhl>;
 781
 782 /********************************************************************
 783 *            ALU64/VB                                               *
 784 *********************************************************************/
 785 // ALU64 - Vector add
 786 def : T_PP_pat <A2_vaddub,   int_hexagon_A2_vaddub>;
 787 def : T_PP_pat <A2_vaddubs,  int_hexagon_A2_vaddubs>;
 788 def : T_PP_pat <A2_vaddh,    int_hexagon_A2_vaddh>;
 789 def : T_PP_pat <A2_vaddhs,   int_hexagon_A2_vaddhs>;
 790 def : T_PP_pat <A2_vadduhs,  int_hexagon_A2_vadduhs>;
 791 def : T_PP_pat <A2_vaddw,    int_hexagon_A2_vaddw>;
 792 def : T_PP_pat <A2_vaddws,   int_hexagon_A2_vaddws>;
 793
 794 // ALU64 - Vector average
 795 def : T_PP_pat <A2_vavgub,   int_hexagon_A2_vavgub>;
 796 def : T_PP_pat <A2_vavgubr,  int_hexagon_A2_vavgubr>;
 797 def : T_PP_pat <A2_vavgh,    int_hexagon_A2_vavgh>;
 798 def : T_PP_pat <A2_vavghr,   int_hexagon_A2_vavghr>;
 799 def : T_PP_pat <A2_vavghcr,  int_hexagon_A2_vavghcr>;
 800 def : T_PP_pat <A2_vavguh,   int_hexagon_A2_vavguh>;
 801 def : T_PP_pat <A2_vavguhr,  int_hexagon_A2_vavguhr>;
 802
 803 def : T_PP_pat <A2_vavgw,    int_hexagon_A2_vavgw>;
 804 def : T_PP_pat <A2_vavgwr,   int_hexagon_A2_vavgwr>;
 805 def : T_PP_pat <A2_vavgwcr,  int_hexagon_A2_vavgwcr>;
 806 def : T_PP_pat <A2_vavguw,   int_hexagon_A2_vavguw>;
 807 def : T_PP_pat <A2_vavguwr,  int_hexagon_A2_vavguwr>;
 808
 809 // ALU64 - Vector negative average
 810 def : T_PP_pat <A2_vnavgh,   int_hexagon_A2_vnavgh>;
 811 def : T_PP_pat <A2_vnavghr,  int_hexagon_A2_vnavghr>;
 812 def : T_PP_pat <A2_vnavghcr, int_hexagon_A2_vnavghcr>;
 813 def : T_PP_pat <A2_vnavgw,   int_hexagon_A2_vnavgw>;
 814 def : T_PP_pat <A2_vnavgwr,  int_hexagon_A2_vnavgwr>;
 815 def : T_PP_pat <A2_vnavgwcr, int_hexagon_A2_vnavgwcr>;
 816
 817 // ALU64 - Vector max
 818 def : T_PP_pat <A2_vmaxh,    int_hexagon_A2_vmaxh>;
 819 def : T_PP_pat <A2_vmaxw,    int_hexagon_A2_vmaxw>;
 820 def : T_PP_pat <A2_vmaxub,   int_hexagon_A2_vmaxub>;
 821 def : T_PP_pat <A2_vmaxuh,   int_hexagon_A2_vmaxuh>;
 822 def : T_PP_pat <A2_vmaxuw,   int_hexagon_A2_vmaxuw>;
 823
 824 // ALU64 - Vector min
 825 def : T_PP_pat <A2_vminh,    int_hexagon_A2_vminh>;
 826 def : T_PP_pat <A2_vminw,    int_hexagon_A2_vminw>;
 827 def : T_PP_pat <A2_vminub,   int_hexagon_A2_vminub>;
 828 def : T_PP_pat <A2_vminuh,   int_hexagon_A2_vminuh>;
 829 def : T_PP_pat <A2_vminuw,   int_hexagon_A2_vminuw>;
 830
 831 // ALU64 - Vector sub
 832 def : T_PP_pat <A2_vsubub,   int_hexagon_A2_vsubub>;
 833 def : T_PP_pat <A2_vsububs,  int_hexagon_A2_vsububs>;
 834 def : T_PP_pat <A2_vsubh,    int_hexagon_A2_vsubh>;
 835 def : T_PP_pat <A2_vsubhs,   int_hexagon_A2_vsubhs>;
 836 def : T_PP_pat <A2_vsubuhs,  int_hexagon_A2_vsubuhs>;
 837 def : T_PP_pat <A2_vsubw,    int_hexagon_A2_vsubw>;
 838 def : T_PP_pat <A2_vsubws,   int_hexagon_A2_vsubws>;
 839
 840 // ALU64 - Vector compare bytes
 841 def : T_PP_pat <A2_vcmpbeq,  int_hexagon_A2_vcmpbeq>;
 842 def : T_PP_pat <A4_vcmpbgt,  int_hexagon_A4_vcmpbgt>;
 843 def : T_PP_pat <A2_vcmpbgtu, int_hexagon_A2_vcmpbgtu>;
 844
 845 // ALU64 - Vector compare halfwords
 846 def : T_PP_pat <A2_vcmpheq,  int_hexagon_A2_vcmpheq>;
 847 def : T_PP_pat <A2_vcmphgt,  int_hexagon_A2_vcmphgt>;
 848 def : T_PP_pat <A2_vcmphgtu, int_hexagon_A2_vcmphgtu>;
 849
 850 // ALU64 - Vector compare words
 851 def : T_PP_pat <A2_vcmpweq,  int_hexagon_A2_vcmpweq>;
 852 def : T_PP_pat <A2_vcmpwgt,  int_hexagon_A2_vcmpwgt>;
 853 def : T_PP_pat <A2_vcmpwgtu, int_hexagon_A2_vcmpwgtu>;
 854
 855 // ALU64 / VB / Vector mux.
 856 def : Pat<(int_hexagon_C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
 857           (C2_vmux PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt)>;
 858
 859 // MPY - Multiply and use full result
 860 // Rdd = mpy[u](Rs, Rt)
 861 def : T_RR_pat <M2_dpmpyss_s0, int_hexagon_M2_dpmpyss_s0>;
 862 def : T_RR_pat <M2_dpmpyuu_s0, int_hexagon_M2_dpmpyuu_s0>;
 863
 864 // Complex multiply real or imaginary
 865 def : T_RR_pat <M2_cmpyi_s0,   int_hexagon_M2_cmpyi_s0>;
 866 def : T_RR_pat <M2_cmpyr_s0,   int_hexagon_M2_cmpyr_s0>;
 867
 868 // Complex multiply
 869 def : T_RR_pat <M2_cmpys_s0,   int_hexagon_M2_cmpys_s0>;
 870 def : T_RR_pat <M2_cmpysc_s0,  int_hexagon_M2_cmpysc_s0>;
 871 def : T_RR_pat <M2_cmpys_s1,   int_hexagon_M2_cmpys_s1>;
 872 def : T_RR_pat <M2_cmpysc_s1,  int_hexagon_M2_cmpysc_s1>;
 873
 874 // Vector multiply halfwords
 875 // Rdd=vmpyh(Rs,Rt)[:<<1]:sat
 876 def : T_RR_pat <M2_vmpy2s_s0,  int_hexagon_M2_vmpy2s_s0>;
 877 def : T_RR_pat <M2_vmpy2s_s1,  int_hexagon_M2_vmpy2s_s1>;
 878
 879 // Rxx[+-]= mpy[u](Rs,Rt)
 880 def : T_PRR_pat <M2_dpmpyss_acc_s0, int_hexagon_M2_dpmpyss_acc_s0>;
 881 def : T_PRR_pat <M2_dpmpyss_nac_s0, int_hexagon_M2_dpmpyss_nac_s0>;
 882 def : T_PRR_pat <M2_dpmpyuu_acc_s0, int_hexagon_M2_dpmpyuu_acc_s0>;
 883 def : T_PRR_pat <M2_dpmpyuu_nac_s0, int_hexagon_M2_dpmpyuu_nac_s0>;
 884
 885 // Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat
 886 def : T_PRR_pat <M2_cmacs_s0, int_hexagon_M2_cmacs_s0>;
 887 def : T_PRR_pat <M2_cnacs_s0, int_hexagon_M2_cnacs_s0>;
 888 def : T_PRR_pat <M2_cmacs_s1, int_hexagon_M2_cmacs_s1>;
 889 def : T_PRR_pat <M2_cnacs_s1, int_hexagon_M2_cnacs_s1>;
 890
 891 // Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat
 892 def : T_PRR_pat <M2_cmacsc_s0, int_hexagon_M2_cmacsc_s0>;
 893 def : T_PRR_pat <M2_cnacsc_s0, int_hexagon_M2_cnacsc_s0>;
 894 def : T_PRR_pat <M2_cmacsc_s1, int_hexagon_M2_cmacsc_s1>;
 895 def : T_PRR_pat <M2_cnacsc_s1, int_hexagon_M2_cnacsc_s1>;
 896
 897 // Rxx+=cmpy[ir](Rs,Rt)
 898 def : T_PRR_pat <M2_cmaci_s0, int_hexagon_M2_cmaci_s0>;
 899 def : T_PRR_pat <M2_cmacr_s0, int_hexagon_M2_cmacr_s0>;
 900
 901 // Rxx+=vmpyh(Rs,Rt)[:<<1][:sat]
 902 def : T_PRR_pat <M2_vmac2, int_hexagon_M2_vmac2>;
 903 def : T_PRR_pat <M2_vmac2s_s0, int_hexagon_M2_vmac2s_s0>;
 904 def : T_PRR_pat <M2_vmac2s_s1, int_hexagon_M2_vmac2s_s1>;
 905
 906 /********************************************************************
 907 *            CR                                                     *
 908 *********************************************************************/
 909 class qi_CRInst_qi_pat<InstHexagon Inst, Intrinsic IntID> :
 910   Pat<(i32 (IntID IntRegs:$Rs)),
 911       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs))))>;
 912
 913 class qi_CRInst_qiqi_pat<InstHexagon Inst, Intrinsic IntID> :
 914   Pat<(i32 (IntID IntRegs:$Rs, IntRegs:$Rt)),
 915       (i32 (C2_tfrpr (Inst (C2_tfrrp IntRegs:$Rs), (C2_tfrrp IntRegs:$Rt))))>;
 916
 917 def: qi_CRInst_qi_pat<C2_not,     int_hexagon_C2_not>;
 918 def: qi_CRInst_qi_pat<C2_all8,    int_hexagon_C2_all8>;
 919 def: qi_CRInst_qi_pat<C2_any8,    int_hexagon_C2_any8>;
 920
 921 def: qi_CRInst_qiqi_pat<C2_and,   int_hexagon_C2_and>;
 922 def: qi_CRInst_qiqi_pat<C2_andn,  int_hexagon_C2_andn>;
 923 def: qi_CRInst_qiqi_pat<C2_or,    int_hexagon_C2_or>;
 924 def: qi_CRInst_qiqi_pat<C2_orn,   int_hexagon_C2_orn>;
 925 def: qi_CRInst_qiqi_pat<C2_xor,   int_hexagon_C2_xor>;
 926
 927 // Assembler mapped from  Pd4=Ps4 to Pd4=or(Ps4,Ps4)
 928 def : Pat<(int_hexagon_C2_pxfer_map PredRegs:$src),
 929           (C2_pxfer_map PredRegs:$src)>;
 930
 931 // Multiply 32x32 and use lower result
 932 def : T_RRI_pat <M2_macsip, int_hexagon_M2_macsip>;
 933 def : T_RRI_pat <M2_macsin, int_hexagon_M2_macsin>;
 934 def : T_RRR_pat <M2_maci, int_hexagon_M2_maci>;
 935
 936 // Subtract and accumulate
 937 def : T_RRR_pat <M2_subacc, int_hexagon_M2_subacc>;
 938
 939 // Add and accumulate
 940 def : T_RRR_pat <M2_acci,   int_hexagon_M2_acci>;
 941 def : T_RRR_pat <M2_nacci,  int_hexagon_M2_nacci>;
 942 def : T_RRI_pat <M2_accii,  int_hexagon_M2_accii>;
 943 def : T_RRI_pat <M2_naccii, int_hexagon_M2_naccii>;
 944
 945 // XOR and XOR with destination
 946 def : T_RRR_pat <M2_xor_xacc, int_hexagon_M2_xor_xacc>;
 947
 948 class MType_R32_pat <Intrinsic IntID, InstHexagon OutputInst> :
 949       Pat <(IntID IntRegs:$src1, IntRegs:$src2),
 950            (OutputInst IntRegs:$src1, IntRegs:$src2)>;
 951
 952 // Vector dual multiply with round and pack
 953
 954 def : Pat <(int_hexagon_M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2),
 955            (M2_vdmpyrs_s0 DoubleRegs:$src1, DoubleRegs:$src2)>;
 956
 957 def : Pat <(int_hexagon_M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2),
 958            (M2_vdmpyrs_s1 DoubleRegs:$src1, DoubleRegs:$src2)>;
 959
 960 // Vector multiply halfwords with round and pack
 961
 962 def : MType_R32_pat <int_hexagon_M2_vmpy2s_s0pack, M2_vmpy2s_s0pack>;
 963 def : MType_R32_pat <int_hexagon_M2_vmpy2s_s1pack, M2_vmpy2s_s1pack>;
 964
 965 // Multiply and use lower result
 966 def : MType_R32_pat <int_hexagon_M2_mpyi, M2_mpyi>;
 967 def : T_RI_pat<M2_mpysmi, int_hexagon_M2_mpysmi>;
 968
 969 // Assembler mapped from Rd32=mpyui(Rs32,Rt32) to Rd32=mpyi(Rs32,Rt32)
 970 def : MType_R32_pat <int_hexagon_M2_mpyui, M2_mpyi>;
 971
 972 // Multiply and use upper result
 973 def : MType_R32_pat <int_hexagon_M2_mpy_up, M2_mpy_up>;
 974 def : MType_R32_pat <int_hexagon_M2_mpyu_up, M2_mpyu_up>;
 975 def : MType_R32_pat <int_hexagon_M2_hmmpyh_rs1, M2_hmmpyh_rs1>;
 976 def : MType_R32_pat <int_hexagon_M2_hmmpyl_rs1, M2_hmmpyl_rs1>;
 977 def : MType_R32_pat <int_hexagon_M2_dpmpyss_rnd_s0, M2_dpmpyss_rnd_s0>;
 978
 979 // Complex multiply with round and pack
 980 // Rxx32+=cmpy(Rs32,[*]Rt32:<<1]:rnd:sat
 981 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s0, M2_cmpyrs_s0>;
 982 def : MType_R32_pat <int_hexagon_M2_cmpyrs_s1, M2_cmpyrs_s1>;
 983 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s0, M2_cmpyrsc_s0>;
 984 def : MType_R32_pat <int_hexagon_M2_cmpyrsc_s1, M2_cmpyrsc_s1>;
 985
 986 /********************************************************************
 987 *            STYPE/ALU                                              *
 988 *********************************************************************/
 989 def : T_P_pat <A2_absp, int_hexagon_A2_absp>;
 990 def : T_P_pat <A2_negp, int_hexagon_A2_negp>;
 991 def : T_P_pat <A2_notp, int_hexagon_A2_notp>;
 992
 993 /********************************************************************
 994 *            STYPE/BIT                                              *
 995 *********************************************************************/
 996
 997 // Count leading/trailing
 998 def: T_R_pat<S2_cl0,     int_hexagon_S2_cl0>;
 999 def: T_P_pat<S2_cl0p,    int_hexagon_S2_cl0p>;
1000 def: T_R_pat<S2_cl1,     int_hexagon_S2_cl1>;
1001 def: T_P_pat<S2_cl1p,    int_hexagon_S2_cl1p>;
1002 def: T_R_pat<S2_clb,     int_hexagon_S2_clb>;
1003 def: T_P_pat<S2_clbp,    int_hexagon_S2_clbp>;
1004 def: T_R_pat<S2_clbnorm, int_hexagon_S2_clbnorm>;
1005 def: T_R_pat<S2_ct0,     int_hexagon_S2_ct0>;
1006 def: T_R_pat<S2_ct1,     int_hexagon_S2_ct1>;
1007
1008 // Compare bit mask
1009 def: T_RR_pat<C2_bitsclr,  int_hexagon_C2_bitsclr>;
1010 def: T_RI_pat<C2_bitsclri, int_hexagon_C2_bitsclri>;
1011 def: T_RR_pat<C2_bitsset,  int_hexagon_C2_bitsset>;
1012
1013 // Vector shuffle
1014 def : T_PP_pat <S2_shuffeb, int_hexagon_S2_shuffeb>;
1015 def : T_PP_pat <S2_shuffob, int_hexagon_S2_shuffob>;
1016 def : T_PP_pat <S2_shuffeh, int_hexagon_S2_shuffeh>;
1017 def : T_PP_pat <S2_shuffoh, int_hexagon_S2_shuffoh>;
1018
1019 // Vector truncate
1020 def : T_PP_pat <S2_vtrunewh, int_hexagon_S2_vtrunewh>;
1021 def : T_PP_pat <S2_vtrunowh, int_hexagon_S2_vtrunowh>;
1022
1023 // Linear feedback-shift Iteration.
1024 def : T_PP_pat <S2_lfsp, int_hexagon_S2_lfsp>;
1025
1026 // Vector splice
1027 def : T_PPQ_pat <S2_vsplicerb, int_hexagon_S2_vsplicerb>;
1028 def : T_PPI_pat <S2_vspliceib, int_hexagon_S2_vspliceib>;
1029
1030 // Shift by immediate and add
1031 def : T_RRI_pat<S2_addasl_rrri, int_hexagon_S2_addasl_rrri>;
1032
1033 // Extract bitfield
1034 def : T_PII_pat<S2_extractup,    int_hexagon_S2_extractup>;
1035 def : T_RII_pat<S2_extractu,     int_hexagon_S2_extractu>;
1036 def : T_RP_pat <S2_extractu_rp,  int_hexagon_S2_extractu_rp>;
1037 def : T_PP_pat <S2_extractup_rp, int_hexagon_S2_extractup_rp>;
1038
1039 // Insert bitfield
1040 def : Pat <(int_hexagon_S2_insert_rp IntRegs:$src1, IntRegs:$src2,
1041                                      DoubleRegs:$src3),
1042            (S2_insert_rp IntRegs:$src1, IntRegs:$src2, DoubleRegs:$src3)>;
1043
1044 def : Pat<(i64 (int_hexagon_S2_insertp_rp (I64:$src1),
1045                  (I64:$src2), (I64:$src3))),
1046           (i64 (S2_insertp_rp (I64:$src1), (I64:$src2),
1047                               (I64:$src3)))>;
1048
1049 def : Pat<(int_hexagon_S2_insert IntRegs:$src1, IntRegs:$src2,
1050                                  u5ImmPred:$src3, u5ImmPred:$src4),
1051           (S2_insert IntRegs:$src1, IntRegs:$src2,
1052                      u5ImmPred:$src3, u5ImmPred:$src4)>;
1053
1054 def : Pat<(i64 (int_hexagon_S2_insertp (I64:$src1),
1055                  (I64:$src2), u6ImmPred:$src3, u6ImmPred:$src4)),
1056           (i64 (S2_insertp (I64:$src1), (I64:$src2),
1057                            u6ImmPred:$src3, u6ImmPred:$src4))>;
1058
1059
1060 // Innterleave/deinterleave
1061 def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
1062 def : T_P_pat <S2_deinterleave, int_hexagon_S2_deinterleave>;
1063
1064 // Set/Clear/Toggle Bit
1065 def: T_RI_pat<S2_setbit_i,    int_hexagon_S2_setbit_i>;
1066 def: T_RI_pat<S2_clrbit_i,    int_hexagon_S2_clrbit_i>;
1067 def: T_RI_pat<S2_togglebit_i, int_hexagon_S2_togglebit_i>;
1068
1069 def: T_RR_pat<S2_setbit_r,    int_hexagon_S2_setbit_r>;
1070 def: T_RR_pat<S2_clrbit_r,    int_hexagon_S2_clrbit_r>;
1071 def: T_RR_pat<S2_togglebit_r, int_hexagon_S2_togglebit_r>;
1072
1073 // Test Bit
1074 def: T_RI_pat<S2_tstbit_i,    int_hexagon_S2_tstbit_i>;
1075 def: T_RR_pat<S2_tstbit_r,    int_hexagon_S2_tstbit_r>;
1076
1077 /********************************************************************
1078 *            STYPE/COMPLEX                                          *
1079 *********************************************************************/
1080 // Vector Complex conjugate
1081 def : T_P_pat <A2_vconj, int_hexagon_A2_vconj>;
1082
1083 // Vector Complex rotate
1084 def : T_PR_pat <S2_vcrotate, int_hexagon_S2_vcrotate>;
1085
1086 /********************************************************************
1087 *            STYPE/PERM                                             *
1088 *********************************************************************/
1089
1090 // Vector saturate without pack
1091 def : T_P_pat <S2_vsathb_nopack, int_hexagon_S2_vsathb_nopack>;
1092 def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>;
1093 def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>;
1094 def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
1095
1096 /********************************************************************
1097 *            STYPE/PRED                                             *
1098 *********************************************************************/
1099
1100 // Predicate transfer
1101 def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))),
1102          (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
1103 def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))),
1104          (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
1105
1106 // Mask generate from predicate
1107 def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))),
1108          (i64 (C2_mask (C2_tfrrp (I32:$Rs))))>;
1109
1110 // Viterbi pack even and odd predicate bits
1111 def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))),
1112          (i32 (C2_vitpack (C2_tfrrp (I32:$Rs)),
1113                           (C2_tfrrp (I32:$Rt))))>;
1114
1115 /********************************************************************
1116 *            STYPE/SHIFT                                            *
1117 *********************************************************************/
1118
1119 def : T_PI_pat <S2_asr_i_p, int_hexagon_S2_asr_i_p>;
1120 def : T_PI_pat <S2_lsr_i_p, int_hexagon_S2_lsr_i_p>;
1121 def : T_PI_pat <S2_asl_i_p, int_hexagon_S2_asl_i_p>;
1122
1123 def : T_PR_pat <S2_asr_r_p, int_hexagon_S2_asr_r_p>;
1124 def : T_PR_pat <S2_lsr_r_p, int_hexagon_S2_lsr_r_p>;
1125 def : T_PR_pat <S2_asl_r_p, int_hexagon_S2_asl_r_p>;
1126 def : T_PR_pat <S2_lsl_r_p, int_hexagon_S2_lsl_r_p>;
1127
1128 def : T_RR_pat <S2_asr_r_r, int_hexagon_S2_asr_r_r>;
1129 def : T_RR_pat <S2_lsr_r_r, int_hexagon_S2_lsr_r_r>;
1130 def : T_RR_pat <S2_asl_r_r, int_hexagon_S2_asl_r_r>;
1131 def : T_RR_pat <S2_lsl_r_r, int_hexagon_S2_lsl_r_r>;
1132
1133 def : T_RR_pat <S2_asr_r_r_sat, int_hexagon_S2_asr_r_r_sat>;
1134 def : T_RR_pat <S2_asl_r_r_sat, int_hexagon_S2_asl_r_r_sat>;
1135
1136 def : T_R_pat <S2_vsxtbh,   int_hexagon_S2_vsxtbh>;
1137 def : T_R_pat <S2_vzxtbh,   int_hexagon_S2_vzxtbh>;
1138 def : T_R_pat <S2_vsxthw,   int_hexagon_S2_vsxthw>;
1139 def : T_R_pat <S2_vzxthw,   int_hexagon_S2_vzxthw>;
1140 def : T_R_pat <S2_vsplatrh, int_hexagon_S2_vsplatrh>;
1141 def : T_R_pat <A2_sxtw,     int_hexagon_A2_sxtw>;
1142
1143 // Vector saturate and pack
1144 def : T_R_pat <S2_svsathb,  int_hexagon_S2_svsathb>;
1145 def : T_R_pat <S2_svsathub, int_hexagon_S2_svsathub>;
1146 def : T_P_pat <S2_vsathub,  int_hexagon_S2_vsathub>;
1147 def : T_P_pat <S2_vsatwh,   int_hexagon_S2_vsatwh>;
1148 def : T_P_pat <S2_vsatwuh,  int_hexagon_S2_vsatwuh>;
1149 def : T_P_pat <S2_vsathb,   int_hexagon_S2_vsathb>;
1150
1151 def : T_P_pat <S2_vtrunohb,    int_hexagon_S2_vtrunohb>;
1152 def : T_P_pat <S2_vtrunehb,    int_hexagon_S2_vtrunehb>;
1153 def : T_P_pat <S2_vrndpackwh,  int_hexagon_S2_vrndpackwh>;
1154 def : T_P_pat <S2_vrndpackwhs, int_hexagon_S2_vrndpackwhs>;
1155 def : T_R_pat <S2_brev,        int_hexagon_S2_brev>;
1156 def : T_R_pat <S2_vsplatrb,    int_hexagon_S2_vsplatrb>;
1157
1158 def : T_R_pat <A2_abs,    int_hexagon_A2_abs>;
1159 def : T_R_pat <A2_abssat, int_hexagon_A2_abssat>;
1160 def : T_R_pat <A2_negsat, int_hexagon_A2_negsat>;
1161
1162 def : T_R_pat <A2_swiz,   int_hexagon_A2_swiz>;
1163
1164 def : T_P_pat <A2_sat,    int_hexagon_A2_sat>;
1165 def : T_R_pat <A2_sath,   int_hexagon_A2_sath>;
1166 def : T_R_pat <A2_satuh,  int_hexagon_A2_satuh>;
1167 def : T_R_pat <A2_satub,  int_hexagon_A2_satub>;
1168 def : T_R_pat <A2_satb,   int_hexagon_A2_satb>;
1169
1170 // Vector arithmetic shift right by immediate with truncate and pack.
1171 def : T_PI_pat<S2_asr_i_svw_trun, int_hexagon_S2_asr_i_svw_trun>;
1172
1173 def : T_RI_pat <S2_asr_i_r,     int_hexagon_S2_asr_i_r>;
1174 def : T_RI_pat <S2_lsr_i_r,     int_hexagon_S2_lsr_i_r>;
1175 def : T_RI_pat <S2_asl_i_r,     int_hexagon_S2_asl_i_r>;
1176 def : T_RI_pat <S2_asr_i_r_rnd, int_hexagon_S2_asr_i_r_rnd>;
1177 def : T_RI_pat <S2_asr_i_r_rnd_goodsyntax,
1178                 int_hexagon_S2_asr_i_r_rnd_goodsyntax>;
1179
1180 // Shift left by immediate with saturation.
1181 def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
1182
1183 //===----------------------------------------------------------------------===//
1184 // Template 'def pat' to map tableidx[bhwd] intrinsics to :raw instructions.
1185 //===----------------------------------------------------------------------===//
1186 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
1187                          SDNodeXForm XformImm>
1188   : Pat <(IntID IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
1189          (OutputInst IntRegs:$src1, IntRegs:$src2, u4ImmPred:$src3,
1190                      (XformImm u5ImmPred:$src4))>;
1191
1192
1193 // Table Index : Extract and insert bits.
1194 // Map to the real hardware instructions after subtracting appropriate
1195 // values from the 4th input operand. Please note that subtraction is not
1196 // needed for int_hexagon_S2_tableidxb_goodsyntax.
1197
1198 def : Pat <(int_hexagon_S2_tableidxb_goodsyntax IntRegs:$src1, IntRegs:$src2,
1199                                               u4ImmPred:$src3, u5ImmPred:$src4),
1200            (S2_tableidxb IntRegs:$src1, IntRegs:$src2,
1201                          u4ImmPred:$src3, u5ImmPred:$src4)>;
1202
1203 def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
1204                          DEC_CONST_SIGNED>;
1205 def : S2op_tableidx_pat <int_hexagon_S2_tableidxw_goodsyntax, S2_tableidxw,
1206                          DEC2_CONST_SIGNED>;
1207 def : S2op_tableidx_pat <int_hexagon_S2_tableidxd_goodsyntax, S2_tableidxd,
1208                          DEC3_CONST_SIGNED>;
1209
1210 /********************************************************************
1211 *            STYPE/VH                                               *
1212 *********************************************************************/
1213
1214 // Vector absolute value halfwords with and without saturation
1215 // Rdd64=vabsh(Rss64)[:sat]
1216 def : T_P_pat <A2_vabsh, int_hexagon_A2_vabsh>;
1217 def : T_P_pat <A2_vabshsat, int_hexagon_A2_vabshsat>;
1218
1219 // Vector shift halfwords by immediate
1220 // Rdd64=[vaslh/vasrh/vlsrh](Rss64,u4)
1221 def : T_PI_pat <S2_asr_i_vh, int_hexagon_S2_asr_i_vh>;
1222 def : T_PI_pat <S2_lsr_i_vh, int_hexagon_S2_lsr_i_vh>;
1223 def : T_PI_pat <S2_asl_i_vh, int_hexagon_S2_asl_i_vh>;
1224
1225 // Vector shift halfwords by register
1226 // Rdd64=[vaslw/vasrw/vlslw/vlsrw](Rss64,Rt32)
1227 def : T_PR_pat <S2_asr_r_vh, int_hexagon_S2_asr_r_vh>;
1228 def : T_PR_pat <S2_lsr_r_vh, int_hexagon_S2_lsr_r_vh>;
1229 def : T_PR_pat <S2_asl_r_vh, int_hexagon_S2_asl_r_vh>;
1230 def : T_PR_pat <S2_lsl_r_vh, int_hexagon_S2_lsl_r_vh>;
1231
1232 /********************************************************************
1233 *            STYPE/VW                                               *
1234 *********************************************************************/
1235
1236 // Vector absolute value words with and without saturation
1237 def : T_P_pat <A2_vabsw, int_hexagon_A2_vabsw>;
1238 def : T_P_pat <A2_vabswsat, int_hexagon_A2_vabswsat>;
1239
1240 // Vector shift words by immediate.
1241 // Rdd64=[vasrw/vlsrw|vaslw](Rss64,u5)
1242 def : T_PI_pat <S2_asr_i_vw, int_hexagon_S2_asr_i_vw>;
1243 def : T_PI_pat <S2_lsr_i_vw, int_hexagon_S2_lsr_i_vw>;
1244 def : T_PI_pat <S2_asl_i_vw, int_hexagon_S2_asl_i_vw>;
1245
1246 // Vector shift words by register.
1247 // Rdd64=[vasrw/vlsrw|vaslw|vlslw](Rss64,Rt32)
1248 def : T_PR_pat <S2_asr_r_vw, int_hexagon_S2_asr_r_vw>;
1249 def : T_PR_pat <S2_lsr_r_vw, int_hexagon_S2_lsr_r_vw>;
1250 def : T_PR_pat <S2_asl_r_vw, int_hexagon_S2_asl_r_vw>;
1251 def : T_PR_pat <S2_lsl_r_vw, int_hexagon_S2_lsl_r_vw>;
1252
1253 // Vector shift words with truncate and pack
1254
1255 def : T_PR_pat <S2_asr_r_svw_trun, int_hexagon_S2_asr_r_svw_trun>;
1256
1257 def : T_R_pat<L2_loadw_locked, int_hexagon_L2_loadw_locked>;
1258 def : T_R_pat<L4_loadd_locked, int_hexagon_L4_loadd_locked>;
1259
1260 def: Pat<(i32 (int_hexagon_S2_storew_locked (I32:$Rs), (I32:$Rt))),
1261          (i32 (C2_tfrpr (S2_storew_locked (I32:$Rs), (I32:$Rt))))>;
1262 def: Pat<(i32 (int_hexagon_S4_stored_locked (I32:$Rs), (I64:$Rt))),
1263          (i32 (C2_tfrpr (S4_stored_locked (I32:$Rs), (I64:$Rt))))>;
1264
1265 /********************************************************************
1266 *            ST
1267 *********************************************************************/
1268
1269 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
1270   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
1271         (MI I32:$Rs, Val:$Rt, I32:$Ru)>;
1272
1273 def : T_stb_pat <S2_storerh_pbr_pseudo, int_hexagon_brev_sth,   I32>;
1274 def : T_stb_pat <S2_storerb_pbr_pseudo, int_hexagon_brev_stb,   I32>;
1275 def : T_stb_pat <S2_storeri_pbr_pseudo, int_hexagon_brev_stw,   I32>;
1276 def : T_stb_pat <S2_storerf_pbr_pseudo, int_hexagon_brev_sthhi, I32>;
1277 def : T_stb_pat <S2_storerd_pbr_pseudo, int_hexagon_brev_std,   I64>;
1278
1279 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
1280   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
1281         (MI I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s)>;
1282
1283 def: T_stc_pat<S2_storerb_pci_pseudo, int_hexagon_circ_stb,   s4_0ImmPred, I32>;
1284 def: T_stc_pat<S2_storerh_pci_pseudo, int_hexagon_circ_sth,   s4_1ImmPred, I32>;
1285 def: T_stc_pat<S2_storeri_pci_pseudo, int_hexagon_circ_stw,   s4_2ImmPred, I32>;
1286 def: T_stc_pat<S2_storerd_pci_pseudo, int_hexagon_circ_std,   s4_3ImmPred, I64>;
1287 def: T_stc_pat<S2_storerf_pci_pseudo, int_hexagon_circ_sthhi, s4_1ImmPred, I32>;
1288
1289 include "HexagonIntrinsicsV3.td"
1290 include "HexagonIntrinsicsV4.td"
1291 include "HexagonIntrinsicsV5.td"