1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef HexagonINSTRUCTIONINFO_H
15 #define HexagonINSTRUCTIONINFO_H
17 #include "HexagonRegisterInfo.h"
18 #include "MCTargetDesc/HexagonBaseInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetFrameLowering.h"
21 #include "llvm/Target/TargetInstrInfo.h"
24 #define GET_INSTRINFO_HEADER
25 #include "HexagonGenInstrInfo.inc"
29 class HexagonInstrInfo : public HexagonGenInstrInfo {
30 const HexagonRegisterInfo RI;
31 const HexagonSubtarget& Subtarget;
32 typedef unsigned Opcode_t;
35 explicit HexagonInstrInfo(HexagonSubtarget &ST);
37 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
38 /// such, whenever a client has an instance of instruction info, it should
39 /// always be able to get register info as well (through this method).
41 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
43 /// isLoadFromStackSlot - If the specified machine instruction is a direct
44 /// load from a stack slot, return the virtual or physical register number of
45 /// the destination along with the FrameIndex of the loaded stack slot. If
46 /// not, return 0. This predicate must return 0 if the instruction has
47 /// any side effects other than loading from the stack slot.
48 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
49 int &FrameIndex) const;
51 /// isStoreToStackSlot - If the specified machine instruction is a direct
52 /// store to a stack slot, return the virtual or physical register number of
53 /// the source reg along with the FrameIndex of the loaded stack slot. If
54 /// not, return 0. This predicate must return 0 if the instruction has
55 /// any side effects other than storing to the stack slot.
56 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
57 int &FrameIndex) const;
60 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
61 MachineBasicBlock *&FBB,
62 SmallVectorImpl<MachineOperand> &Cond,
63 bool AllowModify) const;
65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
67 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
68 MachineBasicBlock *FBB,
69 const SmallVectorImpl<MachineOperand> &Cond,
72 virtual bool analyzeCompare(const MachineInstr *MI,
73 unsigned &SrcReg, unsigned &SrcReg2,
74 int &Mask, int &Value) const;
76 virtual void copyPhysReg(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator I, DebugLoc DL,
78 unsigned DestReg, unsigned SrcReg,
81 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator MBBI,
83 unsigned SrcReg, bool isKill, int FrameIndex,
84 const TargetRegisterClass *RC,
85 const TargetRegisterInfo *TRI) const;
87 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
88 SmallVectorImpl<MachineOperand> &Addr,
89 const TargetRegisterClass *RC,
90 SmallVectorImpl<MachineInstr*> &NewMIs) const;
92 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
93 MachineBasicBlock::iterator MBBI,
94 unsigned DestReg, int FrameIndex,
95 const TargetRegisterClass *RC,
96 const TargetRegisterInfo *TRI) const;
98 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
99 SmallVectorImpl<MachineOperand> &Addr,
100 const TargetRegisterClass *RC,
101 SmallVectorImpl<MachineInstr*> &NewMIs) const;
103 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
105 const SmallVectorImpl<unsigned> &Ops,
106 int FrameIndex) const;
108 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
110 const SmallVectorImpl<unsigned> &Ops,
111 MachineInstr* LoadMI) const {
115 unsigned createVR(MachineFunction* MF, MVT VT) const;
117 virtual bool isPredicable(MachineInstr *MI) const;
119 PredicateInstruction(MachineInstr *MI,
120 const SmallVectorImpl<MachineOperand> &Cond) const;
122 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
123 unsigned ExtraPredCycles,
124 const BranchProbability &Probability) const;
126 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
127 unsigned NumTCycles, unsigned ExtraTCycles,
128 MachineBasicBlock &FMBB,
129 unsigned NumFCycles, unsigned ExtraFCycles,
130 const BranchProbability &Probability) const;
132 virtual bool isPredicated(const MachineInstr *MI) const;
133 virtual bool isPredicatedNew(const MachineInstr *MI) const;
134 virtual bool DefinesPredicate(MachineInstr *MI,
135 std::vector<MachineOperand> &Pred) const;
137 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
138 const SmallVectorImpl<MachineOperand> &Pred2) const;
141 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
144 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
145 const BranchProbability &Probability) const;
147 virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
152 virtual DFAPacketizer*
153 CreateTargetScheduleState(const TargetMachine *TM,
154 const ScheduleDAG *DAG) const;
156 virtual bool isSchedulingBoundary(const MachineInstr *MI,
157 const MachineBasicBlock *MBB,
158 const MachineFunction &MF) const;
159 bool isValidOffset(const int Opcode, const int Offset) const;
160 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
161 bool isMemOp(const MachineInstr *MI) const;
162 bool isSpillPredRegOp(const MachineInstr *MI) const;
163 bool isU6_3Immediate(const int value) const;
164 bool isU6_2Immediate(const int value) const;
165 bool isU6_1Immediate(const int value) const;
166 bool isU6_0Immediate(const int value) const;
167 bool isS4_3Immediate(const int value) const;
168 bool isS4_2Immediate(const int value) const;
169 bool isS4_1Immediate(const int value) const;
170 bool isS4_0Immediate(const int value) const;
171 bool isS12_Immediate(const int value) const;
172 bool isU6_Immediate(const int value) const;
173 bool isS8_Immediate(const int value) const;
174 bool isS6_Immediate(const int value) const;
176 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
177 bool isConditionalTransfer(const MachineInstr* MI) const;
178 bool isConditionalALU32 (const MachineInstr* MI) const;
179 bool isConditionalLoad (const MachineInstr* MI) const;
180 bool isConditionalStore(const MachineInstr* MI) const;
181 bool isNewValueInst(const MachineInstr* MI) const;
182 bool isDotNewInst(const MachineInstr* MI) const;
183 bool isDeallocRet(const MachineInstr *MI) const;
184 unsigned getInvertedPredicatedOpcode(const int Opc) const;
185 bool isExtendable(const MachineInstr* MI) const;
186 bool isExtended(const MachineInstr* MI) const;
187 bool isPostIncrement(const MachineInstr* MI) const;
188 bool isNewValueStore(const MachineInstr* MI) const;
189 bool isNewValueJump(const MachineInstr* MI) const;
190 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
193 void immediateExtend(MachineInstr *MI) const;
194 bool isConstExtended(MachineInstr *MI) const;
195 unsigned getAddrMode(const MachineInstr* MI) const;
196 bool isOperandExtended(const MachineInstr *MI,
197 unsigned short OperandNum) const;
198 unsigned short getCExtOpNum(const MachineInstr *MI) const;
199 int getMinValue(const MachineInstr *MI) const;
200 int getMaxValue(const MachineInstr *MI) const;
201 bool NonExtEquivalentExists (const MachineInstr *MI) const;
202 short getNonExtOpcode(const MachineInstr *MI) const;
203 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
204 bool PredOpcodeHasNot(Opcode_t Opcode) const;
207 int getMatchingCondBranchOpcode(int Opc, bool sense) const;